EP1319193A1 - Isolation device between optically conductive areas - Google Patents

Isolation device between optically conductive areas

Info

Publication number
EP1319193A1
EP1319193A1 EP01967526A EP01967526A EP1319193A1 EP 1319193 A1 EP1319193 A1 EP 1319193A1 EP 01967526 A EP01967526 A EP 01967526A EP 01967526 A EP01967526 A EP 01967526A EP 1319193 A1 EP1319193 A1 EP 1319193A1
Authority
EP
European Patent Office
Prior art keywords
elongate
regions
chip
doped
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01967526A
Other languages
German (de)
French (fr)
Inventor
Andrew Alan House
George Frederick Hopper
Ian Edward Day
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lumentum Technology UK Ltd
Original Assignee
Bookham Technology PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0023133A external-priority patent/GB2367187B/en
Application filed by Bookham Technology PLC filed Critical Bookham Technology PLC
Publication of EP1319193A1 publication Critical patent/EP1319193A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083—Constructional arrangements
    • G02B2006/12126—Light absorber
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4246—Bidirectionally operating package structures

Definitions

  • This invention relates to an isolation device for providing optical and electrical isolation between areas of an integrated optical circuit.
  • This invention aims to provide an alternative form of device, which provides both optical and electrical isolation.
  • an isolation device for providing optical and electrical isolation between two optically conductive areas of an integrated optical chip comprising a first elongate region extending across the chip doped with a first dopant material, a second elongate region extending across the chip on one side of the first elongate region and a third elongate region extending across the chip on the opposite side of the first elongate region, the second and third elongate regions being doped with a second dopant material of opposite polarity to the first dopant material so a first diode is formed between the second and first elongate regions and a second diode is formed between the first and third elongate regions, the first and second diodes being connected in series with opposing polarity.
  • Figure 1 is a schematic cross-sectional view through a device according to one embodiment of the invention.
  • Figure 2 is a schematic cross-sectional view through a device according to another embodiment of the invention.
  • Figure 3 is a schematic plan view of a variable optical attenuator incorporating devices such as shown in Figures 1 and 2;
  • Figure 4 is a schematic cross-sectional view through a device according to a further embodiment of the invention.
  • Figures 1 and 2 show devices comprising an n-p-n junction formed in the silicon layer of a silicon-on-insulator (SOI) chip comprises a layer of silicon 1 , separated from a substrate 2 (which may also be of silicon) by an insulating layer 3, e.g. of silicon dioxide.
  • SOI silicon-on-insulator
  • the silicon layer 1 is nominally intrinsic, i.e. with no n or p doping, although in practice it tends to contain a very small amount of p-dopant.
  • Figure 1 shows first and second areas 1A and 1 B of the silicon layer 1 which are separated by an n-p-n junction comprising an elongate p-doped region 4, a first elongate n-doped region 5 on one side thereof and a second elongate p-doped region 6 on the opposite side thereof.
  • the regions 4 and 5 thus form a first pn junction and the regions 4 and 6 form a second pn junction, the two pn junctions being connected in series (by the common p-doped region 4) with opposing polarity.
  • the p-doped region 4 and the n-doped regions 5 and 6 preferably extend down to the oxide layer 3 (which is electrically non-conductive) so there is no undoped silicon path extending from area 1A to area 1 B.
  • the doped regions 4, 5 and 6 may be fabricated by a variety of known methods involving ion implantation and/or diffusing in of dopant and may take forms other than those shown in Figure 1.
  • Each of the n-doped regions 5 and 6 is shown contiguous with the p-doped region 4 so there is no undoped silicon area therebetween. Alternatively, the adjacent regions may overlap to some extent (as shown in Figure 2). Such arrangements are suitable where the applied voltage is relatively low, e.g. 5V, and a compact layout is required.
  • Figure 2 shows an alternative form of device in which a trench 7 is first etched in the silicon layer 1 prior to formation of the n-p-n junctions.
  • the layer of silicon remaining at the base of the trench 7 is thus shallower so making it easier to form the doped regions 4, 5 and 6 through to the oxide layer 3.
  • Figure 2 shows a thin silicon layer remaining beneath the doped regions 4, 5 and 6 but, as indicated above, the doped regions 4, 5 and 6 preferably extend through the entire depth of the silicon layer to the oxide layer 3.
  • the silicon layer 1 may have a thickness (from the surface of the chip to the oxide layer 3) of 4 - 8 microns.
  • the trench 7 is preferably etched to a depth such as to leave a layer of silicon at the base thereof of a thickness of around 2.6 microns.
  • the trench 7 may be etched deeper, or a further trench etched at the base thereof, to reduce the thickness of silicon remaining further so long as the remaining layer of silicon has a sufficient thickness to enable the doped regions 4, 5 and 6 to be formed therein.
  • the trench may be formed at the same time as other etched features on the chip, e.g. p-i-n diodes (see below), so will be subject to the minimum thickness requirements of these features, which might typically be 1 micron.
  • the depth of the trench 7, or the thickness of the silicon layer, in which the n-p-n junction is formed, need not be uniform across the device.
  • An isolation device such as that described above, may be used to provide optical and electrical isolation between selected components of an integrated optical circuit.
  • a variable optical attenuator may comprise 40 or more channels and comprise an array of rib waveguides formed in the silicon layer spaced from each other at a pitch of about 250 microns.
  • Figure 3 shows a plan view of part of such a VOA comprising a plurality of rib waveguides 8 extending across a chip 9.
  • Tapered sections 8A are provided at each end of the waveguides to facilitate a low loss coupling with an optical fibre (not shown).
  • the tapered sections 8A may, for instance, be as described in US6108478.
  • Attenuation devices 10 are provided on each waveguide 8 to provide variable attenuation of the optical signal carried by the waveguide 8.
  • the attenuation device may, for instance, comprise one or more p-i-n diode modulators, e.g. as described in US5757986 or co-pending application No
  • Isolation devices 11 comprising n- p-n junctions as described above are provided between each pair of waveguides 8 to provide electrical and optical isolation between adjacent waveguides and their associated attenuation devices 10.
  • the devices are shown as comprising n-doped regions 11A each side of a p-doped region 11 B as described in relation to Figures 1 and 2.
  • the p-type and n-type regions are preferably separated by a relatively undoped or intrinsic region.
  • Figure 4 shows such a form of device in which a trench 7A is first etched in the silicon layer 1 , prior to formation of n and p-type regions, 5A, 6A and 4A, separated by intrinsic regions 12 so as to form a n-i-p-i-n junction.
  • the n and p-type doped regions preferably extend through the entire depth of the silicon layer to the oxide layer 3 to prevent any current leakage across the junction between the regions 1A and 1 B.
  • the n-i-p-i-n arrangement provides better reverse breakdown characteristics due to the less steep doping concentration gradient between the p and n-doped regions, due to the intrinsic regions 12 therebetween.
  • Figure 4 also shows a cross-section through a p-i-n diode attenuator device 10, such as that described above, on one side of the n-i-p-i-n junction.
  • an isolation device such as that described above between adjacent waveguides can significantly reduce the cross-talk between the channels caused either by stray light passing from one waveguide to another or electrical signals applied to an attenuator 10 on one waveguide affecting the attenuators 10 on adjacent waveguides.
  • a device such as that shown in Figure 1 , Figure 2 or Figure 4 may, typically, have a width (i.e. the width of the n-p-n (or n-i-p-i-n) junction) in the range 20 microns to 50 microns.
  • the n-p-n (or n-i-p-i-n) junction is formed by the elongate regions 4, 5 and 6 which extend a required distance across the optical device. In the example of a VOA mentioned above, they may, for instance, extend the entire length of the chip (as shown in Fig 3), which may be a distance 20 mm or more.
  • n-p-n or n-i-p-i-n
  • n-i-p-i-n may be formed in other types of chip to optically and electrically isolate one are from another, e.g. a lll/V material system or other semiconductor material.
  • a p-n-p (or p-i-n-i-p) junction may be used in place of the n-p-n (or n-i-p-i-n) junctions described. If the nominally intrinsic silicon layer 1 were slightly n-doped, this would be preferred.
  • the p-type dopant may typically comprise boron provided at a dopant level of at least 10 18 cm "3 , e.g., in the range of 10 18 to 10 20 cm "3 , or higher.
  • the n-type dopant may typically comprise phosphorous provided at a dopant level of at least 10 8 cm “3 , e.g., in the range of 10 18 to 10 20 cm “3 , or higher.
  • the dopant concentrations are preferably substantially uniform along the length of the elongate doped regions although, in practice, some variations may occur.

Abstract

An isolation device for providing optical and electrical isolating between optically conductive areas (1A, 1B9 such as parallel waveguides of an integrated optical chip comprising a first elongate region (4) doped with a first dopant material (p+), a second elongate region (5) on one side of the first elongate region (4) and a third elongate region (6) on the opposite side of the first elongate region (4), the second and third elongate regions (5, 6) being doped with a second dopant material (n+) of opposite polarity to the first dopant material (p+) so a first diode is formed between the second and first elongate regions (5, 4) and a second diode is formed between the first and third elongate regions (4, 6), the first and second diodes being connected in series with opposing polarity. The opposing diodes block the passage of electrical current and the doped regions (4, 5, 6) absorb light attempting to pass therethrough.

Description

ISOLATION DEVICE BETWEEN OPTICALLY CONDUCTIVE AREAS
TECHNICAL FIELD
This invention relates to an isolation device for providing optical and electrical isolation between areas of an integrated optical circuit.
BACKGROUND PRIOR ART
It is known to isolate two optically conductive areas of an integrated optical circuit from each other by providing a trench between the two areas. If the trench is empty, optical isolation is provided by reflection of stray light at the interface between the optically conductive area and the trench. It is preferable instead to absorb the stray light by filling the trench with light absorbent material. However, this may have a tendency of reducing the electrical isolation between the two optically conductive areas.
It is also known to absorb stray light by providing dopant in selected areas of an optical chip, e.g. as described in WO-A-99/28772, the disclosure of which is incorporated herein.
This invention aims to provide an alternative form of device, which provides both optical and electrical isolation.
SUMMARY OF THE INVENTION
According to the invention, there is provided an isolation device for providing optical and electrical isolation between two optically conductive areas of an integrated optical chip comprising a first elongate region extending across the chip doped with a first dopant material, a second elongate region extending across the chip on one side of the first elongate region and a third elongate region extending across the chip on the opposite side of the first elongate region, the second and third elongate regions being doped with a second dopant material of opposite polarity to the first dopant material so a first diode is formed between the second and first elongate regions and a second diode is formed between the first and third elongate regions, the first and second diodes being connected in series with opposing polarity.
Preferred and optional features of the invention will be apparent from the following description and from the subsidiary claims of the specification.
BRIEF DESCRIPTION OF DRAWINGS
The invention will now be further described, merely by way of example, with reference to the accompanying drawings, in which: -
Figure 1 is a schematic cross-sectional view through a device according to one embodiment of the invention;
Figure 2 is a schematic cross-sectional view through a device according to another embodiment of the invention; and
Figure 3 is a schematic plan view of a variable optical attenuator incorporating devices such as shown in Figures 1 and 2; and
Figure 4 is a schematic cross-sectional view through a device according to a further embodiment of the invention. BEST MODE OF THE INVENTION
Figures 1 and 2 show devices comprising an n-p-n junction formed in the silicon layer of a silicon-on-insulator (SOI) chip comprises a layer of silicon 1 , separated from a substrate 2 (which may also be of silicon) by an insulating layer 3, e.g. of silicon dioxide.
The silicon layer 1 is nominally intrinsic, i.e. with no n or p doping, although in practice it tends to contain a very small amount of p-dopant. Figure 1 shows first and second areas 1A and 1 B of the silicon layer 1 which are separated by an n-p-n junction comprising an elongate p-doped region 4, a first elongate n-doped region 5 on one side thereof and a second elongate p-doped region 6 on the opposite side thereof. The regions 4 and 5 thus form a first pn junction and the regions 4 and 6 form a second pn junction, the two pn junctions being connected in series (by the common p-doped region 4) with opposing polarity. It will be appreciated that current may flow through a forward biased pn junction but not through a reverse biased pn junction. Thus, even if an electrical potential exists between the first area 1 A and the second area 1 B, no current can flow therebetween through the regions 4, 5 and 6 as this potential will reverse bias one of the pn junctions. The n-p-n junction thus electrically isolates the first area 1A from the second area 1 B. Furthermore, the dopant provided within the regions 4, 5 and 6 absorbs stray light attempting to pass either from area 1 A to area 1 B or vice versa. The n-p-n junction thus also effectively optically isolates the area 1A from the area 1 B.
As shown in Figure 1 , the p-doped region 4 and the n-doped regions 5 and 6 preferably extend down to the oxide layer 3 (which is electrically non-conductive) so there is no undoped silicon path extending from area 1A to area 1 B. The doped regions 4, 5 and 6 may be fabricated by a variety of known methods involving ion implantation and/or diffusing in of dopant and may take forms other than those shown in Figure 1. Each of the n-doped regions 5 and 6 is shown contiguous with the p-doped region 4 so there is no undoped silicon area therebetween. Alternatively, the adjacent regions may overlap to some extent (as shown in Figure 2). Such arrangements are suitable where the applied voltage is relatively low, e.g. 5V, and a compact layout is required.
Figure 2 shows an alternative form of device in which a trench 7 is first etched in the silicon layer 1 prior to formation of the n-p-n junctions. The layer of silicon remaining at the base of the trench 7 is thus shallower so making it easier to form the doped regions 4, 5 and 6 through to the oxide layer 3.
Figure 2 shows a thin silicon layer remaining beneath the doped regions 4, 5 and 6 but, as indicated above, the doped regions 4, 5 and 6 preferably extend through the entire depth of the silicon layer to the oxide layer 3.
In a typical SOI chip, the silicon layer 1 may have a thickness (from the surface of the chip to the oxide layer 3) of 4 - 8 microns. The trench 7 is preferably etched to a depth such as to leave a layer of silicon at the base thereof of a thickness of around 2.6 microns.
The trench 7 may be etched deeper, or a further trench etched at the base thereof, to reduce the thickness of silicon remaining further so long as the remaining layer of silicon has a sufficient thickness to enable the doped regions 4, 5 and 6 to be formed therein. However, in practice, the trench may be formed at the same time as other etched features on the chip, e.g. p-i-n diodes (see below), so will be subject to the minimum thickness requirements of these features, which might typically be 1 micron. The depth of the trench 7, or the thickness of the silicon layer, in which the n-p-n junction is formed, need not be uniform across the device.
An isolation device such as that described above, may be used to provide optical and electrical isolation between selected components of an integrated optical circuit. In particular, it may be used between adjacent optical waveguides. For instance, a variable optical attenuator (VOA) may comprise 40 or more channels and comprise an array of rib waveguides formed in the silicon layer spaced from each other at a pitch of about 250 microns. Figure 3 shows a plan view of part of such a VOA comprising a plurality of rib waveguides 8 extending across a chip 9. Tapered sections 8A are provided at each end of the waveguides to facilitate a low loss coupling with an optical fibre (not shown). The tapered sections 8A may, for instance, be as described in US6108478. Attenuation devices 10 are provided on each waveguide 8 to provide variable attenuation of the optical signal carried by the waveguide 8. The attenuation device may, for instance, comprise one or more p-i-n diode modulators, e.g. as described in US5757986 or co-pending application No
GB0019771.5 (Publication No ). Isolation devices 11 comprising n- p-n junctions as described above are provided between each pair of waveguides 8 to provide electrical and optical isolation between adjacent waveguides and their associated attenuation devices 10. The devices are shown as comprising n-doped regions 11A each side of a p-doped region 11 B as described in relation to Figures 1 and 2.
In a further embodiment, especially where the electrical isolation to high voltages is required, e.g., in excess of 90V, the p-type and n-type regions are preferably separated by a relatively undoped or intrinsic region. Figure 4 shows such a form of device in which a trench 7A is first etched in the silicon layer 1 , prior to formation of n and p-type regions, 5A, 6A and 4A, separated by intrinsic regions 12 so as to form a n-i-p-i-n junction. As previously indicated, the n and p-type doped regions preferably extend through the entire depth of the silicon layer to the oxide layer 3 to prevent any current leakage across the junction between the regions 1A and 1 B. The n-i-p-i-n arrangement provides better reverse breakdown characteristics due to the less steep doping concentration gradient between the p and n-doped regions, due to the intrinsic regions 12 therebetween.
Figure 4 also shows a cross-section through a p-i-n diode attenuator device 10, such as that described above, on one side of the n-i-p-i-n junction.
The provision of an isolation device such as that described above between adjacent waveguides can significantly reduce the cross-talk between the channels caused either by stray light passing from one waveguide to another or electrical signals applied to an attenuator 10 on one waveguide affecting the attenuators 10 on adjacent waveguides.
A device such as that shown in Figure 1 , Figure 2 or Figure 4, may, typically, have a width (i.e. the width of the n-p-n (or n-i-p-i-n) junction) in the range 20 microns to 50 microns. The n-p-n (or n-i-p-i-n) junction is formed by the elongate regions 4, 5 and 6 which extend a required distance across the optical device. In the example of a VOA mentioned above, they may, for instance, extend the entire length of the chip (as shown in Fig 3), which may be a distance 20 mm or more.
It will be appreciated that a similar n-p-n (or n-i-p-i-n) junction may be formed in other types of chip to optically and electrically isolate one are from another, e.g. a lll/V material system or other semiconductor material.
A p-n-p (or p-i-n-i-p) junction may be used in place of the n-p-n (or n-i-p-i-n) junctions described. If the nominally intrinsic silicon layer 1 were slightly n-doped, this would be preferred. The p-type dopant may typically comprise boron provided at a dopant level of at least 1018 cm"3, e.g., in the range of 1018 to 1020 cm"3, or higher.
The n-type dopant may typically comprise phosphorous provided at a dopant level of at least 10 8 cm"3, e.g., in the range of 1018 to 1020 cm"3, or higher.
The dopant concentrations are preferably substantially uniform along the length of the elongate doped regions although, in practice, some variations may occur.

Claims

1. According to the invention, there is provided an isolation device for providing optical and electrical isolation between two optically conductive areas of an integrated optical chip comprising a first elongate region extending across the chip doped with a first dopant material, a second elongate region extending across the chip on one side of the first elongate region and a third elongate region extending across the chip on the opposite side of the first elongate region, the second and third elongate regions being doped with a second dopant material of opposite polarity to the first dopant material so a first diode is formed between the second and first elongate regions and a second diode is formed between the first and third elongate regions, the first and second diodes being connected in series with opposing polarity.
2. A device as claimed in claim 1 comprising an optically conductive layer formed over an electrically non-conductive layer, the first, second and third doped regions extending through the optically conductive layer to the electrically non-conductive layer.
3. A device as claimed in claim 1 or 2 formed at the base of a trench formed in the surface of the optical chip.
4. A device as claimed in claim 1 , 2 or 3 in which the second, first and third elongate regions form an n-p-n junction.
5. A device as claimed in any preceding claim in which the first elongate region is separated from both the second and third elongate regions by a relatively undoped region.
6. A device as claimed in any preceding claim formed on a silicon-on-insulator chip comprising a layer of silicon separated from a substrate by a layer of insulating material.
7. A device as claimed in claim 6 formed between two rib waveguides formed in the silicon layer.
8. An isolation device substantially as hereinbefore described with reference to and/or as shown in Figure 1 and/or Figure 2 and/or Figure 4 of the accompanying drawings.
9. An optical device comprising an array of waveguides with a device as claimed in any of claims 1-8 provided between adjacent waveguides.
10. An optical device substantially as hereinbefore described with reference to and/or as shown in Figure 3 of the accompanying drawings.
EP01967526A 2000-09-21 2001-09-20 Isolation device between optically conductive areas Withdrawn EP1319193A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
GB0023133 2000-09-21
GB0023133A GB2367187B (en) 2000-09-21 2000-09-21 An isolation device
US850060 2001-05-08
US09/850,060 US6628852B2 (en) 2000-09-21 2001-05-08 Isolation device
PCT/GB2001/004191 WO2002025334A1 (en) 2000-09-21 2001-09-20 Isolation device between optically conductive areas

Publications (1)

Publication Number Publication Date
EP1319193A1 true EP1319193A1 (en) 2003-06-18

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EP01967526A Withdrawn EP1319193A1 (en) 2000-09-21 2001-09-20 Isolation device between optically conductive areas

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EP (1) EP1319193A1 (en)
CN (1) CN1461418A (en)
AU (1) AU2001287900A1 (en)
CA (1) CA2422572A1 (en)
WO (1) WO2002025334A1 (en)

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Publication number Priority date Publication date Assignee Title
CN102403321A (en) * 2011-09-30 2012-04-04 上海新傲科技股份有限公司 Semiconductor device and preparation method thereof
US9946023B2 (en) * 2015-08-05 2018-04-17 Huawei Technologies Co., Ltd. Optical attenuator and fabrication method thereof
CN114898791A (en) 2016-01-29 2022-08-12 三星电子株式会社 Semiconductor device for selectively performing isolation function and layout replacement method thereof
CN107039070B (en) 2016-01-29 2022-06-14 三星电子株式会社 Semiconductor device for selectively performing isolation function and layout replacement method thereof
US11442296B2 (en) 2020-07-20 2022-09-13 Taiwan Semiconductor Manufacturing Company Ltd. Waveguide structure and method for forming the same
US20240012199A1 (en) * 2022-07-08 2024-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of formation

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FR2710455B1 (en) * 1993-09-24 1995-12-15 Frederic Ghirardi Method for producing a monolithic integrated structure incorporating opto-electronic components and structure thus produced.
EP0704913B1 (en) * 1994-09-28 1999-09-01 Nippon Telegraph And Telephone Corporation Optical semiconductor device and method of fabricating the same
JPH08116135A (en) * 1994-10-17 1996-05-07 Mitsubishi Electric Corp Manufacture of waveguiding path integrated element and waveguiding path integrated element

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Title
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Also Published As

Publication number Publication date
WO2002025334B1 (en) 2002-07-04
AU2001287900A1 (en) 2002-04-02
CA2422572A1 (en) 2002-03-28
WO2002025334A1 (en) 2002-03-28
CN1461418A (en) 2003-12-10

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