GB2385145A

GB2385145A - A diode structure

Info

Publication number: GB2385145A
Application number: GB0207215A
Authority: GB
Inventors: Andrew Alan House; Ian Edward Day; Sara Otero Barros
Original assignee: Bookham Technology PLC
Current assignee: Lumentum Technology UK Ltd
Priority date: 2001-12-19
Filing date: 2002-03-27
Publication date: 2003-08-13
Also published as: GB0130274D0; GB2383425A; GB0207215D0

Abstract

A diode structure within an integrated optical device comprising a waveguide layer 1, of optically conductive material separated from a supporting substrate 2, by an optical confinement layer 3. A first relatively highly doped region 4 extends from the surface of the waveguide layer 1, remote from the confinement layer 3, partway into the waveguide layer 1. The highly doped region 4 is separated from a second relatively highly doped region 5, in a direction normal to the plane of the waveguide layer 1, by an intrinsic or relatively lightly doped region 1. The diode structure provides for a system wherein the majority of the optical mode is situated in a region of intrinsic or relatively lightly doped conductive material which is optically less lossy than doped waveguides.

Description

A DIODE STRUCTURE

This Invention relates to a diode structure within an integrated optical device.

It is known to form pnjunction devices situated in waveguides to provide modulation, either by forward (free-carrier effect) or reverse (depletion) biasing. In such devices, the anode/cathode may be a top contact in the waveguide and the cathode/anode an extended region in a lower slab layer that is electrically interconnected via a substrate electrode. The disadvantage of such devices is that the optical mode is situated in and/or extends into regions of doped semiconductor material, which makes such devices optically lossy and electrical connection with the substrate is not always convenient.

US5757986 discloses a method for manufacturing an electro-optic device comprising lateral pin diode structures in a silicon-on-insulator (SOI) chip.

The present invention aims to provide an alternative pin diode structure wherein at least a majority of the optical mode is situated in a region of undoped, intrinsic silicon which is less optically lossy than a doped waveguide structure of the type discussed above, and without requiring electrical connection to the substrate.

The present invention may also be used in the construction of free carrier prisms, e.g. as disclosed in the GB application number 0130274.4, the disclosure of which is incorporated herein.

According to a find aspect of the invention, there is provided a diode structure within an integrated optical device comprising: a waveguide layer of optically conductive material separated from a supporting substrate by an optical confinement layer;

a first relatively highly doped region extending from a surface of the waveguide layer remote from said confinement layer part way into said waveguide layer and separated in a direction normal to the plane of the waveguide layer by an intrinsic or relatively lightly doped region from a second relatively highly doped region within said waveguide region.

According to a second aspect of the invention there is provided an isolation device for providing optical and electrical isolation between two areas of an integrated optical chip, each area comprising a diode structure as described above and a first elongate region extending across the chip doped with a first dopant material, a second elongate region extending across the chip on one side of the first elongate region and a third elongate region extending across the chip on the opposite side of the first elongate region, the second and third regions being doped with a second dopant material of opposite polarity to the first dopant material so a first lateral diode is formed between the second and first elongate regions and a second lateral diode is formed between the first and third elongate regions, the first and second diodes being connected in series with opposing polarity.

According to a third aspect of the invention there is provided a vertical pin diode structure in a silicon waveguide layer separated from a substrate by an optical confinement layer, comprising doped regions arranged above and below each-other in a direction perpendicular to the plane of the waveguide layer. The term vertical is used herein to refer to a direction perpendicular to the plane of the device and the term lateral to directions within the plane of the device. Preferred and optional features of the invention will be apparent from the following description and from the subsidiary claims of the specification.

The invention will now be further described, merely by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic cross-sectional view through a device according to one embodiment of the invention; and Figure 2 is a schematic cross-sectional view through a device according to a second embodiment of the invention.

Figure 1 shows a vertical pin diode structure comprising a waveguide layer of optically conductive material 1, e.g. of silicon, separated from a supporting substrate 2 (which may also be of silicon) by an optical confinement layer 3, e.g. of silicon dioxide or silicon nitrate.

The silicon layer 1 is nominally intrinsic, i.e. with no n- or p- doping, although in practice it tends to contain a small amount of p-dopant (or ndopant).

Figure 1 shows a highly doped region 4, formed in an upper surface 1A of the silicon layer 1 remote from the optical confinement layer 3, and a second highly doped region 5 within the silicon layer 1 adjacent the optical confinement layer 3. The doped region 4 may be introduced through any exposed surface of the silicon layer, including the top surface 1D of the slab i region and top and/or side surfaces 1A, 1 C of a rib region. An electrode 7 provides electrical contact with the doped region 4. A passivating oxide layer (not shown) would also be provided over the surface of the silicon layer 1.

The first and second highly doped regions are separated from each other in a direction normal to the plane of the silicon layer 1 by an intrinsic or relatively lightly doped region 1 B of the silicon layer 1.

Although the first highly doped region 4 is shown as being p-type and the second highly doped region 5 is shown as being e-type, such that a vertical

diode of the type p-i-n is formed, the person skilled in the art will realise that the polarity may be reversed to form a n-i-p diode.

A similar structure may also be used with the two doped areas being of the same polarity, e.g. to form a n-i-n or p-i-p structure and such arrangements are to be understood to be covered by the term 'diode' as used herein even though they are better described as resistors and/or heaters.

The doped region 5 may be introduced by doping the surface of a silicon wafer, then bonding the wafer with said doped surface facing the SiO2 layer of a SiO2 on silicon wafer. Another method of manufacture is to dope the top surface of a conventional Sol wafer, then epitaxiaily grow an undoped silicon waveguiding layer on top, such that the highly doped layer is buried. The waveguiding elements are then formed in a conventional fashion. Other methods of forming the doped region 5 can also be used. The doped region 5 is shown to be adjacent the optical confinement layer 3, however, it may also be formed so that it is separated from the optical confinement layer 3, e.g. by an intrinsic silicon layer.

As mentioned previously, confinement of the optical mode by doping tends to lead to lossy waveguides due to the evanescent "tail" of the mode extending into the doped regions. The doped layer 5 is thus preferably formed as a thin layer, e.g. in the range 0.1 to 0.5 microns, and preferably around 0.2 microns, which minimises its interaction with the optical mode and hence reduces optical losses, the oxide layer being the primary means of optical confinement in the vertical direction.

Although, in the above example the diode structure is formed in a rib waveguide device, this type of vertical diode structure can also be used in a slab waveguiding region, i.e. with no rib or ridge portions.

A diode structure such as that described above may be used in a wide variety of devices and applications. It may, for example, be used in conjunction with an isolation device such as described in patent application no. PCT/GB01/04191 (the disclosure of which is incorporated herein) to provide

optical and electrical isolation between adjacent optical waveguides (or other optical devices). For instance, a variable optical attenuator (VOA) may comprise 40 or more channels and comprise an array of rib waveguides formed in the silicon layer spaced from each other at a pitch of about 250 microns. Figure 2 shows a cross-sectional view of part of such a VOA comprising a plurality of rib waveguides, of which two, 10 and 20, are shown, with an attenuator in each waveguide formed by a vertical modulator diode having the structure described above. The dashed line M is shown to separate the two optical waveguide devices. Highly doped regions 4, are separated from a highly doped region 5, comprising material of the opposite polarity to regions 4, by intrinsic or relatively lightly doped regions 1 B. The device also comprises a lateral n-p-n (or n-i-p-i-n) junction formed by elongate highly doped regions 30, 31 and 32 which extend parallel to the waveguides 20, 30. The doped regions 30, 31 and 32 extend in a vertical direction between the doped region 5 and the upper surface of the silicon layer 1, such that they provide optical and electrical isolation between the two waveguides 10 and 20. The optical modes 11 and 21 are thus confined in an intrinsic silicon layer 1B and the waveguide and associated attenuators are optically and electrically isolated from each other by the highly doped regions 30, 31 and 32.

As in the above device, the lower highly doped region 5 may be used as a common ground between two or more vertical diodes. Electrical contact with the lower doped region 5 may be provided via etch holes which are laterally remote from the device, or at the edge of the chip, such that neither the oxide layer 3 or substrate 2 is interrupted.

It will be appreciated that a similar n-p-n (or n-i-p-i-n) junction may be formed in other types of chip to optically and electrically isolate one area from another, e.g. a IIIN material system or other semiconductor material.

A p-n-p (or p-i-n-i-p) junction may be used in place of the n-p-n (or n-ip-i-n) junctions described.

The p-doped regions 4 and 31 may typically comprise boron provided at a dopant level of at least 1043 cm-3, e.g. in the range of 10'8 to 102 cm 3, or h igher.

The e-doped regions 5, 30 and 32 may typically comprise phosphorous provided at a dopant level of at least 10'3 cm-3, e.g. in the range of 10'i3 to 1 o20 cm 3, or higher.

Claims

1. A diode structure within an integrated optical device comprising: a waveguide layer of optically conductive material separated frorr a supporting substrate by an optical confinement layer; a first relatively highly doped region extending from a surface of the waveguide layer remote from said confinement layer part way into said waveguide layer and separated in a direction normal to the plane of the waveguide layer by an intrinsic or relatively lightly doped region from a second relatively highly doped region within said waveguide layer.

2. A diode structure as claimed in claim 1 in which one of the first and second highly doped regions is p-doped and the other is e-doped.

3. A diode structure as claimed in claim 1 or 2 in which said second highly doped region comprises a layer remote from said surface of the waveguide layer.

4. A diode structure as claimed in claim 3 in which said second highly doped region is adjacent said optical confinement layer.

5. A diode structure as claimed in any preceding claim in which the optical confinement layer comprises an oxide or a nitride.

6. A diode structure as claimed in any preceding claim in which the waveguide layer comprises silicon.

7. An isolation device for providing optical and electrical isolation between two areas of an integrated optical chip, each area

comprising a diode structure according to any preceding claim, the device comprising a first elongate region extending across the chip doped with a first dopant material, a second elongate region extending across the chip on one side of the first elongate region and a third elongate region extending across the chip on the opposite side of the first elongate region, the second and third regions being doped with a second dopant material of opposite polarity to the first dopant material so a first lateral diode is formed between the second and first elongate regions and a second lateral diode is formed between the first and third elongate regions, the first and second diodes being connected in series with opposing polarity to provide optical and electrical isolation between said diode structures.

8. A device as claimed in claim 7, comprising an optically conductive layer formed over a highly doped layer forming the second highly doped region of said diode structures, the first, second and third doped regions extending through the optically conductive layer to the highly doped layer.

9. A device as claimed in claim 7 or 8, in which the second, first and third elongate regions form a lateral n-p-n junction.

10.A device as claimed in claim 7, 8 or 9 in which the first elongate region is separated from both the second and third elongate regions by a relatively undoped region.

11. A vertical pin diode structure in a silicon waveguide layer separated from a substrate by an optical confinement layer, comprising doped regions arranged above and below each other in a direction perpendicular to the plane of the waveguide layer.

12.A diode structure substantially as hereinbefore described with reference to and/or as shown in one or more of the accompanying drawings.