EP1310852A2 - System with a current source and associated serial switch - Google Patents

Abstract

A PMOS transistor (P2) acting as a switch is connected in series with another PMOS transistor (P1) acting as a source. A controller ensures that potential established on the current source side terminal of the switch during open state of switch is similar to the potential during the closed state of switch.

Description

The present invention relates to a device according to the Preamble of claim 1, i.e. an arrangement with a power source and one connected in series to it Switch.

• wobei der erste Transistor P1 ein PMOS-Transistor ist, dessen Source-Anschluß mit dem positiven Pol VDD einer die Anordnung mit Energie versorgenden Versorgungsspannung verbunden ist, und welcher durch ein Signal icp_refp gesteuert wird,
• wobei der zweite Transistor P2 ein PMOS-Transistor ist, dessen Source-Anschluß mit dem Drain-Anschluß des ersten Transistors P1 verbunden ist, und welcher durch ein Signal upq gesteuert wird,
• wobei der dritte Transistor N1 ein NMOS-Transistor ist, dessen Drain-Anschluß mit dem Drain-Anschluß des zweiten Transistors P2 verbunden ist, und welcher durch ein Signal down gesteuert wird, und
• wobei der vierte Transistor N2 ein NMOS-Transistor ist, dessen Drain-Anschluß mit dem Source-Anschluß des dritten Transistors N1 verbunden ist, dessen Source-Anschluß mit dem negativen Pol VSS einer die Anordnung mit Energie versorgenden Versorgungsspannung verbunden ist, und welcher durch ein Signal ipc_refn gesteuert wird.

Such an arrangement is shown in FIG. 2. The arrangement shown in FIG. 2 contains four transistors P1, P2, N1 and N2 connected in series,

• the first transistor P1 being a PMOS transistor, the source connection of which is connected to the positive pole VDD of a supply voltage supplying the arrangement with energy, and which is controlled by a signal icp_refp,
• wherein the second transistor P2 is a PMOS transistor, the source connection of which is connected to the drain connection of the first transistor P1 and which is controlled by a signal upq,
• wherein the third transistor N1 is an NMOS transistor, the drain connection of which is connected to the drain connection of the second transistor P2 and which is controlled by a signal down, and
• wherein the fourth transistor N2 is an NMOS transistor, the drain connection of which is connected to the source connection of the third transistor N1, the source connection of which is connected to the negative pole VSS of a supply voltage supplying the arrangement with energy, and which through a Signal ipc_refn is controlled.

The signal upq controlling the transistor P2 is the output signal one by a PMOS transistor P3 and an NMOS transistor N3 formed inverter INV1, which is fed to it Incr signal inverted.

The signal down controlling the transistor N1 is the output signal one by a PMOS transistor P4 and an NMOS transistor N4 formed inverter INV2, which is fed to it Output signal one through a PMOS transistor P5 and an inverter INV3 formed by an NMOS transistor N5, which in turn decr a signal supplied to it inverted.

The transistors P1 and N2 are controlled by the ones that control them Signals icp_refp or icp_refn are controlled so that they a current source is formed in each case, the one of these Current sources emitted currents through the transistors controlling signals icp_refp or icp_refn to the desired ones Values are adjustable. Transistors P1 and N2 are also in the following for the sake of clarity referred to as current sources P1 and N2.

The transistors P2 and N1 are driven by the ones that drive them Signals upq and down (incr and decr) controlled so that a switch is formed by them, this Switch open depending on the signals upq or down and can be closed. Transistors P2 and N1 are used in the following for the sake of clarity also referred to as switches P2 and N1.

The arrangement has an output connection O, which with a point connected between the switches P2 and N1 and via which an output signal icp is output becomes.

• wird der von der Stromquelle P1 erzeugte Strom ausgegeben, wenn und so lange der Schalter P2 geschlossen ist (der den Schalter bildende Transistor P2 sich im leitenden Zustand befindet),
• wird der von der Stromquelle N2 erzeugte Strom ausgegeben, wenn und so lange der Schalter N1 geschlossen ist (der den Schalter bildende Transistor N1 sich im leitenden Zustand befindet), und
• wird kein Strom ausgegeben, wenn beide Schalter P2 und N1 geöffnet sind (die die Schalter bildenden Transistoren P2 und N1 sich im sperrenden Zustand befinden).

From the structure of the arrangement described above it is clear that either the current generated by the current source P1, or the current generated by the current source N2, or no current is output via the output terminal O. More specifically

• the current generated by the current source P1 is output when and as long as the switch P2 is closed (the transistor P2 forming the switch is in the conductive state),
• the current generated by the current source N2 is output when and as long as the switch N1 is closed (the transistor N1 constituting the switch is in the conductive state), and
• no current is output when both switches P2 and N1 are open (the transistors P2 and N1 forming the switches are in the blocking state).

The arrangement shown in FIG. 2 is universal usable power source. Through it can at any time an arbitrarily large current for any duration be issued.

However, this only applies in theory. In practice you can Problems arise that affect the uses of the arrangement limit. These problems are that sometimes for a while after closing the switch P2 and N1 a current is output that is higher or lower than the current actually to be output (than that from the power sources P1 or N2 output current); the experience shows that the output after closing the switch Current for a certain time up to several hundred µA higher or can be lower than the one actually to be issued Electricity.

• wenn sehr kurze Stromimpulse definierter Größe benötigt werden, beispielsweise wenn ein Strom von 10µA für eine Dauer von 0,5 ns oder weniger benötigt wird, und/oder
• wenn (unabhängig von der Dauer, während welcher die Anordnung einen Strom ausgibt) größere Abweichungen des von der Anordnung ausgegebenen Stromes von dem eigentlich auszugebenden Strom unzulässig sind.

One of the consequences of this is that the arrangement shown in FIG. 2 cannot be used,

• if very short current pulses of a defined size are required, for example if a current of 10µA is required for a duration of 0.5 ns or less, and / or
• if (regardless of the duration during which the arrangement emits a current) major deviations of the current emitted by the arrangement from the current actually to be emitted are not permitted.

The present invention is therefore based on the object the arrangement according to the preamble of claim 1 to develop such that the current output by this always, especially immediately after closing the Switch is large as desired.

This object is achieved by the claim 1 claimed arrangement solved.

The arrangement according to the invention is characterized in that it contains a control device which ensures that the potential that exists on the power source side when the switch is open Connection of the same, has the value which it would have if the switch were otherwise unchanged conditions would be closed and by that flow from the power source would.

As a result, it is excluded that this is on the power source side Connection of the switch setting potential in Phases in which this is open increases. With the Preventing the rise in potential eliminates the cause which is responsible for that when closing an increased current flows through the switch.

In conventional arrangements of the type shown in FIG Phases in which the switch is open on the power source side Connection of it inevitably leads to an increase in potential on. This is because the power source too emits a current after opening the switch. The further flowing current has the consequence that in the between the Power source and the switch section of the line collects an increased amount of charge, and this in turn leads to As a result, the potential there increases. The increased potential, more precisely the potential increase causing increased amount of charge causes a Close the switch not just the one from the power source emitted electricity flows, but also one from the breakdown the increased charge quantity resulting additional current flows, where it depends on the capacity of the between the power source and the switch extending line section depends on how the additional current quickly subsides.

The fact that in the arrangement according to the invention current source side connection of the switch Potential brought to a certain value or on a certain value is held, can vary between the Power source and the switch section of the line do not collect an increased amount of charge, and consequently none Additional current flows when the switch is closed.

Due to the attitude of the current source side connection of the switch The conditions that are fulfilled are met must, so that the switch in the closed state exactly from the current emitted by the power source is flowed through and therefore exactly the current emitted by the power source the order is issued. Because this condition applies to everyone Times, i.e. also at the time the switch is closed (whenever this is done) the switch will from the moment it is closed exactly from that of the Current source flowed through current, so that the off the current output always, that is, also directly after closing the switch exactly the same as that of the Current source is current.

Advantageous developments of the invention are the subclaims, the following description, and the figures.

Figur 1

den Aufbau der im folgenden näher beschriebenen Anordnung mit einer Stromquelle und einem zu dieser in Reihe geschalteten Schalter, und

Figur 2

den Aufbau einer herkömmlichen Anordnung mit einer Stromquelle und einem zu dieser in Reihe geschalteten Schalter.

The invention is explained in more detail below using an exemplary embodiment with reference to the figures. Show it

Figure 1

the structure of the arrangement described in more detail below with a current source and a switch connected in series with this, and

Figure 2

the construction of a conventional arrangement with a current source and a switch connected in series with this.

The described below with reference to Figure 1 In the example considered, arrangement is part of a integrated circuit, but can also be replaced by a normal i.e. not integrated circuit can be realized.

The arrangement described is based on that shown in FIG and initially described with reference to it Arrangement. Components with the same reference numerals are identical or correspond to one another Components.

• eine erste Steuereinrichtung, welche dafür sorgt, daß das Potential, das sich bei geöffnetem Schalter P2 am stromquellenseitigen Anschluß desselben, genauer gesagt an einem in der Figur 1 mit dem Bezugszeichen SP bezeichneten, zwischen der Stromquelle P1 und dem Schalter P2 liegenden Knotenpunkt einstellt, den Wert aufweist, den es aufweisen würde, wenn der Schalter P2 bei ansonsten unveränderten Bedingungen geschlossen wäre und von dem von der Stromquelle P1 abgegebenen Strom durchflossen werden würde, und
• eine zweite Steuereinrichtung, welche dafür sorgt, daß das Potential, das sich bei geöffnetem Schalter N1 am stromquellenseitigen Anschluß desselben, genauer gesagt an einem in der Figur 1 mit dem Bezugszeichen SN bezeichneten, zwischen der Stromquelle N2 und dem Schalter N1 liegenden Knotenpunkt einstellt, den Wert aufweist, den es aufweisen würde, wenn der Schalter N1 bei ansonsten unveränderten Bedingungen geschlossen wäre und von dem von der Stromquelle N2 abgegebenen Strom durchflossen werden würde.

The arrangement shown in FIG. 1 additionally contains the components contained in the arrangement according to FIG

• a first control device which ensures that the potential, which is set when the switch P2 is open at the power source-side connection thereof, more precisely at a reference number SP in FIG. 1, between the power source P1 and the switch P2, the Has a value which it would have if the switch P2 were closed under otherwise unchanged conditions and the current emitted by the current source P1 would flow through, and
• a second control device, which ensures that the potential which occurs when the switch N1 is open at the power source-side connection thereof, more precisely at a node designated by the reference symbol SN in FIG. 1, between the current source N2 and the switch N1, the Has value that it would have if the switch N1 were closed under otherwise unchanged conditions and the current emitted by the current source N2 would flow through.

The first control device contains a number of other components a PMOS transistor P8, which are identical Has properties like that of the switch P2 Transistor P2. There, as explained in more detail below this transistor P8 is driven like the transistor P2 that it acts as a switch, it will be the following also referred to as switch P8.

The transistor P8 is on the source side with the node SP connected, and is with the remaining components of the first Control device interconnected so that it is in phases in which the switch formed by transistor P2 opens is the current through which the switch flows P2 flow through under the prevailing conditions would if it were closed. Because this current in the stationary State exactly that emitted by the current source P1 Is current, the node SP through the transistor P8 automatically brought to the potential they have would if the switch P2 from that of the current source P1 generated electricity would flow through.

In contrast to this, conventional arrangements follow Type of Figure 2 in phases in which the switch P2 opens is inevitable at the power source-side connection of the same a rise in potential. This is because the Current source P1 even after opening switch P2 Emits electricity. The further flowing current has the consequence that between the power source and the switch Line section an increased amount of charge collects, and this in turn means that the Potential setting node SP increases. That increased Potential, more precisely the one causing this potential increase increased amount of charge causes a Closing switch P2 not only that of the power source P1 emitted current flows, but additionally one from the Reduction of the increased charge quantity resulting additional current flows, it depends on the capacity of between the power source and the switch section of the line depends on how quickly the additional current decays.

The fact that in the arrangement according to Figure 1 current source-side connection of the switch P2 Potential brought to a certain value or on a certain value is held, can vary between the Current source P1 and the switch P2 extending line section do not collect an increased amount of charge, and consequently also no additional current flow when the switch is closed.

This has the positive effect that the switch P2 if it is closed from the start from that of the power source P1 current delivered, that is exactly from the current from which it is to be flowed through, is flowed through.

The transistor P8 is driven by a signal up, which complementary to the signal controlling the transistor T2 upq runs. The signal upq is the output signal of a by a PMOS transistor P6 and an NMOS transistor N6 formed inverter INV4. The INV4 inverter receives this from Inverter INV1 generated signal upq generated as an input signal from this the signal up inverse to the signal upq.

Through the complementary control of transistors P2 and P8, the transistor P8 is only conductive (is the one formed thereby Switch only closed) if and as long as the transistor P2 locks (if the switch thus formed opens is); in the conductive state of the transistor P2 (in the closed State of the switch thus formed) blocks the transistor P8 (the switch thus formed is open) and can therefore not affect the in the arrangement prevailing conditions and ongoing processes.

The current flowing through the transistor P8 via a to Transistor P8 in series NMOS transistor N9, one NMOS transistor N10 connected in series with transistor N9, and an NMOS transistor connected in parallel with transistor N10 N11 to the negative pole VSS which the arrangement with energy supply voltage.

Transistors N10 and N11 are corresponding to transistor N2, i.e. the same properties as the transistor N2 having transistors, and also become like the transistor N2 controlled by the signal icp_refn. With that forms the Transistors N10 and N11 corresponding to current source N2 Power sources.

The transistor N9 acts as a diode.

Transistors N9 to N11 also have other functions, which will be discussed in more detail later.

In addition to those described so far, the first control device contains Components of the same still means which for it ensure that the current flows through the transistor P8 exactly from which the transistor P2 flows would become if he were currently in charge formed switch would be closed).

In the example considered, this is achieved in that is ensured by the means mentioned that the potential setting at the drain of transistor P8 is as large as the potential at the drain connection of the Would set transistor P2 if it were just conducting (if the switch thus formed were closed).

In the example considered, this is done by a voltage follower or a device that acts as a voltage follower reached. For the sake of completeness it should be noted that as Voltage follower circuits are referred to that have an input terminal and have an output terminal, and at which the output voltage is equal to the input voltage.

This voltage follower is shown in the example under consideration an NMOS transistor N8 and the previously mentioned NMOS transistor N9 formed.

From transistor N8

• is the drain connection with the positive pole VDD the Arrangement connected to supply voltage supplying energy,
• is the gate terminal with the output terminal O of the arrangement connected, and
• is the source connection
  • connected to the source of transistor N9, and
  • connected via transistors N10 and N11 to the negative pole VSS of the supply voltage supplying the arrangement with energy.

From transistor N9

• is the drain with the drain of the transistor P8 connected,
• the gate is connected to the drain, and
• is the source connection
  • connected to the source of transistor N8, and
  • connected via transistors N10 and N11 to the negative pole VSS of the supply voltage supplying the arrangement with energy.

The input terminal of that formed by transistors N8 and N9 The voltage follower is the gate connection of the transistor N8, and the output terminal of the voltage follower is the drain of transistor N9.

It should be clear that tension followers are also realized differently can be used. For example, it would be conceivable to use an operational amplifier as a voltage follower, from which the output terminal and the inverting Input connection are interconnected.

In this context, however, it should be noted that in general of those used in the arrangement according to FIG. 1 Tension follower implementation is to be preferred. Such a realized voltage follower works as fast as possible and without stability problems. With feedback operational amplifiers on the other hand, stability problems often arise. These can be compensated for by appropriate compensation Operational amplifier are eliminated, but has a compensation as a result, the operational amplifier slower Changes responded. That is why and because of both the provision an operational amplifier as well as the measures for compensation associated with a comparatively high effort is the use of a feedback operational amplifier as a voltage follower in general not the optimal solution.

With the help of the voltage follower, this will be at the drain connection of the transistor P8 to the potential Value of the arrangement (and thus also at the drain of transistor P2) Brought potential.

This places itself on all connections of the transistor P8 exactly the potentials that are on the transistor P2 would set if this is in the conductive state befände. As a result, the transistor P8 is exactly from the current flows through, of which also the transistor P2 would be flowed through if it was in the conductive state befände.

As a result, the node SP is always, i.e. both in phases in which the switch P2 is closed, as well as in phases, in which the switch P2 is opened by the same Current, more precisely from that emitted by the current source P1 Current flowed through. As a result, neither Still opening the switch P2 changes the potential arising at the junction can, and that the switch S2 after closing it is immediately flowed through by the stream from which it flows shall be.

The second control device consists of PMOS transistors P7, P9, P10, P11, and P12, and of NMOS transistors N7 and N12, and is constructed analogously to the first control device, so that a description can be omitted.

The arrangement shown in Figure 1 can be in various ways Modify terms. For example, it is possible other than the transistors used here Transistors, for example bipolar transistors or others To use transistors. Of course you can also the power sources and / or the switches differently than in the arrangement of Figure 1 can be realized.

The arrangement described above makes it possible independently from the details of the practical realization that the current output by the arrangement always, in particular even immediately after the switch P2 is closed and N1 is as large as desired, more precisely exactly that of them Current sources P1 and N2 is current.

LIST OF REFERENCE NUMBERS

decr

Control signal for switch control

down

Control signal for switch control

downq

Control signal for switch control

icp

current output from the arrangement

icp_refn

Control signal for current setting

icp_refp

Control signal for current setting

incr

Control signal for switch control

InvX

inverter

nx

NMOS transistors

O

output terminal

px

PMOS transistors

up

Control signal for switch control

upq

Control signal for switch control

VDD

Potential of the positive pole of the arrangement with Power supply voltage

VSS

Potential of the negative pole of the arrangement with Power supply voltage

Claims (10)

Arrangement with a current source (P1) and a switch (P2) connected in series with it,
characterized in that the arrangement contains a control device (N6, N8 to N11, P6, P8) which ensures that the potential which arises when the switch (P2) is open at the power source-side connection thereof has the value which it has would if the switch (P2) were closed under otherwise unchanged conditions and the current emitted by the current source (P1) would flow through. Arrangement according to claim 1,
characterized in that the control device (N6, N8 to N11, P6, P8) contains a switch (P8) corresponding to the switch (P2), one of the connections of the switch (P8) of the control device being provided with the connection of the power source on the outside of the control device Switch (P2) is connected, and wherein the switch (P8) of the control device is otherwise arranged and connected such that in the closed state the current flows through it, which also flows through the switch (P2) provided outside the control device, when it is closed. Arrangement according to claim 2,
characterized in that the switch (P8) of the control device (N6, N8 to N11, P6, P8) is flowed through by the current emitted by the current source (P1) in the closed state. Arrangement according to claim 2 or 3,
characterized in that the switch (P2) provided outside the control device (N6, N8 to N11, P6, P8) and the switch (P8) of the control device are controlled such that the switch (P8) of the control device is open when the outside the switch (P2) provided in the control device is closed, and in that the switch (P8) in the control device is closed when the switch (P2) provided outside the control device is open. Arrangement according to one of claims 2 to 4,
characterized in that it is ensured that the potential which arises at the connection of the switch (P8) of the control device (N6, N8 to N11, P6, P8), which does not match the current source-side connection of the switch provided outside the control device ( P2) is connected, which corresponds to the potential which arises at the connection of the switch (P2) provided outside the control device, which is not connected to the current source (P1). Arrangement according to claim 5,
characterized in that the setting of the potential which arises at the connection of the switch (P8) of the control device (N6, N8 to N11, P6, P8), which is not connected to the power source-side connection of the switch (P2) provided outside the control device is carried out using a voltage follower (N8, N9) or a device corresponding to a voltage follower. Arrangement according to claim 6,
characterized in that the input terminal of the voltage follower (N8, N9) is not connected to the power source-side terminal of the switch (P2) provided outside the control device (N6, N8 to N11, P6, P8), and in that the output terminal of the voltage follower ( N8, N9) is connected to the connection of the switch (P8) of the control device, which is not connected to the power source-side connection of the switch (P2) provided outside the control device. Arrangement according to claim 6 or 7,
characterized in that the voltage follower (N8, N9) is formed by two transistors connected in series, the first transistor (N8) being a transistor arranged in a source follower circuit, and the second transistor (N9) being used as a diode. Arrangement according to claim 8,
characterized in that the gate of the first transistor (N8) is the input of the voltage follower (N8, N9) and the drain of the second transistor (N9) is the output of the voltage follower. Arrangement according to one of claims 2 to 9,
characterized in that the switch (P2) provided outside the control device and the switch (P8) of the control device are each formed by a transistor.

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