EP1295397A1 - Convertisseur numerique-analogique volontairement non monotone - Google Patents

Convertisseur numerique-analogique volontairement non monotone

Info

Publication number
EP1295397A1
EP1295397A1 EP01906667A EP01906667A EP1295397A1 EP 1295397 A1 EP1295397 A1 EP 1295397A1 EP 01906667 A EP01906667 A EP 01906667A EP 01906667 A EP01906667 A EP 01906667A EP 1295397 A1 EP1295397 A1 EP 1295397A1
Authority
EP
European Patent Office
Prior art keywords
potential
node
resistor
switch
convertor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01906667A
Other languages
German (de)
English (en)
Inventor
Victor Marten
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semtech New York Corp
Original Assignee
Semtech New York Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semtech New York Corp filed Critical Semtech New York Corp
Publication of EP1295397A1 publication Critical patent/EP1295397A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
    • G06F3/038—Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
    • G06F3/0383—Signal control means within the pointing device
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05G—CONTROL DEVICES OR SYSTEMS INSOFAR AS CHARACTERISED BY MECHANICAL FEATURES ONLY
    • G05G9/00—Manually-actuated control mechanisms provided with one single controlling member co-operating with two or more controlled members, e.g. selectively, simultaneously
    • G05G9/02—Manually-actuated control mechanisms provided with one single controlling member co-operating with two or more controlled members, e.g. selectively, simultaneously the controlling member being movable in different independent ways, movement in each individual way actuating one controlled member only
    • G05G9/04—Manually-actuated control mechanisms provided with one single controlling member co-operating with two or more controlled members, e.g. selectively, simultaneously the controlling member being movable in different independent ways, movement in each individual way actuating one controlled member only in which movement in two or more ways can occur simultaneously
    • G05G9/047—Manually-actuated control mechanisms provided with one single controlling member co-operating with two or more controlled members, e.g. selectively, simultaneously the controlling member being movable in different independent ways, movement in each individual way actuating one controlled member only in which movement in two or more ways can occur simultaneously the controlling member being movable by hand about orthogonal axes, e.g. joysticks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L3/00—Starting of generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05G—CONTROL DEVICES OR SYSTEMS INSOFAR AS CHARACTERISED BY MECHANICAL FEATURES ONLY
    • G05G9/00—Manually-actuated control mechanisms provided with one single controlling member co-operating with two or more controlled members, e.g. selectively, simultaneously
    • G05G9/02—Manually-actuated control mechanisms provided with one single controlling member co-operating with two or more controlled members, e.g. selectively, simultaneously the controlling member being movable in different independent ways, movement in each individual way actuating one controlled member only
    • G05G9/04—Manually-actuated control mechanisms provided with one single controlling member co-operating with two or more controlled members, e.g. selectively, simultaneously the controlling member being movable in different independent ways, movement in each individual way actuating one controlled member only in which movement in two or more ways can occur simultaneously
    • G05G9/047—Manually-actuated control mechanisms provided with one single controlling member co-operating with two or more controlled members, e.g. selectively, simultaneously the controlling member being movable in different independent ways, movement in each individual way actuating one controlled member only in which movement in two or more ways can occur simultaneously the controlling member being movable by hand about orthogonal axes, e.g. joysticks
    • G05G2009/04777—Manually-actuated control mechanisms provided with one single controlling member co-operating with two or more controlled members, e.g. selectively, simultaneously the controlling member being movable in different independent ways, movement in each individual way actuating one controlled member only in which movement in two or more ways can occur simultaneously the controlling member being movable by hand about orthogonal axes, e.g. joysticks with additional push or pull action on the handle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/82—Digital/analogue converters with intermediate conversion to time interval
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the generating circuit can be less expensive.
  • a so-called delta-sigma architecture may be used, which is basically a pulse width modulator followed by a low-pass filter.
  • FIG. 1 Another prior-art approach, shown in Fig. 1, is to employ two or more D/A convertors 22, 24 with appropriate gain or attenuation blocks 23, 25 prior to a linear summation stage 20 having an output 21. These components taken together are a composite D/A convertor 103.
  • Fig. 1 Another prior-art approach, shown in Fig. 1, is to employ two or more D/A convertors 22, 24 with appropriate gain or attenuation blocks 23, 25 prior to a linear summation stage 20 having an output 21. These components taken together are a composite D/A convertor 103.
  • D/A convertor 22 is the "coarse” convertor, where each stepwise change in the input control lines 101 makes a large change in the output of the convertor 22.
  • D/A convertor 24 is the "fine” convertor, where each stepwise change in the input control lines 102 makes a small change in the output of the convertor 24.
  • the usual design goal is to adjust the gain or attenuation blocks 23, 25 so that the composite D/A convertor 103 comes as close as possible to having a linear transfer characteristic as possible.
  • a digital ⁇ to- analog convertor which provides accurate and high-resolution results in particular constrained applications where feedback is available and where there is no need for monotonicity across the entire dynamic range.
  • the convertor comprises a capacitor stack, the common point of which is the output of the convertor.
  • Digitally controlled switches which may be discrete outputs from a microcontroller, selectively apply first or second potentials to points in the capacitor stack, either directly or through resistors. Appropriate control of the switches permits developing desired output voltages quickly and accurately. Performance equivalent to 24-bit 1 least-significant-bit (LSB) accuracy is easily attainable even with components having 5% tolerance.
  • LSB least-significant-bit
  • Fig. 1 is a functional block diagram of a composite D/A convertor which, with appropriate configuration, performs as in the prior art
  • Fig. 2 is a graph showing output voltage as a function of digital control signal for a D/A convertor such as in Fig. 1, depending on the configuration;
  • Fig. 3 is a general model of a resistor bridge measurement application, depicting a generalized error signal
  • Fig. 4 is the general model of a resistor bridge measurement application of Fig. 3, depicting a generalized error signal, but with a switching feature which permits correcting for much of the error signal;
  • Fig. 5 is a circuit schematic of a D/A convertor according to the invention.
  • Fig. 6 shows a typical component-level switch of the type used in the convertor of Fig. 5;
  • Fig. 7a shows the developed output voltage as a function of time of the convertor of Fig. 5 for a first set of inputs
  • Fig. 7b shows the developed output voltage as a function of time of the convertor of Fig. 5 for a second, different set of inputs
  • Fig. 8 shows a generalization of the convertor of Fig. 5, designed for incorporation onto an integrated circuit, with 12 bits of digital control signal.
  • the system must provide some sort of feedback of the output voltage.
  • the system must not require linearity over the entire dynamic range, but instead must be capable of accomphshing its goals drawing upon linearity only within reasonably small parts of the whole dynamic range.
  • a related condition is that the system must be capable of accommodating that a change from one output voltage setting to another may not be monotonic in the event that the magnitude of the change exceeds the linear adjustment range. If the system does not require outputs that stay the same for long periods of time, but instead only requires "pulsed" outputs (outputs that are known to be correct only for predetermined brief intervals) then the D/A convertor can be simplified and further reduced in cost.
  • Fig. 3 is a general model of a resistor bridge measurement application, depicting a generalized error signal 7.
  • the resistor bridge is defined by sensor 11, modeled by resistors 110, 111, and by D/A convertor 1.
  • two nodes of the resistor bridge namely the excitation nodes, are a reference voltage 6 and a defined ground potential 112.
  • the other two nodes 113, 114 of the resistor bridge serve as inputs to differential amplifier 3.
  • Differential amplifier 3 feeds an amplifier 4 which has a fixed gain.
  • These two amplifiers collectively are defined as instramentation amplifier 2.
  • the output of instramentation amplifier 2 is an input to an A/D convertor 5, having a digital output 116.
  • resistors 110, 111 vary as a function of force applied to the touch pointer or vary as a function of touch position on a touch pad.
  • the goal is for the digital output 116 to convey faithfully the force upon the touch pointer or the touch position on the touch pad.
  • Double-pole double-throw switch 10 is interposed in circuitry which otherwise matches that of Fig. 3.
  • switch 10 is in the lower position, with resistor 110 connected to potential 6 (e.g. V+) and resistor 111 connected to potential 112 (e.g. ground).
  • a first measurement is made yielding a digital output 116.
  • switch 10 is placed in the upper position, with resistor 110 connected to potential 112 (e.g. ground) and resistor 111 connected to potential 6 (e.g.
  • a second measurement is made yielding a digital output 116.
  • Each measurement has an associated offset voltage generated at the output of D/A 1, these offsets being different, one for the first measurement and one for the second measurement.
  • the two measured values at the digital output 116 are averaged to arrive at a value which is presumed to be nearly correct.
  • the difference between the two measured values at the digital output 116 is divided by two and this value is used to adjust the offset voltages generated at the output of D/A 1, each adjusted by the same amount in the same direction.
  • D/A 1 is adjusted is to ensure that the amplifier 2 is kept within its linear operating region, and that the output of the amplifier 2 is within the permissible input range of the A/D convertor 5, for each of the two measurements (that is, the measurement with switch 10 in the lower position and with the switch 10 in the upper position).
  • Fig. 5 is a circuit schematic of a D/A convertor according to the invention.
  • the D/A convertor works with respect to first and second potentials 6, 112, typically being V+ and ground. Its output is line 60.
  • Digitally controlled switches 66, 61, 68, 69 and 70 are provided.
  • Switch 66 has two contacting positions.
  • Switches 67, 68, and 69 are tri-state, having two contacting positions and a floating position.
  • Switch 70 has two positions, one of which is contacting and one of which is floating.
  • Resistors 63, 64, and 65 are provided, the resistors differing from each other in value as will be characterized below.
  • a capacitor stack is defined by capacitors 61, 62.
  • the inventive apparatus has an output line 60.
  • the apparatus has first, second, and third nodes 120, 121, 122, said second node 121 defining the output line 60.
  • a first capacitor 61 is provided between the first and second nodes 120, 121.
  • a second capacitor 62 is provided between the second and third nodes 121, 122.
  • a first switch 66 selectably connects the first node 120 to either a first potential 6 or a second potential 112.
  • a second switch 67 selectably connects the second node 121 via a first resistor 63 to the first potential 6, to the second potential 112, or to an open connection.
  • a third switch 68 selectably connects the second node 121 via a second resistor 64 to the first potential 6, to the second potential 112, or to an open connection, said second resistor 64 smaller in value than the first resistor 63.
  • a fourth switch 70 selectably connects the second node 121 to the second potential 112 or to an open connection.
  • the first switch 66, second switch 67, third switch 68, and fourth switch 70 are each controlled by digital circuitry.
  • the inventive apparatus also has a fifth switch 69 selectably connecting the second node 121 via a third resistor 65 to the first potential 6, to the second potential 112, or to an open connection, the third resistor 65 smaller in value than the second resistor 64.
  • Fig. 6 shows a typical component- level switch 151 which may be an output pin of a general-purpose microcontiOller.
  • Semiconductor switches 140, 150 are preferably FETs. If FET 140 is turned on, then V+ is connected to the output 54. If FET 150 is turned on, then ground is connected to the output 54. If neither FET is turned on, then the output 54 is allowed to float. In this way the switch 151 can be a tri-state switch. Control circuitry 51 ensures that FETs 140, 150 are never turned on simultaneously, and thus saves the FETs 140, 150 from destruction due to high current passing between V+ and ground.
  • the measurement regime of Figs. 3 and 4 is able to work with merely pulsed D/A outputs, and does not require that the D/A outputs remain constant and stable for long periods of time. For the rest of the time the D/A outputs are allowed to be undetermined. As will be seen, in this example the D/A outputs are at ground potential during times when no particular controlled output voltage is required.
  • the system design assumes that the A/D convertor 5 (Figs. 3 and 4) takes reference voltages from the same places as the references voltages for the D/A convertor (and for the rest of the resistor bridge, namely for the sensor 11). The sequence of steps for digital-to-analog conversion will now be described, and it may be helpful to refer to Figs. 7a and 7b to follow the sequence.
  • the convertor is in an idle or resting state 160. All of the switches 66, 67, 68, 69, 70 are connected to ground. This fully discharges capacitors 61, 62. The output 60 is at ground.
  • Node 120 is connected to supply voltage 6 by switching switch 66 to the upper position.
  • the capacitors get charged and define a voltage divider.
  • Node 121 and thus output 60 quickly acquire a voltage:
  • V 0 V+ • C1/(C1 + C2)
  • Cl and C2 are the capacitance of capacitors 61 and 62 respectively.
  • V o ⁇ (T1) V 0 + ( V+ - V 0 ) ( 1- exp (-T, / R ))
  • time constant R is defined as resistor 63 times the sum of capacitors 61, 62.
  • a "coarse" D/A conversion is perfo ⁇ ned by connecting node 121, through resistor 64, to ground for a duration T 2 , and then to V+ for a duration T 3 , with T 2 and T 3 selected to add up to a constant.
  • the output of the circuit may then be modeled as:
  • Vor jT (No + ( V+ - V 0 ) ( 1- exp (-T, / RC 1 )))exp(-(T 2 + T ⁇ /R + V+ .(l-exp(-T 3 /RC 2 ))
  • time constant RC 2 is defined as resistor 64 times the sum of capacitors 61, 62.
  • Figs. 7a and 7b show the output voltage as a function of various choices for T l5 T 2 , and T 3 . It will be appreciated that, as shown in Fig. 7a, if T 2 is long, then the final output voltage is lower than the voltage at the end of interval T v In contrast, as shown in Fig. 7b, if T 3 is long, then the final output voltage is higher than the voltage at the end of interval T v
  • a third resistor 65 is provided, even smaller in value than resistor 64. This pe ⁇ nits a third, even "coarser” D/A conversion, so that the entire conversion is accomplished in an even shorter settling time.
  • the method for D/A conversion is as follows.
  • the first and second nodes 120, 121 are connected to a second potential 112.
  • the second node 121 is disconnected from the second potential 112.
  • the first node 120 is disconnected from the second potential
  • the second node 120 is connected to a first one of the first and second potentials 6, 112 through a resistance 63 for a first time interval.
  • the second node 121 is connected to the second one of the first and second potentials 6, 112 through a resistance 64 for a second time interval.
  • the second node 121 is connected to the first one of the first and second potentials 6, 112 tlirough the resistance 64 for a third time interval.
  • the first one of the first and second potentials 6, 112 can be the first potential 6, whereby the second one of the first and second potentials 6, 112 is the second potential 112.
  • the first one of the first and second potentials 6, 112 can be the second potential
  • additional method steps are: connecting the node 121 is connected to the second one ofthe first and second potentials 6, 112 through the resistance 65 for a fourth time interval, and the second node 121 is connected to the first one of the first and second potentials 6, 112 through the resistance 65 for a fifth time interval.
  • Fig. 8 shows a generalization of the convertor of Fig. 5, designed for incorporation onto an integrated circuit, with 12 bits of digital control signal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Automation & Control Theory (AREA)
  • Microcomputers (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Analogue/Digital Conversion (AREA)
  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
  • Secondary Cells (AREA)

Abstract

L'invention concerne un convertisseur numérique-analogique comportant une pile de condensateurs (61, 62) dont le point commun est la sortie du convertisseur. Des commutateurs à commande numérique (66-70) pouvant être des sorties discrètes d'un microcontrôleur, appliquent sélectivement, de manière directe (66, 70) ou au moyen de résistances (63, 65), un premier ou un deuxième potentiel sur des points de la pile de condensateurs.
EP01906667A 2000-01-28 2001-01-24 Convertisseur numerique-analogique volontairement non monotone Withdrawn EP1295397A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17888700P 2000-01-28 2000-01-28
US178887P 2000-01-28
PCT/US2001/002390 WO2001056163A1 (fr) 2000-01-28 2001-01-24 Convertisseur numerique-analogique volontairement non monotone

Publications (1)

Publication Number Publication Date
EP1295397A1 true EP1295397A1 (fr) 2003-03-26

Family

ID=22654305

Family Applications (2)

Application Number Title Priority Date Filing Date
EP01906667A Withdrawn EP1295397A1 (fr) 2000-01-28 2001-01-24 Convertisseur numerique-analogique volontairement non monotone
EP01906736A Withdrawn EP1262015A4 (fr) 2000-01-28 2001-01-27 Horloge externe de conservation d'energie s'utilisant avec un circuit integre dependant de l'horloge

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP01906736A Withdrawn EP1262015A4 (fr) 2000-01-28 2001-01-27 Horloge externe de conservation d'energie s'utilisant avec un circuit integre dependant de l'horloge

Country Status (5)

Country Link
US (1) US6501342B2 (fr)
EP (2) EP1295397A1 (fr)
AU (4) AU2001232952A1 (fr)
CA (1) CA2398730A1 (fr)
WO (4) WO2001056163A1 (fr)

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WO2005017728A1 (fr) 2003-08-14 2005-02-24 Infineon Technologies Ag Modification de signaux de synchronisation produits par un circuit integre
WO2006017466A2 (fr) * 2004-08-02 2006-02-16 Coaxsys, Inc. Techniques de mise en reseau d'ordinateurs
JP4178279B2 (ja) * 2005-01-11 2008-11-12 富士通マイクロエレクトロニクス株式会社 信号検出方法、消費電力制御方法、信号検出装置及び消費電力制御装置
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JP4208864B2 (ja) * 2005-06-30 2009-01-14 日本テキサス・インスツルメンツ株式会社 チューナー用半導体装置及びダイバーシティ受信機
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WO2010117498A2 (fr) 2009-03-30 2010-10-14 Sendyne Corp. Circuit et système de protection et de conditionnement de cellule de batterie
US9195286B2 (en) * 2012-03-26 2015-11-24 Mediatek Inc. Method for performing power consumption control, and associated apparatus
CN106598195A (zh) * 2015-10-18 2017-04-26 联发科技股份有限公司 功耗控制方法及其装置
EP3685486A1 (fr) 2017-09-18 2020-07-29 Semtech Corporation Système et procédé de transmission d'énergie et de communication sans fil
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Also Published As

Publication number Publication date
AU2001234552A1 (en) 2001-08-07
WO2001056062A3 (fr) 2001-11-08
AU2001234551A1 (en) 2001-08-07
US6501342B2 (en) 2002-12-31
EP1262015A1 (fr) 2002-12-04
WO2001056145A9 (fr) 2002-10-31
WO2001056008A1 (fr) 2001-08-02
US20020145477A1 (en) 2002-10-10
CA2398730A1 (fr) 2001-08-02
EP1262015A4 (fr) 2007-03-28
WO2001056008A9 (fr) 2002-10-24
WO2001056163A1 (fr) 2001-08-02
WO2001056062A2 (fr) 2001-08-02
AU2001234609A1 (en) 2001-08-07
AU2001232952A1 (en) 2001-08-07
WO2001056145A1 (fr) 2001-08-02
WO2001056062B1 (fr) 2001-12-27

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