EP1287555A1 - Process for forming doped epitaxial silicon on a silicon substrate - Google Patents

Process for forming doped epitaxial silicon on a silicon substrate

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Publication number
EP1287555A1
EP1287555A1 EP01939124A EP01939124A EP1287555A1 EP 1287555 A1 EP1287555 A1 EP 1287555A1 EP 01939124 A EP01939124 A EP 01939124A EP 01939124 A EP01939124 A EP 01939124A EP 1287555 A1 EP1287555 A1 EP 1287555A1
Authority
EP
European Patent Office
Prior art keywords
silicon
amorphous silicon
doped amorphous
doped
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01939124A
Other languages
German (de)
French (fr)
Inventor
Young Limb
Bradley P. Jones
Michael Maldei
Samuel C. Ramac
Colleen M. Snavely
Yun Yu Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Infineon Technologies North America Corp
Original Assignee
International Business Machines Corp
Infineon Technologies North America Corp
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Filing date
Publication date
Application filed by International Business Machines Corp, Infineon Technologies North America Corp filed Critical International Business Machines Corp
Publication of EP1287555A1 publication Critical patent/EP1287555A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0113—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Definitions

  • the present invention relates to process for forming epitaxial silicon on a silicon substrate.
  • the invention relates to the formation of doped epitaxial silicon by depositing doped amorphous silicon on a silicon substrate and annealing the doped amorphous silicon to form doped epitaxial silicon.
  • An “FET” is a field effect transistor.
  • MOSFET also called an insulated-gate FET, or IGFET
  • JFET junction-gate FET
  • An FET has a control gate, and source and drain regions formed in a substrate.
  • the control gate is formed above a dielectric insulator that is deposited over the area between the source and drain regions. As voltage is applied to the control gate, mobile charged particles in the substrate form a conduction channel in the region between the source and drain regions. Once the channel forms, the transistor turns “on” and current may flow between the source and drain regions.
  • the conventional method of making a contact stud to the source-drain region of a MOSFET is to deposit an interlayer dielectric (ILD) after the MOSFET is fabricated on the substrate.
  • ILD interlayer dielectric
  • a contact hole is etched through the interlayer dielectric to the source-drain region.
  • the contact hole is filled with doped polysilicon by a blanket deposition of doped polysilicon using chemical vapor deposition (CVD).
  • CVD is a process for depositing a thin film of material onto a substrate by reacting the constituent elements in gaseous phase. CVD processes are used to produce thin, single-crystal films called epitaxial films.
  • the polysilicon on top of the interlayer dielectric is selectively removed by chemical mechanical polishing (CMP) or reactive ion etching (RTE).
  • CMP chemical mechanical polishing
  • RTE reactive ion etching
  • the polysilicon in the contact holes forms a contact stud.
  • the polysilicon is subsequently annealed to activate the dopant.
  • Contact studs formed by this process have a high stud resistance, however, due to scattering and dopant segregation at grain boundaries of the polysilicon.
  • the contact hole is filled with undoped monocrystalline silicon, which is doped by ion implantation and annealed to form epitaxial silicon.
  • the monocrystalline silicon is deposited by vapor phase deposition at greater than 1,000°C using silane (SiH 4 ), dichlorosilane (SiH 2 Cl 2 ), or silicon tetrachloride (SiCl ) as the silicon source.
  • silane SiH 4
  • dichlorosilane SiH 2 Cl 2
  • silicon tetrachloride SiCl
  • U.S. Patent No. 5,824,586 issued to Wollesen et al. incorporated in this document by reference, discloses a method for manufacturing raised silicon source and drain junctions by depositing undoped amorphous silicon on a source-drain region, ion implanting to form the source and drain junctions, and annealing the amorphous silicon at an elevated temperature so that epitaxial growth takes place in the source-drain region. The remaining amorphous silicon is removed.
  • this method requires a high temperature, use of this method with devices having small features is limited by the stringent thermal budget requirement of the device.
  • the need to dope the silicon by ion implantation is undesirable because it introduces additional process steps.
  • the method is difficult to use in a mass production environment.
  • U.S. Patent No. 5,250,454 issued to Maszara discloses a method for the self- aligned thickening of the source and drain contact regions in which an amorphous silicon layer is deposited using sputtering, electron beam evaporation, or any type of vacuum deposition system. Subsequently, the amorphous silicon layer is heated to induce solid state epitaxial regrowth on the silicon substrate.
  • the drawback of this method is the intrinsic problem of vacuum deposition: poor step coverage.
  • the aspect ratio of contact holes to silicon substrate of deep submicron features is typically greater than three. It is extremely difficult, if possible at all, to fill such contact holes with amorphous silicon by vacuum deposition technique.
  • An object of the present invention is to provide a process that is not limited by stringent thermal budget requirements.
  • a related object is to conduct the process at relatively low temperatures.
  • Another object is to avoid the problem of poor step coverage.
  • An additional object is to reduce the contact resistance of the device produced according to the process.
  • the present invention provides a process for forming doped, epitaxial, crystalline silicon on a monocrystalline silicon substrate.
  • the process produces good contact fill but does not introduce additional complexity to the fabrication process.
  • the process comprises the steps of:
  • This process allows the low-temperature formation of doped, crystalline, epitaxial silicon in a device opening having a very high aspect ratio.
  • the doped epitaxial silicon can partially or completely replace polycrystalline silicon with monocrystalline silicon, producing a drastic reduction in contact resistance.
  • the process can also be used to form a raised source- drain MOSFET.
  • Figs. 1, 2, 3, and 4 are schematic cross-sectional views illustrating the sequential fabrication of a source or drain contact stud using the process of the invention
  • Figs. 5, 6, and 7 are schematic cross-sectional views illustrating the sequential fabrication of a raised source- drain MOSFET using the process of the invention. More specifically,
  • Fig. 1 illustrates a semiconductor device having (1) a silicon substrate, in which a gate (including a thin dielectric layer, a conductive layer, and a dielectric layer) and source and drain regions have been fabricated, (2) an interlayer dielectric layer covering the silicon substrate, and (3) a contact hole etched through the interlayer dielectric layer to one of the source-drain regions;
  • Fig. 2 illustrates the structure shown in Fig. 1 after a layer of doped amorphous silicon is deposited on the surface of the device;
  • Fig. 3 illustrates the structure shown in Fig. 2 after the excess doped amorphous silicon on top of the interlayer dielectric layer is selectively removed;
  • Fig. 4 illustrates the structure shown in Fig. 3 after epitaxial growth has converted the doped amorphous silicon into doped crystalline epitaxial silicon;
  • Fig. 5 is a cross-sectional view of a semiconductor device comprising a silicon substrate, field oxide regions, source-drain regions, a gate region, a polysilicon gate formed on the gate region, gate sidewall spacers formed on either side of the gate region, and a doped amorphous silicon layer deposited on the device;
  • Fig. 6 illustrates the structure shown in Fig. 5 after the doped amorphous silicon is annealed
  • Fig. 7 illustrates the structure shown in Fig. 6 after the amorphous silicon has been removed.
  • the invention is not limited to constructions of any particular shape. Those skilled in the art will recognize that the positions and configuration of the doped regions vary with the design of the semiconductor device and that alternate designs are encompassed by the invention.
  • Fig. 1 is a cross-sectional view of a semiconductor device 10, comprising a silicon substrate 12 of which a gate 14, which comprises a thin dielectric layer 16, a conductive layer 18, and a dielectric layer 20 as well as source and drain regions 22 have been fabricated.
  • Thin dielectric layer 16 may be a layer of a dielectric material, such as silicon dioxide, having a thickness of about 100 A or less.
  • Conductive layer 18 may be a layer of a conductive material, such as polycrystalline silicon, having a thickness of about 2000 A.
  • Dielectric layer 20 may be a layer of a dielectric material, such as silicon nitride, having a thickness of about 2000 A. Preparation of semiconductor device 10 is conventional and can be effected by methods well known to those skilled in the art. As will be recognized by those skilled in the art, although the boundaries of silicon substrate 12 are not shown, the substrate typically comprises a number of devices and may comprise multilayer devices.
  • Interlayer dielectric layer 24 may be any low dielectric constant material known in the art to be useful as a dielectric material, such as silicon dioxide, polyimide, an organic siloxane polymer, poly-arylene ether, carbon-doped silicate glass or silsesquioxane glass, spin-on glass, fluorinated or non- fluorinated silicate glass, or diamond-like amorphous carbon.
  • Interlayer dielectric layer 24 can be deposited by chemical vapor deposition (CVD), including plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or spin coating.
  • the thickness of interlayer dielectric layer 24 is typically about 0.2 to about 2.0 microns.
  • a typical dielectric material is borophosphosilicate glass (BPSG).
  • Contact hole 26 has been etched through interlayer dielectric layer 24 to source- drain region 22 by, for example, reactive ion etching (RIE).
  • RIE reactive ion etching
  • contact hole 26 is about 100 to 1,000 nm in diameter.
  • contact hole 26 is about 250 nm in diameter.
  • a layer of doped amorphous silicon 28 is deposited on the surface of the device.
  • Deposition of doped silicon is conveniently conducted by low pressure chemical vapor deposition (LPCVD).
  • LPCVD is a method in which deposition gases are pyrolyzed in a LPCVD reactor to form the doped silicon using procedures well known to those skilled in the art.
  • doped amorphous silicon using one or more of phosphorous trichloride, t-butyl phosphine, i-butyl phosphine, tetramethyl phosphate, and tetramethyl phosphate as the dopant and silane as the silicon source is disclosed in U.S. Patent No. 4,877,753 issued to Freeman.
  • In-situ doping of silicon using phosphine as the dopant and silane as the silicon source is disclosed in U.S. Patent No. 5,256,566 issued to Bailey.
  • the silicon is doped with arsenic or phosphorus ions.
  • p-type conductivity is desired, the silicon is doped with boron ions.
  • Deposition should be completed at a temperature at or below about 625 °C, preferably at or below 600°C. More preferably, deposition is completed at about 550°C, a pressure of about 300 mTorr, and a phosphine-to-silane ratio of about 0.0008 to form a phosphorus-doped amorphous silicon. Because doped amorphous silicon 28 is deposited by low pressure chemical vapor deposition, it fills contact hole 26 with good step coverage. For n-type conductivity, for example, the dopant level is typically about 1.2 x 10 20 phosphorus atoms/cm 3.
  • CMP chemical mechanical polishing
  • RLE reactive ion etching
  • doped amorphous silicon 28 is annealed at a temperature sufficient to induce epitaxial crystallization of the doped amorphous silicon.
  • Conventional annealing is conducted at a temperature between about 550°C and 1,000°C, generally between 800°C and 570°C, preferably at about 570°C, for about 5 minutes to 10 hours, to induce epitaxial growth of the doped amorphous silicon.
  • Rapid thermal anneal is typically conducted at a temperature of about 1,000°C for 5 to 90 seconds.
  • the crystalline structure of underlying source- drain region 22 provides the seed for the epitaxial crystal growth of doped amorphous silicon 28. Epitaxial growth converts doped amorphous silicon 28 into doped crystalline epitaxial silicon 30.
  • FIG. 5 is a cross-sectional view of a semiconductor device 110 comprising a silicon substrate 112, field oxide regions 132, source-drain regions 122, and a gate region 134 formed on substrate 112.
  • Source-drain regions 122 comprise mono-crystalline silicon.
  • a polysilicon gate 136 is formed on gate region 134 and gate sidewall spacers 138 are formed on either side of gate region 134.
  • This structure is conventional and can be fabricated by methods well known to those skilled in the art.
  • a doped amorphous silicon layer 128 has been deposited as described above. The doped amorphous silicon layer typically is about 30 nm to 100 nm thick.
  • the doped amorphous silicon is annealed as described above at a temperature sufficient to induce epitaxial crystallization of the doped amorphous silicon.
  • the regions 140 of doped amorphous silicon layer 128 that are in contact with single crystal silicon undergo epitaxial growth.
  • the region 142 in contact with polycrystalline silicon is converted to poly-crystalline silicon.
  • the regions 144 not in contact with silicon, i.e., those regions over field oxide regions 132 or over gate spacer sidewalls 138, are not converted to epitaxial silicon, but remain as amorphous silicon.
  • the amorphous silicon has been removed by, for example, a hydrofluoric acid etch.
  • Raised epitaxial silicon regions 140 remain over source-drain regions 122.
  • Raised epitaxial silicon regions 140 serve as a sacrificial thickness for subsequent suicide formation and as a material for the underlying junction.
  • Processing of the device can be continued using well-known fabrication methods such as those disclosed at column 5, lines 33-56, of U.S. Patent No. 5,824,586 issued to Wollesen et al.
  • a layer of refractory metal such as titanium or cobalt, may be deposited on the MOSFET.
  • a rapid thermal anneal is conducted to form suicide in those regions in which the deposited metal overlies epitaxial silicon.
  • the refractory metal not converted to suicide is removed, producing a MOSFET in which the source and drain regions have been raised.
  • the present invention can be used in the manufacture of semiconductor devices, which are incorporated, for example, in digital computers.
  • the invention has been particularly shown and described with reference to the preferred embodiments, those skilled in the art will appreciate that various modifications and changes in form and details may be made without departing from the spirit and scope of the invention.
  • specific details are set forth to provide a more thorough understanding of the invention, but it will be apparent to those skilled in the art that the invention may be practiced without using these specific details.
  • the process of the invention can also be used in the fabrication of multi-level devices.
  • the invention is described with respect to formation of a contact stud to a source and drain region of a MOSFET, and with respect to formation of a raised source-drain MOSFET, it is not so limited.
  • the present invention may be used in any situation in which it is desired to form doped epitaxial crystalline silicon on a monocrystalline silicon substrate.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A process for forming doped epitaxial silicon on a silicon substrate. Doped amorphous silicon is deposited on a silicon substrate and annealed to form doped epitaxial crystalline silicon. Doped crystalline epitaxial silicon can be grown in a device opening having a very high aspect ratio at a very low temperature. The doped epitaxial silicon can partially or completely replace polycrystalline silicon with monocrystalline silicon, producing a drastic reduction in contact resistance. The process can also be used to fabricate a raised source-drain MOSFET.

Description

PROCESS FOR FORMING DOPED EPITAXIAL SILICON ON A SILICON SUBSTRATE
TECHNICAL FIELD
The present invention relates to process for forming epitaxial silicon on a silicon substrate. In particular, the invention relates to the formation of doped epitaxial silicon by depositing doped amorphous silicon on a silicon substrate and annealing the doped amorphous silicon to form doped epitaxial silicon.
BACKGROUND OF THE INVENTION
An "FET" is a field effect transistor. There are two major types of FET's, the metal-oxide-semiconductor field effect transistor or MOSFET (also called an insulated-gate FET, or IGFET), and the junction-gate FET, or JFET. An FET has a control gate, and source and drain regions formed in a substrate. The control gate is formed above a dielectric insulator that is deposited over the area between the source and drain regions. As voltage is applied to the control gate, mobile charged particles in the substrate form a conduction channel in the region between the source and drain regions. Once the channel forms, the transistor turns "on" and current may flow between the source and drain regions.
The conventional method of making a contact stud to the source-drain region of a MOSFET is to deposit an interlayer dielectric (ILD) after the MOSFET is fabricated on the substrate. A contact hole is etched through the interlayer dielectric to the source-drain region. The contact hole is filled with doped polysilicon by a blanket deposition of doped polysilicon using chemical vapor deposition (CVD). CVD is a process for depositing a thin film of material onto a substrate by reacting the constituent elements in gaseous phase. CVD processes are used to produce thin, single-crystal films called epitaxial films.
The polysilicon on top of the interlayer dielectric is selectively removed by chemical mechanical polishing (CMP) or reactive ion etching (RTE). The polysilicon in the contact holes forms a contact stud. The polysilicon is subsequently annealed to activate the dopant. Contact studs formed by this process have a high stud resistance, however, due to scattering and dopant segregation at grain boundaries of the polysilicon. Alternatively, the contact hole is filled with undoped monocrystalline silicon, which is doped by ion implantation and annealed to form epitaxial silicon. The monocrystalline silicon is deposited by vapor phase deposition at greater than 1,000°C using silane (SiH4), dichlorosilane (SiH2Cl2), or silicon tetrachloride (SiCl ) as the silicon source. For example, U.S. Patent No. 5,824,586 issued to Wollesen et al., incorporated in this document by reference, discloses a method for manufacturing raised silicon source and drain junctions by depositing undoped amorphous silicon on a source-drain region, ion implanting to form the source and drain junctions, and annealing the amorphous silicon at an elevated temperature so that epitaxial growth takes place in the source-drain region. The remaining amorphous silicon is removed.
Because this method requires a high temperature, use of this method with devices having small features is limited by the stringent thermal budget requirement of the device. The need to dope the silicon by ion implantation is undesirable because it introduces additional process steps. In addition, the method is difficult to use in a mass production environment.
U.S. Patent No. 5,250,454 issued to Maszara discloses a method for the self- aligned thickening of the source and drain contact regions in which an amorphous silicon layer is deposited using sputtering, electron beam evaporation, or any type of vacuum deposition system. Subsequently, the amorphous silicon layer is heated to induce solid state epitaxial regrowth on the silicon substrate. The drawback of this method is the intrinsic problem of vacuum deposition: poor step coverage. The aspect ratio of contact holes to silicon substrate of deep submicron features is typically greater than three. It is extremely difficult, if possible at all, to fill such contact holes with amorphous silicon by vacuum deposition technique.
Thus, a need exists for a process that forms epitaxial, crystalline silicon on a silicon substrate with good contact fill but does not introduce additional complexity to the fabrication process. To overcome the shortcomings of conventional methods, a new process for forming doped epitaxial silicon on a silicon substrate is provided. An object of the present invention is to provide a process that is not limited by stringent thermal budget requirements. A related object is to conduct the process at relatively low temperatures. Another object is to avoid the problem of poor step coverage. It is still another object of the present invention to allow the growth of doped epitaxial film in a device opening having a high aspect ratio. An additional object is to reduce the contact resistance of the device produced according to the process. SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a process for forming doped, epitaxial, crystalline silicon on a monocrystalline silicon substrate. The process produces good contact fill but does not introduce additional complexity to the fabrication process. The process comprises the steps of:
depositing doped amorphous silicon on the monocrystalline silicon substrate; and
annealing the doped amorphous silicon at a temperature sufficient to induce epitaxial crystallization of the doped amorphous silicon, and forming the doped epitaxial silicon.
This process allows the low-temperature formation of doped, crystalline, epitaxial silicon in a device opening having a very high aspect ratio. The doped epitaxial silicon can partially or completely replace polycrystalline silicon with monocrystalline silicon, producing a drastic reduction in contact resistance. The process can also be used to form a raised source- drain MOSFET.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
BRIEF DESCRIPTION OF THE DRAWING
The invention is best understood from the following detailed description when read in connection with the accompanying drawing. Included in the drawing are the following figures: Figs. 1, 2, 3, and 4 are schematic cross-sectional views illustrating the sequential fabrication of a source or drain contact stud using the process of the invention and Figs. 5, 6, and 7 are schematic cross-sectional views illustrating the sequential fabrication of a raised source- drain MOSFET using the process of the invention. More specifically,
Fig. 1 illustrates a semiconductor device having (1) a silicon substrate, in which a gate (including a thin dielectric layer, a conductive layer, and a dielectric layer) and source and drain regions have been fabricated, (2) an interlayer dielectric layer covering the silicon substrate, and (3) a contact hole etched through the interlayer dielectric layer to one of the source-drain regions;
Fig. 2 illustrates the structure shown in Fig. 1 after a layer of doped amorphous silicon is deposited on the surface of the device;
Fig. 3 illustrates the structure shown in Fig. 2 after the excess doped amorphous silicon on top of the interlayer dielectric layer is selectively removed;
Fig. 4 illustrates the structure shown in Fig. 3 after epitaxial growth has converted the doped amorphous silicon into doped crystalline epitaxial silicon;
Fig. 5 is a cross-sectional view of a semiconductor device comprising a silicon substrate, field oxide regions, source-drain regions, a gate region, a polysilicon gate formed on the gate region, gate sidewall spacers formed on either side of the gate region, and a doped amorphous silicon layer deposited on the device;
Fig. 6 illustrates the structure shown in Fig. 5 after the doped amorphous silicon is annealed; and
Fig. 7 illustrates the structure shown in Fig. 6 after the amorphous silicon has been removed.
DETAILED DESCRIPTION OF THE INVENTION
The present invention will now be described by reference to the accompanying drawing. Throughout the specification, similar reference numbers refer to similar elements in all figures of the drawing. In the drawing, various aspects of the structures have been shown and schematically represented in a simplified manner to more clearly describe and illustrate the invention. For example, the drawings are not intended to be to scale. In addition, the vertical cross-sections of the various aspects of the structures are illustrated as being generally rectangular in shape. Those skilled in the art will appreciate, however, that with practical structures these aspects will most likely incorporate more tapered features.
Moreover, the invention is not limited to constructions of any particular shape. Those skilled in the art will recognize that the positions and configuration of the doped regions vary with the design of the semiconductor device and that alternate designs are encompassed by the invention.
Referring to the drawing, the invention will be described with respect to fabrication of a source or drain (source-drain) contact stud. Fig. 1 is a cross-sectional view of a semiconductor device 10, comprising a silicon substrate 12 of which a gate 14, which comprises a thin dielectric layer 16, a conductive layer 18, and a dielectric layer 20 as well as source and drain regions 22 have been fabricated. Thin dielectric layer 16 may be a layer of a dielectric material, such as silicon dioxide, having a thickness of about 100 A or less. Conductive layer 18 may be a layer of a conductive material, such as polycrystalline silicon, having a thickness of about 2000 A. Dielectric layer 20 may be a layer of a dielectric material, such as silicon nitride, having a thickness of about 2000 A. Preparation of semiconductor device 10 is conventional and can be effected by methods well known to those skilled in the art. As will be recognized by those skilled in the art, although the boundaries of silicon substrate 12 are not shown, the substrate typically comprises a number of devices and may comprise multilayer devices.
Silicon substrate 12 is covered with interlayer dielectric layer 24. Interlayer dielectric layer 24 may be any low dielectric constant material known in the art to be useful as a dielectric material, such as silicon dioxide, polyimide, an organic siloxane polymer, poly-arylene ether, carbon-doped silicate glass or silsesquioxane glass, spin-on glass, fluorinated or non- fluorinated silicate glass, or diamond-like amorphous carbon. Interlayer dielectric layer 24 can be deposited by chemical vapor deposition (CVD), including plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or spin coating. The thickness of interlayer dielectric layer 24 is typically about 0.2 to about 2.0 microns. A typical dielectric material is borophosphosilicate glass (BPSG).
Contact hole 26 has been etched through interlayer dielectric layer 24 to source- drain region 22 by, for example, reactive ion etching (RIE). Typically, contact hole 26 is about 100 to 1,000 nm in diameter. Preferably, contact hole 26 is about 250 nm in diameter.
Referring to Fig. 2, a layer of doped amorphous silicon 28 is deposited on the surface of the device. Deposition of doped silicon, sometimes called "in-situ" doping, is conveniently conducted by low pressure chemical vapor deposition (LPCVD). LPCVD is a method in which deposition gases are pyrolyzed in a LPCVD reactor to form the doped silicon using procedures well known to those skilled in the art.
For example, formation of doped amorphous silicon using one or more of phosphorous trichloride, t-butyl phosphine, i-butyl phosphine, tetramethyl phosphate, and tetramethyl phosphate as the dopant and silane as the silicon source is disclosed in U.S. Patent No. 4,877,753 issued to Freeman. In-situ doping of silicon using phosphine as the dopant and silane as the silicon source is disclosed in U.S. Patent No. 5,256,566 issued to Bailey. As is known in the art, if n-type conductivity is desired, the silicon is doped with arsenic or phosphorus ions. If p-type conductivity is desired, the silicon is doped with boron ions.
Deposition should be completed at a temperature at or below about 625 °C, preferably at or below 600°C. More preferably, deposition is completed at about 550°C, a pressure of about 300 mTorr, and a phosphine-to-silane ratio of about 0.0008 to form a phosphorus-doped amorphous silicon. Because doped amorphous silicon 28 is deposited by low pressure chemical vapor deposition, it fills contact hole 26 with good step coverage. For n-type conductivity, for example, the dopant level is typically about 1.2 x 10 20 phosphorus atoms/cm 3.
Referring to Fig. 3, the excess doped amorphous silicon 28 on top of interlayer dielectric layer 24 is selectively removed by chemical mechanical polishing (CMP) or reactive ion etching (RLE). CMP is described, for example, in U.S. Patent No. 4,944,836 issued to Beyer and in U.S. Patent No. 4,789,648 issued to Chow.
Referring to Fig. 4, doped amorphous silicon 28 is annealed at a temperature sufficient to induce epitaxial crystallization of the doped amorphous silicon. Conventional annealing is conducted at a temperature between about 550°C and 1,000°C, generally between 800°C and 570°C, preferably at about 570°C, for about 5 minutes to 10 hours, to induce epitaxial growth of the doped amorphous silicon. Rapid thermal anneal is typically conducted at a temperature of about 1,000°C for 5 to 90 seconds. The crystalline structure of underlying source- drain region 22 provides the seed for the epitaxial crystal growth of doped amorphous silicon 28. Epitaxial growth converts doped amorphous silicon 28 into doped crystalline epitaxial silicon 30.
The present invention will also be described with respect to fabrication of a raised source-drain MOSFET. Fig. 5 is a cross-sectional view of a semiconductor device 110 comprising a silicon substrate 112, field oxide regions 132, source-drain regions 122, and a gate region 134 formed on substrate 112. Source-drain regions 122 comprise mono-crystalline silicon. A polysilicon gate 136 is formed on gate region 134 and gate sidewall spacers 138 are formed on either side of gate region 134. This structure is conventional and can be fabricated by methods well known to those skilled in the art. A doped amorphous silicon layer 128 has been deposited as described above. The doped amorphous silicon layer typically is about 30 nm to 100 nm thick.
The doped amorphous silicon is annealed as described above at a temperature sufficient to induce epitaxial crystallization of the doped amorphous silicon. Referring to Fig. 6, the regions 140 of doped amorphous silicon layer 128 that are in contact with single crystal silicon undergo epitaxial growth. The region 142 in contact with polycrystalline silicon is converted to poly-crystalline silicon. The regions 144 not in contact with silicon, i.e., those regions over field oxide regions 132 or over gate spacer sidewalls 138, are not converted to epitaxial silicon, but remain as amorphous silicon.
Referring to Fig. 7, the amorphous silicon has been removed by, for example, a hydrofluoric acid etch. Raised epitaxial silicon regions 140 remain over source-drain regions 122. Raised epitaxial silicon regions 140 serve as a sacrificial thickness for subsequent suicide formation and as a material for the underlying junction.
Processing of the device can be continued using well-known fabrication methods such as those disclosed at column 5, lines 33-56, of U.S. Patent No. 5,824,586 issued to Wollesen et al. As stated above, the disclosure is incorporated in this document by reference. For example, a layer of refractory metal, such as titanium or cobalt, may be deposited on the MOSFET. A rapid thermal anneal is conducted to form suicide in those regions in which the deposited metal overlies epitaxial silicon. The refractory metal not converted to suicide is removed, producing a MOSFET in which the source and drain regions have been raised.
INDUSTRIAL APPLICABILITY
The present invention can be used in the manufacture of semiconductor devices, which are incorporated, for example, in digital computers. Although the invention has been particularly shown and described with reference to the preferred embodiments, those skilled in the art will appreciate that various modifications and changes in form and details may be made without departing from the spirit and scope of the invention. For example, in the preceding description specific details are set forth to provide a more thorough understanding of the invention, but it will be apparent to those skilled in the art that the invention may be practiced without using these specific details.
Although the invention has been illustrated with a single-level device, it is not so limited. As will be apparent to those skilled in the art, the process of the invention can also be used in the fabrication of multi-level devices. Further, although the invention is described with respect to formation of a contact stud to a source and drain region of a MOSFET, and with respect to formation of a raised source-drain MOSFET, it is not so limited. The present invention may be used in any situation in which it is desired to form doped epitaxial crystalline silicon on a monocrystalline silicon substrate.

Claims

What is Claimed:
1. A process for forming a doped epitaxial silicon on a monocrystalline silicon substrate, the process comprising:
depositing doped amorphous silicon on the monocrystalline silicon substrate; and
annealing the doped amorphous silicon at a temperature sufficient to induce epitaxial crystallization of the doped amorphous silicon and form the doped epitaxial silicon.
2. The process of claim 1 in which the doped amorphous silicon is deposited at a temperature below about 625°C.
3. The process of claim 1 in which the doped amorphous silicon is annealed at a temperature of about 550°C to 1,000°C.
4. The process of claim 3 in which the doped amorphous silicon is annealed at a temperature of about 570°C.
5. The process of claim 4 in which the doped amorphous silicon is deposited at a temperature below about 600°C.
6. A process of forming a contact stud comprising doped epitaxial silicon in a semiconductor device, the process comprising the steps of:
opening a contact hole through an interlayer dielectric layer of the device;
filling the contact hole with doped amorphous silicon;
annealing the doped amorphous silicon and forming the doped epitaxial silicon contact stud.
7. The process of claim 6 in which the doped amorphous silicon is deposited at a temperature below about 625°C.
8. The process of claim 7 in which the contact hole is opened by reactive ion etching.
9. The process of claim 7 in which the doped amorphous silicon is annealed at a temperature of about 550°C to 1,000°C.
10. The process of claim 9 in which the doped amorphous silicon is annealed at a temperature of about 570°C.
11. The process of claim 10 in which the doped amorphous silicon is deposited at a temperature below about 600°C.
12. The process of claim 6 in which the silicon substrate is crystalline silicon.
13. The process of claim 6 in which the contact hole is opened to a source- drain region of a metal-oxide semiconductor field effect transistor, in which the metal oxide semiconductor field effect transistor comprises two source-drain regions in a silicon substrate, a gate region in contact with each of the source-drain regions, and an interlayer dielectric over the gate regions and the source-drain regions.
14. The process of claim 13 in which the doped amorphous silicon is deposited at a temperature below about 600°C.
15. A process for forming a metal-oxide semiconductor field effect transistor, the process comprising the steps of:
providing a structure having a silicon substrate, two source-drain regions including monocrystalline silicon on the substrate, and a gate region;
depositing doped amorphous silicon over the structure;
annealing the doped amorphous silicon at a temperature sufficient to induce epitaxial crystallization of the doped amorphous silicon and forming doped epitaxial silicon in regions of the doped amorphous silicon in contact with the source-drain regions; and removing the remaining doped amorphous silicon.
16. The process of claim 15 in which the doped amorphous silicon is deposited at a temperature below about 625°C.
17. The process of claim 16 in which the doped amorphous silicon is annealed at a temperature of about 550°C to 1,000°C.
18. The process of claim 17 in which the doped amorphous silicon is annealed at a temperature of about 570°C.
19. The process of claim 15 further comprising, before the step of depositing doped amorphous silicon, depositing an interlayer dielectric layer and creating a high aspect ratio contact hole through the interlayer dielectric layer to a source-drain region, whereby the doped amorphous silicon when deposited fills the contact hole.
20. The process of claim 15 further comprising, after the step of depositing doped amorphous silicon, selectively removing excess doped amorphous silicon on top of the interlayer dielectric layer.
EP01939124A 2000-05-31 2001-05-18 Process for forming doped epitaxial silicon on a silicon substrate Withdrawn EP1287555A1 (en)

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KR100882930B1 (en) 2004-12-17 2009-02-10 삼성전자주식회사 CMOS semiconductor devices having source and drain regions and fabrication methods thereof
EP1952438A1 (en) * 2005-11-16 2008-08-06 Nxp B.V. Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
US8853862B2 (en) * 2011-12-20 2014-10-07 International Business Machines Corporation Contact structures for semiconductor transistors
JP2013258188A (en) * 2012-06-11 2013-12-26 Hitachi Kokusai Electric Inc Method for processing substrate, method for manufacturing semiconductor device, and substrate processing device
CN114695249A (en) * 2020-12-25 2022-07-01 中国科学院微电子研究所 Method for manufacturing contact part, bit line, storage node and DRAM

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8504725D0 (en) * 1985-02-23 1985-03-27 Standard Telephones Cables Ltd Integrated circuits
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
JP2695185B2 (en) * 1988-05-02 1997-12-24 株式会社日立製作所 Semiconductor integrated circuit device and method of manufacturing the same
US5192708A (en) * 1991-04-29 1993-03-09 International Business Machines Corporation Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
US5591674A (en) * 1991-12-30 1997-01-07 Lucent Technologies Inc. Integrated circuit with silicon contact to silicide
US5250454A (en) * 1992-12-10 1993-10-05 Allied Signal Inc. Method for forming thickened source/drain contact regions for field effect transistors
US5686335A (en) * 1996-07-22 1997-11-11 Taiwan Semiconductor Manufacturing Company, Ltd Method of making high-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel
US5824586A (en) * 1996-10-23 1998-10-20 Advanced Micro Devices, Inc. Method of manufacturing a raised source/drain MOSFET

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0193326A1 *

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