EP1276120B1 - Device to control an electromagnet - Google Patents

Device to control an electromagnet Download PDF

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Publication number
EP1276120B1
EP1276120B1 EP20020014583 EP02014583A EP1276120B1 EP 1276120 B1 EP1276120 B1 EP 1276120B1 EP 20020014583 EP20020014583 EP 20020014583 EP 02014583 A EP02014583 A EP 02014583A EP 1276120 B1 EP1276120 B1 EP 1276120B1
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EP
European Patent Office
Prior art keywords
clock generator
voltage
resistor
switch
clock
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EP20020014583
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German (de)
French (fr)
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EP1276120A2 (en
EP1276120A3 (en
Inventor
Hermann Hoepken
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KA Schmersal GmbH and Co KG
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KA Schmersal GmbH and Co KG
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    • E—FIXED CONSTRUCTIONS
    • E05—LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05B—LOCKS; ACCESSORIES THEREFOR; HANDCUFFS
    • E05B47/00—Operating or controlling locks or other fastening devices by electric or magnetic means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F7/00—Magnets
    • H01F7/06—Electromagnets; Actuators including electromagnets
    • H01F7/08—Electromagnets; Actuators including electromagnets with armatures
    • H01F7/18—Circuit arrangements for obtaining desired operating characteristics, e.g. for slow operation, for sequential energisation of windings, for high-speed energisation of windings
    • H01F7/1844—Monitoring or fail-safe circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T70/00—Locks
    • Y10T70/60—Systems

Definitions

  • the invention relates to a device for controlling an electromagnet according to the preamble of claim 1.
  • electromagnets In safety circuits for locking and unlocking of doors, flaps or the like electromagnets are used which have an actuatable according to the control of a solenoid armature, which locks or unlocks a door due to its position. It must be ensured that the armature moves correctly during a tightening section, and that a magnetic force exerted by the solenoid for holding the armature in position during a holding section at the lowest possible applied operating voltage is not reduced so far that the armature due to external disturbances, especially vibrations, drops.
  • a predetermined voltage loading of the solenoid does not account for control of the current flowing through the solenoid with respect to energy loss or the operating temperature of the solenoid, so that it is advantageous to interrupt the application of voltage when the solenoid heats up and / or certain current values are reached to prevent energy loss through heat generation of the solenoid.
  • the object of the invention is to provide a device for driving an electromagnet according to the preamble of claim 1, which uses simple components and has a simpler structure.
  • Fig. 1 shows a simplified and schematic representation of a circuit diagram of an embodiment of a circuit for driving an electromagnet.
  • FIG. 12 shows an example of a detailed circuit diagram of the embodiment of FIG Fig. 1 ,
  • Fig. 3 shows an example of a detailed circuit diagram of another embodiment of Fig. 1 .
  • the circuit after Fig. 1 has an electromagnet with a solenoid 1, which can be acted upon by a DC voltage of a voltage source 2 and serves to actuate an associated spring-loaded armature 3.
  • a timer 4 connected to the power source 2 is coupled to a switch 5 serially connected to the solenoid 1, whereby the switch 5 is closed and opened in accordance with the clock of the timer 4. When the switch 5 is closed, the DC voltage of the voltage source 2 is applied to the solenoid 1.
  • a first ohmic resistor 6 Connected in series with the switch 5 is a first ohmic resistor 6, which is coupled to ground, via which a voltage drop occurs when the switch 5 is closed and the DC voltage is applied to the solenoid 1.
  • a device comprising a current detection switch 7 is provided.
  • the current detection switch 7 is coupled in parallel to the first resistor 6 and serially to the switch 5 and temporarily turns off the power source 2 of the solenoid 1 by opening the switch 5 as long as a predetermined current flowing through the solenoid 1 is detected by the current detection switch 7. If the detected current drops again, the current detection switch 7 stops its influence on the switch 5 and this is again actuated by the clock 4.
  • the current flowing through the solenoid 1 is thus limited by the switching of the current detection switch 7, wherein the current flowing through the first ohmic resistor 6 current is detected by the current detection switch 7.
  • the size of the first resistor 6 in conjunction with the current detection switch 7 is selected so that that through the solenoid 1, a current can flow, which is sufficient to hold the armature 3 in its position - it then flows then a holding current.
  • the clock overlaps at least partially with that of the clock 4 and is lower than this, another, second resistor 9 is parallel to the first resistor 6 in the circuit via a switch 10 switchable, wherein the second resistor 9 at Mass is coupled.
  • the size of the second resistor 9 is chosen so that there is a smaller total resistance.
  • the size of the first resistor 6 is greater than that of the second resistor 9.
  • a freewheeling circuit for the solenoid 1 which comprises a parallel to the solenoid 1 coupled freewheeling diode 11.
  • the current through the solenoid 1 is maintained with the switch 5 open over a certain time by the inductance of the solenoid 1 time and short-circuited by the freewheeling diode 11.
  • the freewheeling circuit may optionally comprise a series connection of further diodes and / or transistors.
  • Fig. 2 is the voltage source 2 designed as a DC voltage control device for a via the terminals 12, 13 coupled operating AC voltage.
  • a rectifier 14 is provided, are coupled to the two mutually connected Zener diodes 15, 16 and a capacitor 17 in parallel.
  • the capacitor 17 is connected in series with ground.
  • the DC voltage control device further comprises a coupled to the capacitor 17 diode 18, which follows a field effect transistor 19.
  • the field effect transistor 19 is connected via two resistors 20, 21 connected in series, connected in series with the capacitor 17, a limiter diode 22 coupled to ground being provided between the two resistors 20, 21 and the field effect transistor 19. When closed, the field effect transistor 19 switches a resistor 23 and a capacitor coupled to ground 24 as a filter in the circuit of the DC voltage control device.
  • the clock 4 for clocked closing of the switch 5 formed in this embodiment as a field effect transistor comprises a clock NAND gate 25, from which an input to the voltage source 2 is coupled to the power supply and further supplied with a high level.
  • the output of clock NAND gate 25 is fed back to the other input of clock NAND gate 25 through a combination of one ohmic clock resistor 26, one clock diode 27 and one clock capacitor 28.
  • the output of the clock generator 4 is also connected to a SET input of a flip-flop 31 comprising two NAND gates 29, 30 which, due to the signal of the clock generator 4 applied to the SET input, opens or switches the switch 5 clocked by means of the signal at the Q output closes.
  • the current detection switch 7 is designed as a transistor whose base-emitter path detects the voltage on the circuit.
  • the emitter of the transistor is connected to ground, and the collector is coupled both via a high-potential ohmic resistor 32 and to a RESET input of the flipflop 31.
  • the parallel to the resistor 6 and connected in series with the solenoid 1 transistor becomes conductive when the voltage across the resistor 6 exceeds the voltage between the base and emitter of the transistor. Then the signal applied to the RESET input of the flip-flop 31 changes, since the current flowing through the resistor 32 flows through the current detection switch 7 to ground.
  • the flip-flop 31 then opens the switch 5, and the application of the DC voltage to the solenoid 1 is temporarily interrupted.
  • the clocked connection of the resistor 9 takes place in the clock of the other clock 8, which comprises a clock NAND gate 33.
  • the output of the clock NAND gate 33 is fed back to an input of the clock NAND gate 33 via a combination of two parallel ohmic clock resistors 34, 35, a clock diode 36, and a clock capacitor 37, one input Another input of the clock NAND gate 33 can be beaufschiagbar with a positive voltage.
  • the circuit combination of the clock resistors 34, 35, the clock diode 36 and the clock capacitor 37, a constant, clocked timing is achieved, the clock of the clock 8 is lower than the clock of the clock 4.
  • the clock capacitor 37 is discharged more slowly than charged, for example, when the size of the resistor 35 is ten times the size of the resistor 34, wherein the value of the resistor 34, for example, 1M ⁇ and the value of the resistor 35, for example, 10M ⁇ .
  • the clock 8 configured as a transistor switch 10 is switched, the resistor 9 in the cycle of the second clock 8 in the circuit parallel to the first resistor 6 and coupled to ground.
  • the other clock 8 is set via the clock NAND gate 33 at the beginning of a control of the electromagnet for attracting the armature 3 about a corresponding control in motion, while after tightening the armature 3 only the clock 4 is in action.
  • the another clock 8 also be switched on permanently, so that alternating tightening and holding sections.
  • a peak filter resistor 38 and a peak filter capacitor 39 are provided for filtering voltage spikes.
  • a filter 40 is provided which may comprise an inductance and / or a ferrite core.
  • the current detection switch 7 may also be formed as an inverting comparator whose output is coupled to the RESET input of the flip-flop 31.
  • a first of the two inputs of the comparator is serially coupled to the resistor 6 and detects the voltage on the circuit.
  • the other, second input of the comparator is supplied with a comparison voltage whose value is set by a voltage divider 41, which is connected between a rectified AC operating voltage supply terminal 42 and the second input of the comparator.
  • the voltage divider 41 comprises three series-connected ohmic resistors 43, 44, 45, of which the resistor 45 is coupled to ground.
  • the second input of the comparator is connected to a node which is between the resistor 44 and the resistor 45.
  • a node located between resistor 43 and resistor 44 is connected to ground via a forward biased diode 46.
  • the comparator supplies a high level to the RESET input of the flip-flop 31. If the detected voltage is greater, the comparator supplies a low level to the RESET input. Input of the flip-flop 31, and the switch 5 is opened by the flip-flop 31. If the detected voltage falls below the predetermined reference voltage value, the comparator supplies a high level to the RESET input of the flip-flop 31 and the switch 5 is opened and closed again in time with the clock 4.
  • a voltage divider 47 connected between the rectifier 14 and the clock NAND gate 25 may be provided.
  • This comprises two serially connected resistive voltage dividing resistors 48, 49, of which the voltage dividing resistor 49 is grounded, and a capacitor 50 connected in parallel with the voltage dividing resistor 49.
  • the voltage application of one input of the one clock NAND gate 25 to The clocking of the clock generator 4 is carried out via the voltage divider 47, wherein the clocking must be carried out in compliance with a predetermined condition, when the AC operating voltage is above 80% of its rated voltage and is interrupted when the AC operating voltage drops below 20% of its rated voltage.
  • the voltage dividing resistor 48 is adapted to the voltage applied to the terminals 12, 13 AC operating voltage in conjunction with the voltage dividing resistor 49 just so that at a certain percentage of operating AC voltage is greater than 20% and less than 80% of the AC operating voltage, the upper trigger threshold of the coupled to the voltage dividing resistor 48 clock NAND gate 25 is exceeded and the timing starts, so that the timing is performed at the latest at 80% of the rated voltage.
  • the clock NAND gate 25 Since the clock NAND gate 25 has a "hysteresis" due to Schmitt triggers on the inputs, the clock is maintained even if the voltage drops below the value of the upper trigger threshold and only interrupted when the lower threshold of the Schmitt trigger falls below the input.
  • a voltage value is defined, from which the clocking is performed, while it is further ensured that the clocking is interrupted at a drop below 20% of the rated voltage.
  • the capacitor 50 which is connected in parallel with the voltage-dividing resistor 49, bridges the zero crossing during AC operation.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Relay Circuits (AREA)
  • Electronic Switches (AREA)
  • Electromagnets (AREA)
  • Control Of Linear Motors (AREA)

Description

Die Erfindung betrifft eine Vorrichtung zur Ansteuerung eines Elektromagneten nach dem Oberbegriff des Anspruchs 1.The invention relates to a device for controlling an electromagnet according to the preamble of claim 1.

In Sicherheitsschaltungen zur Ver- und Entriegelung von Türen, Klappen oder dergleichen werden Elektromagneten verwendet, die einen gemäß der Ansteuerung eines Solenoids betätigbaren Anker aufweisen, der aufgrund seiner Position eine Tür ver- bzw. entriegelt. Dabei muß gewährleistet sein, daß sich der Anker während eines Anzugsabschnitts korrekt bewegt, und daß sich eine vom Solenoid ausgeübte Magnetkraft zum Halten des Ankers in seiner Position während eines Halteabschnitts bei einer möglichst niedrigen angelegten Betriebsspannung nicht soweit reduziert, daß der Anker durch äußere Störungen, insbesondere Erschütterungen, abfällt.In safety circuits for locking and unlocking of doors, flaps or the like electromagnets are used which have an actuatable according to the control of a solenoid armature, which locks or unlocks a door due to its position. It must be ensured that the armature moves correctly during a tightening section, and that a magnetic force exerted by the solenoid for holding the armature in position during a holding section at the lowest possible applied operating voltage is not reduced so far that the armature due to external disturbances, especially vibrations, drops.

Eine vorbestimmte Spannungsbeaufschlagung des Solenoids trägt einer Kontrolle des durch das Solenoid fließenden Stroms in Hinblick auf einen Energieverlust oder der Betriebstemperatur des Solenoids allerdings keine Rechnung, so daß es vorteilhaft ist, die Spannungsbeaufschlagung bei einer Erwärmung des Solenoids und/oder bei Erreichen bestimmter Stromwerte zu unterbrechen, um einen Energieverlust durch eine Wärmeerzeugung des Solenoids zu verhindern.However, a predetermined voltage loading of the solenoid does not account for control of the current flowing through the solenoid with respect to energy loss or the operating temperature of the solenoid, so that it is advantageous to interrupt the application of voltage when the solenoid heats up and / or certain current values are reached to prevent energy loss through heat generation of the solenoid.

Aus DE 196 47 215 A ist eine Vorrichtung zur Austeuerung eines Elektromagneten nach dem Oberbegriff des Patentanspruchs 1 bekannt.Out DE 196 47 215 A a device for Austeuerung an electromagnet according to the preamble of claim 1 is known.

Aus DE 43 41 797 A1 ist es bekannt, einen durch einen elektromagnetischen Verbraucher, z.B. in Form eines Solenoids, fließenden Strom durch eine Stromregelung auf einen vorbestimmten Wert zu begrenzen, der in einem Anzugsabschnitt höher ist als in einem Halteabschnitt. Dazu wird ein Schalter verwendet, mit dem das Solenoid von der an ihn angelegten Spannung temporär getrennt werden kann, wenn der jeweilige Stromwert erreicht wird. Der Schalter wird wieder geschlossen, wenn ein jeweiliger niedrigerer Stromwert erreicht wird. Die Vorrichtung verwendet zur Bestimmung des durch den Solenoid fließenden Stroms eine Meßvorrichtung, die mit einer Stromauswertung gekoppelt ist. Der von der Stromauswertung gemessene Strom wird von einem Stromregler mit einem Höchststrom verglichen, wobei der Stromregler ein Ansteuersignal erzeugt, mit dem eine Endstufe beaufschlagt wird, die ihrerseits den Schalter ansteuert. Dies ist aufgrund der Verwendung zahlreicher unterschiedlicher Bauteile aufwendig und weist insbesondere mit der Stromauswertung und der Endstufe mehrkomponentige Bauteile auf.Out DE 43 41 797 A1 It is known to limit a current flowing through an electromagnetic consumer, for example in the form of a solenoid current control by a current control to a predetermined value which is higher in a tightening portion than in a holding portion. For this purpose, a switch is used with which the solenoid can be temporarily separated from the voltage applied to it when the respective current value is reached. The switch is closed again when a respective lower current value is reached. The device uses a measuring device coupled to a current evaluation to determine the current flowing through the solenoid. The current measured by the current evaluation is compared by a current regulator with a maximum current, wherein the current controller generates a drive signal, which is applied to an output stage, which in turn drives the switch. This is complicated due to the use of many different components and has in particular with the current evaluation and the power amplifier multi-component components.

Aus DE 195 22 582 C2 ist es bekannt, zur Ansteuerung eines Elektromagneten, der einen Anker betätigt, an ein Solenoid eine Spannung in einer vorbestimmten Periodizität anzulegen. Eine Periode weist Zeitabschnitte unterschiedlicher Länge auf. Es kann zwischen Anzugs- und längeren Halteabschnitten unterschieden werden, wobei die Anzugsabschnitte im wesentlichen einen langen Impuls und die Halteabschnitte mehrere kürzere Impulse zur Spannungsbeaufschlagung des Solenoids aufweisen. Die Anzugsabschnitte dienen einem Anziehen des Solenoids, wobei am Ende eines Anzugsabschnitts - aufgrund der größeren Impulslänge gegenüber den Impulslängen während der Halteabschnitte - ein größerer Strom als am Ende eines Impulses der Halteabschnitte durch das Solenoid fließt. Die Halteabschnitte dienen einer Aufrechterhaltung eines kleineren, durch das Solenoid fließenden Stroms, der ausreicht, den Anker in seiner Position zu halten.Out DE 195 22 582 C2 It is known to apply to a solenoid a voltage in a predetermined periodicity for driving an electromagnet, which operates an armature. A period has time periods of different lengths. It can be distinguished between tightening and longer holding sections, wherein the tightening sections essentially have a long pulse and the holding sections a plurality of shorter pulses for applying voltage to the solenoid. The tightening sections serve to attract the solenoid, wherein at the end of a tightening section - due to the greater pulse length compared to the Pulse lengths during the holding sections - a larger current than at the end of a pulse of the holding sections flows through the solenoid. The holding portions serve to maintain a smaller current flowing through the solenoid sufficient to hold the armature in position.

Aufgabe der Erfindung ist es, eine Vorrichtung zum Ansteuern eines Elektromagneten gemäß dem Oberbegriff des Anspruchs 1 zu schaffen, die einfache Bauteile verwendet und einfacher aufgebaut ist.The object of the invention is to provide a device for driving an electromagnet according to the preamble of claim 1, which uses simple components and has a simpler structure.

Diese Aufgabe wird entsprechend den Merkmalen des Anspruchs 1 gelöst.This object is achieved according to the features of claim 1.

Dadurch kann ein sehr einfacher Aufbau mit einfachen Bauteilen erreicht werden.This allows a very simple construction can be achieved with simple components.

Weitere Ausgestaltungen der Erfindung sind der nachfolgenden Beschreibung und den Unteransprüchen zu entnehmen.Further embodiments of the invention are described in the following description and the dependent claims.

Die Erfindung wird nachstehend anhand eines in den beigefügten Abbildungen dargestellten Ausführungsbeispiels näher erläutert.The invention is explained below with reference to an embodiment shown in the accompanying drawings.

Fig. 1 zeigt eine vereinfachte und schematische Darstellung eines Schaltbilds einer Ausführungsform einer Schaltung zur Ansteuerung eines Elektromagneten. Fig. 1 shows a simplified and schematic representation of a circuit diagram of an embodiment of a circuit for driving an electromagnet.

Fig. 2 zeigt ein Beispiel eines detaillierten Schaltbilds der Ausführungsform von Fig. 1. Fig. 2 FIG. 12 shows an example of a detailed circuit diagram of the embodiment of FIG Fig. 1 ,

Fig. 3 zeigt ein Beispiel eines detaillierten Schaltbilds einer weiteren Ausführungsform von Fig. 1. Fig. 3 shows an example of a detailed circuit diagram of another embodiment of Fig. 1 ,

Die Schaltung nach Fig. 1 weist einen Elektromagneten mit einem Solenoid 1 auf, das mit einer Gleichspannung einer Spannungsquelle 2 beaufschlagbar ist und zum Betätigen eines zugehörigen federbeaufschlagten Ankers 3 dient. Ein mit der Spannungsquelle 2 verbundener Taktgeber 4 ist mit einem seriell mit dem Solenoid 1 geschalteten Schalter 5 gekoppelt, wodurch der Schalter 5 entsprechend dem Takt des Taktgebers 4 geschlossen und geöffnet wird. Im geschlossenen Zustand des Schalters 5 liegt an dem Solenoid 1 die Gleichspannung der Spannungsquelle 2 an.The circuit after Fig. 1 has an electromagnet with a solenoid 1, which can be acted upon by a DC voltage of a voltage source 2 and serves to actuate an associated spring-loaded armature 3. A timer 4 connected to the power source 2 is coupled to a switch 5 serially connected to the solenoid 1, whereby the switch 5 is closed and opened in accordance with the clock of the timer 4. When the switch 5 is closed, the DC voltage of the voltage source 2 is applied to the solenoid 1.

Seriell mit dem Schalter 5 ist ein erster ohmscher Widerstand 6, der an Masse gekoppelt ist, verbunden, über den ein Spannungsabfall erfolgt, wenn der Schalter 5 geschlossen und die Gleichspannung an dem Solenoid 1 angelegt ist.Connected in series with the switch 5 is a first ohmic resistor 6, which is coupled to ground, via which a voltage drop occurs when the switch 5 is closed and the DC voltage is applied to the solenoid 1.

Zum temporären Unterbrechen der Spannungsbeaufschlagung des Solenoids 1 ist eine einen Stromnachweisschalter 7 umfassende Einrichtung vorgesehen. Der Stromnachweisschalter 7 ist parallel zum ersten Widerstand 6 und seriell zum Schalter 5 gekoppelt und schaltet die Spannungsquelle 2 des Solenoids 1 durch Öffnen des Schalters 5 temporär ab, solange ein vorbestimmter, durch das Solenoid 1 fließender Strom durch den Stromnachweisschalter 7 nachgewiesen wird. Fällt der nachgewiesene Strom wieder ab, beendet der Stromnachweisschalter 7 seinen Einfluß auf den Schalter 5 und dieser wird wieder durch den Taktgeber 4 betätigt. Der durch das Solenoid 1 fließende Strom wird somit durch das Schalten des Stromnachweisschalters 7 begrenzt, wobei durch den Stromnachweisschalter 7 der durch den ersten ohmschen Widerstand 6 fließende Strom erfaßt wird. Dabei ist die Größe des ersten Widerstands 6 in Verbindung mit dem Stromnachweisschalter 7 so gewählt, daß durch das Solenoid 1 ein Strom fließen kann, der ausreicht, um den Anker 3 in seiner Stellung zu halten - es fließt dann somit ein Haltestrom.For temporarily interrupting the voltage application of the solenoid 1, a device comprising a current detection switch 7 is provided. The current detection switch 7 is coupled in parallel to the first resistor 6 and serially to the switch 5 and temporarily turns off the power source 2 of the solenoid 1 by opening the switch 5 as long as a predetermined current flowing through the solenoid 1 is detected by the current detection switch 7. If the detected current drops again, the current detection switch 7 stops its influence on the switch 5 and this is again actuated by the clock 4. The current flowing through the solenoid 1 is thus limited by the switching of the current detection switch 7, wherein the current flowing through the first ohmic resistor 6 current is detected by the current detection switch 7. In this case, the size of the first resistor 6 in conjunction with the current detection switch 7 is selected so that that through the solenoid 1, a current can flow, which is sufficient to hold the armature 3 in its position - it then flows then a holding current.

Über einen weiteren Taktgeber 8, dessen Takt zumindest teilweise mit dem des Taktgebers 4 überlappt und niedriger ist als dieser, ist ein weiterer, zweiter ohmscher Widerstand 9 parallel zum ersten Widerstand 6 in den Stromkreis über einen Schalter 10 schaltbar, wobei der zweite Widerstand 9 an Masse gekoppelt wird. Die Größe des zweiten Widerstands 9 ist so gewählt, daß sich ein kleinerer Gesamtwiderstand ergibt. Vorzugsweise ist die Größe des ersten Widerstands 6 größer als die des zweiten Widerstands 9. Wenn der Schalter 4 geschlossen und der zweite Widerstand 9 zugeschaltet ist, kann ein höherer Strom durch das Solenoid 1 fließen, da der Strom verstärkt über den sich ergebenden kleineren Gesamtwiderstand abfließt, ohne daß die Ansprechschwelle des Stromnachweisschalters 7 erreicht wird und dieser schaltet. Auf diese Weise ist es durch das getaktete Zuschalten des zweiten Widerstands 9 bei geschlossenem Schalter 5 möglich, daß ein höherer Strom als der Haltestrom, nämlich ein Anzugsstrom, durch das Solenoid 1 fließen kann. Bei Erreichen der Ansprechschwelle am Stromnachweisschalter 7 wird auch in diesem Fall die Spannungsbeaufschlagung des Solenoids 1 temporär über den Stromnachweisschalter 7 unterbrochen.About another clock 8, the clock overlaps at least partially with that of the clock 4 and is lower than this, another, second resistor 9 is parallel to the first resistor 6 in the circuit via a switch 10 switchable, wherein the second resistor 9 at Mass is coupled. The size of the second resistor 9 is chosen so that there is a smaller total resistance. Preferably, the size of the first resistor 6 is greater than that of the second resistor 9. When the switch 4 is closed and the second resistor 9 is switched on, a higher current can flow through the solenoid 1, as the current flows off more efficiently over the resulting smaller total resistance Without the threshold of the current detection switch 7 is reached and this switches. In this way, it is possible by the clocked connection of the second resistor 9 with the switch 5 closed, that a higher current than the holding current, namely a starting current, can flow through the solenoid 1. Upon reaching the threshold at the current detection switch 7, the voltage application of the solenoid 1 is temporarily interrupted via the current detection switch 7 in this case.

Vorzugsweise ist ein Freilaufkreis für das Solenoid 1 vorgesehen, der eine parallel zum Solenoid 1 gekoppelte Freilaufdiode 11 umfaßt. Der Strom durch das Solenoid 1 wird bei geöffnetem Schalter 5 über eine durch die Induktivität des Solenoids 1 bestimmte Zeit aufrechterhalten und durch die Freilaufdiode 11 kurzgeschlossen. Dabei kann der Freilaufkreis gegebenenfalls eine Reihenschaltung weiterer Dioden und/oder Transistoren umfassen.Preferably, a freewheeling circuit for the solenoid 1 is provided, which comprises a parallel to the solenoid 1 coupled freewheeling diode 11. The current through the solenoid 1 is maintained with the switch 5 open over a certain time by the inductance of the solenoid 1 time and short-circuited by the freewheeling diode 11. In this case, the freewheeling circuit may optionally comprise a series connection of further diodes and / or transistors.

Gemäß Fig. 2 ist die Spannungsquelle 2 als Gleichspannungsregelungseinrichtung für eine über die Anschlüsse 12, 13 angekoppelte Betriebswechselspannung ausgestaltet. In der Gleichspannungsregelungseinrichtung ist ein Gleichrichter 14 vorgesehen, an den zwei gegeneinander geschaltete Zenerdioden 15, 16 und ein Kondensator 17 parallel gekoppelt sind. Der Kondensator 17 ist dabei seriell mit Masse verbunden. Die Gleichspannungsregelungseinrichtung umfaßt weiter eine mit dem Kondensator 17 gekoppelte Diode 18, der ein Feldeffekt-Transistor 19 folgt. Der Feldeffekttransistor 19 wird über zwei hintereinander geschaltete, seriell mit dem Kondensator 17 verbundene Widerstände 20, 21 geschaltet, wobei eine an Masse gekoppelte Begrenzerdiode 22 zwischen den beiden Widerständen 20, 21 und dem Feldeffekttransistor 19 vorgesehen ist. Im geschlossenen Zustand schaltet der Feldeffekttransistor 19 einen Widerstand 23 und einen an Masse gekoppelten Kondensator 24 als Filter in den Stromkreis der Gleichspannungsregelungseinrichtung.According to Fig. 2 is the voltage source 2 designed as a DC voltage control device for a via the terminals 12, 13 coupled operating AC voltage. In the DC voltage control device, a rectifier 14 is provided, are coupled to the two mutually connected Zener diodes 15, 16 and a capacitor 17 in parallel. The capacitor 17 is connected in series with ground. The DC voltage control device further comprises a coupled to the capacitor 17 diode 18, which follows a field effect transistor 19. The field effect transistor 19 is connected via two resistors 20, 21 connected in series, connected in series with the capacitor 17, a limiter diode 22 coupled to ground being provided between the two resistors 20, 21 and the field effect transistor 19. When closed, the field effect transistor 19 switches a resistor 23 and a capacitor coupled to ground 24 as a filter in the circuit of the DC voltage control device.

Der Taktgeber 4 zum getakteten Schließen des in diesem Ausführungsbeispiel als Feldeffekt-Transistor ausgebildeten Schalters 5, umfaßt ein Taktgeber-NAND-Gatter 25, von dem ein Eingang mit der Spannungsquelle 2 zur Stromversorgung gekoppelt und weiter mit einem hohen Pegel beaufschlagt ist. Der Ausgang des Taktgeber-NAND-Gatters 25 wird über eine Schaltungskombination aus einem ohmschen Taktgeber-Widerstand 26, einer Taktgeber-Diode 27 und einem Taktgeber-Kondensator 28 auf den anderen Eingang des Taktgeber-NAND-Gatters 25 zurückgeführt. Durch die Schaltungskombination des Taktgeber-Widerstands 26, der Taktgeber-Diode 27 und des Taktgeber-Kondensators 28 wird ein konstantes, getaktetes Zeitverhalten des Ausgangssignals des Taktgeber-NAND-Gatters 25 erreicht, wobei das Aufladen des Taktgeber-Kondensators 28 langsamer erfolgt als das Entladen.The clock 4 for clocked closing of the switch 5 formed in this embodiment as a field effect transistor comprises a clock NAND gate 25, from which an input to the voltage source 2 is coupled to the power supply and further supplied with a high level. The output of clock NAND gate 25 is fed back to the other input of clock NAND gate 25 through a combination of one ohmic clock resistor 26, one clock diode 27 and one clock capacitor 28. By the circuit combination of the clock resistor 26, the clock diode 27 and the clock capacitor 28, a constant, clocked timing of the output signal of the clock NAND gate 25 is achieved, wherein the charging of the clock capacitor 28 is slower than the discharge ,

Der Ausgang des Taktgebers 4 ist auch mit einem SET-Eingang eines zwei NAND-Gatter 29, 30 umfassenden Flipflops 31 verbunden, das aufgrund des am SET-Eingang anliegenden Signals des Taktgebers 4 den Schalter 5 mittels des Signals am Q-Ausgang getaktet öffnet bzw. schließt.The output of the clock generator 4 is also connected to a SET input of a flip-flop 31 comprising two NAND gates 29, 30 which, due to the signal of the clock generator 4 applied to the SET input, opens or switches the switch 5 clocked by means of the signal at the Q output closes.

Der Stromnachweisschalter 7 ist als Transistor ausgebildet, dessen Basis-Emitter-Strecke die Spannung am Stromkreis erfaßt. Der Emitter des Transistors ist mit Masse verbunden, und der Kollektor sowohl über einen ohmschen Widerstand 32 mit hohem Potential als auch mit einem RESET-Eingang des Flipflops 31 gekoppelt. Der parallel zum ohmschen Widerstand 6 und seriell zum Solenoid 1 gekoppelte Transistor wird leitend, wenn die Spannung am Widerstand 6 die Spannung zwischen Basis und Emitter des Transistors übersteigt. Dann wechselt das am RESET-Eingang des Flipflops 31 anliegende Signal, da der über den Widerstand 32 fließende Strom über den Stromnachweisschalter 7 nach Masse abfließt. Das Flipflop 31 öffnet dann den Schalter 5, und das Anlegen der Gleichspannung an das Solenoid 1 wird temporär unterbrochen.The current detection switch 7 is designed as a transistor whose base-emitter path detects the voltage on the circuit. The emitter of the transistor is connected to ground, and the collector is coupled both via a high-potential ohmic resistor 32 and to a RESET input of the flipflop 31. The parallel to the resistor 6 and connected in series with the solenoid 1 transistor becomes conductive when the voltage across the resistor 6 exceeds the voltage between the base and emitter of the transistor. Then the signal applied to the RESET input of the flip-flop 31 changes, since the current flowing through the resistor 32 flows through the current detection switch 7 to ground. The flip-flop 31 then opens the switch 5, and the application of the DC voltage to the solenoid 1 is temporarily interrupted.

Fällt die Spannung an dem als Stromnachweisschalter 7 verwendeten Transistor wieder ab, sperrt der Transistor und das Signal am RESET-Eingang des Flipflops 31 wechselt wieder, so daß der Schalter 5 wieder gemäß dem Takt des Taktgebers 4 geschaltet wird.If the voltage at the transistor used as current detection switch 7 drops again, the transistor blocks and the signal at the RESET input of the flip-flop 31 changes again, so that the switch 5 is switched again according to the clock of the clock 4.

Die getaktete Zuschaltung des Widerstands 9 erfolgt in dem Takt des weiteren Taktgebers 8, der ein Taktgeber-NAND-Gatter 33 umfaßt. Der Ausgang des Taktgeber-NAND-Gatters 33 wird über eine Schaltungskombination aus zwei parallelen ohmschen Taktgeber-Widerständen 34, 35, einer Taktgeber-Diode 36 und einem Taktgeber-Kondensator 37 wieder auf einen Eingang des Taktgeber-NAND-Gatters 33 zurückgeführt, wobei ein weiterer Eingang des Taktgeber-NAND-Gatters 33 mit einer positiven Spannung beaufschiagbar ist. Durch die Schaltungskombination aus den Taktgeber-Widerständen 34, 35, der Taktgeber-Diode 36 und dem Taktgeber-Kondensator 37 wird ein konstantes, getaktetes Zeitverhalten erreicht, wobei der Takt des Taktgebers 8 niedriger als der Takt des Taktgebers 4 ist. Dabei wird der Taktgeber-Kondensator 37 langsamer entladen als aufgeladen, wenn beispielsweise die Größe des Widerstands 35 der zehnfachen Größe des Widerstands 34 entspricht, wobei der Wert des Widerstands 34 beispielsweise 1MΩ und der Wert des Widerstands 35 beispielsweise 10MΩ beträgt. Durch den Taktgeber 8 wird der als Transistor ausgestaltete Schalter 10 geschaltet, der den Widerstand 9 im Takt des zweiten Taktgebers 8 in den Stromkreis parallel zum ersten Widerstand 6 schaltet und an Masse koppelt.The clocked connection of the resistor 9 takes place in the clock of the other clock 8, which comprises a clock NAND gate 33. The output of the clock NAND gate 33 is fed back to an input of the clock NAND gate 33 via a combination of two parallel ohmic clock resistors 34, 35, a clock diode 36, and a clock capacitor 37, one input Another input of the clock NAND gate 33 can be beaufschiagbar with a positive voltage. The circuit combination of the clock resistors 34, 35, the clock diode 36 and the clock capacitor 37, a constant, clocked timing is achieved, the clock of the clock 8 is lower than the clock of the clock 4. In this case, the clock capacitor 37 is discharged more slowly than charged, for example, when the size of the resistor 35 is ten times the size of the resistor 34, wherein the value of the resistor 34, for example, 1MΩ and the value of the resistor 35, for example, 10MΩ. By the clock 8 configured as a transistor switch 10 is switched, the resistor 9 in the cycle of the second clock 8 in the circuit parallel to the first resistor 6 and coupled to ground.

Der weitere Taktgeber 8 wird über das Taktgeber-NAND-Gatter 33 zu Beginn einer Ansteuerung des Elektromagneten zum Anziehen des Ankers 3 etwa über eine entsprechende Steuerung in Gang gesetzt, während nach dem Anziehen des Ankers 3 nur noch der Taktgeber 4 in Tätigkeit ist. Jedoch kann der weitere Taktgeber 8 auch permanent zugeschaltet sein, so daß sich Anzugs- und Halteabschnitte abwechseln.The other clock 8 is set via the clock NAND gate 33 at the beginning of a control of the electromagnet for attracting the armature 3 about a corresponding control in motion, while after tightening the armature 3 only the clock 4 is in action. However, the another clock 8 also be switched on permanently, so that alternating tightening and holding sections.

Vor dem Stromnachweisschalter 7 sind zur Filterung von Spannungsspitzen ein Spitzenfilterwiderstand 38 und ein Spitzenfilterkondensator 39 vorgesehen.In front of the current detection switch 7, a peak filter resistor 38 and a peak filter capacitor 39 are provided for filtering voltage spikes.

Im Stromkreis zwischen dem Solenoid 1 und der Spannungsquelle 2 ist ein Filter 40 vorgesehen, der eine Induktivität und/oder einen Ferritkern umfassen kann.In the circuit between the solenoid 1 and the voltage source 2, a filter 40 is provided which may comprise an inductance and / or a ferrite core.

Wie in der weiteren in Fig. 3 dargestellten Ausführungsform gezeigt, kann der Stromnachweisschalter 7 auch als invertierender Komparator ausgebildet sein, dessen Ausgang mit dem RESET-Eingang des Flipflops 31 gekoppelt ist. Ein erster der beiden Eingänge des Komparators ist seriell mit dem Widerstand 6 gekoppelt und erfaßt die Spannung am Stromkreis. Der andere, zweite Eingang des Komparators wird mit einer Vergleichsspannung beaufschlagt, deren Wert durch einen Spannungsteiler 41, der zwischen einem die gleichgerichtete Betriebswechselspannung liefernden Anschluß 42 und dem zweiten Eingang des Komparators geschaltet ist, eingestellt wird. Der Spannungsteiler 41 umfaßt drei in Reihe geschaltete ohmsche Widerstände 43, 44, 45, von denen der Widerstand 45 an Masse gekoppelt ist. Der zweite Eingang des Komparators ist mit einem Knoten verbunden, der zwischen dem Widerstand 44 und dem Widerstand 45 liegt. Ein zwischen dem Widerstand 43 und dem Widerstand 44 liegender Knoten ist über eine in Durchlaßrichtung geschaltete Diode 46 mit Masse verbunden.As in the other in Fig. 3 shown embodiment, the current detection switch 7 may also be formed as an inverting comparator whose output is coupled to the RESET input of the flip-flop 31. A first of the two inputs of the comparator is serially coupled to the resistor 6 and detects the voltage on the circuit. The other, second input of the comparator is supplied with a comparison voltage whose value is set by a voltage divider 41, which is connected between a rectified AC operating voltage supply terminal 42 and the second input of the comparator. The voltage divider 41 comprises three series-connected ohmic resistors 43, 44, 45, of which the resistor 45 is coupled to ground. The second input of the comparator is connected to a node which is between the resistor 44 and the resistor 45. A node located between resistor 43 and resistor 44 is connected to ground via a forward biased diode 46.

Der Komparator liefert, solange die am ersten Eingang erfaßte Spannung den am zweiten Eingang anliegenden, vorbestimmten Vergleichsspannungswert nicht übersteigt, einen hohen Pegel an den RESET-Eingang des Flipflops 31. Wird die erfaßte Spannung größer, liefert der Komparator einen niedrigen Pegel an den RESET-Eingang des Flipflops 31, und der Schalter 5 wird vom Flipflop 31 geöffnet. Fällt die erfaßte Spannung unter den vorbestimmten Vergleichsspannungswert ab, liefert der Komparator einen hohen Pegel an den RESET-Eingang des Flipflops 31 und der Schalter 5 wird wieder im Takt des Taktgebers 4 geöffnet und geschlossen.As long as the voltage detected at the first input does not exceed the predetermined reference voltage value applied to the second input, the comparator supplies a high level to the RESET input of the flip-flop 31. If the detected voltage is greater, the comparator supplies a low level to the RESET input. Input of the flip-flop 31, and the switch 5 is opened by the flip-flop 31. If the detected voltage falls below the predetermined reference voltage value, the comparator supplies a high level to the RESET input of the flip-flop 31 and the switch 5 is opened and closed again in time with the clock 4.

Des weiteren kann, wie in Fig. 3 gezeigt, bei den dargestellten Ausführungsformen eine zwischen den Gleichrichter 14 und das Taktgeber-NAND-Gatter 25 geschaltete Spannungsteilungseinrichtung 47 vorgesehen sein. Diese umfaßt zwei in Reihe geschaltete ohmsche Spannungsteilungs-Widerstände 48, 49, von denen der Spannungsteilungs-Widerstand 49 geerdet ist, und einen parallel zum Spannungsteilungs-Widerstand 49 geschalteten Kondensator 50. Die Spannungsbeaufschlagung des einen Eingangs des einen Taktgeber-NAND-Gatters 25 zur Durchführung der Taktung des Taktgebers 4 erfolgt über die Spannungsteilungseinrichtung 47, wobei die Taktung in Erfüllung einer vorgegebenen Bedingung durchgeführt werden muß, wenn die Betriebswechselspannung über 80% ihrer Nennspannung liegt und unterbrochen wird, wenn die Betriebswechselspannung unter 20% ihrer Nennspannung sinkt. Dies trägt einem trotz abgeschalteter Spannungsquelle vorhandenen Reststrom dahingehend Rechnung, daß gewährleistet ist, daß trotz dieses Reststroms für Werte unter 20% der Nennspannung die Taktung und damit ein Anziehen des Solenoids 1 verhindert wird. Dazu ist der Spannungsteilungs-Widerstand 48 an die an den Anschlüssen 12, 13 anliegende Betriebswechselspannung in Verbindung mit dem Spannungsteilungs-Widerstand 49 gerade so angepaßt, daß bei einem bestimmten Prozentsatz der Betriebswechselspannung, der über 20% und unter 80% der Betriebswechselspannung liegt, die obere Triggerschwelle des an den Spannungsteilungs-Widerstand 48 gekoppelten Taktgeber-NAND-Gatters 25 überschritten wird und die Taktung beginnt, so daß die Taktung spätestens bei 80% der Nennspannung durchgeführt wird. Da das Taktgeber-NAND-Gatter 25 eine "Hysterese" infolge von Schmitt-Triggern an den Eingängen aufweist, wird die Taktung auch bei einem Absinken der Spannung unter den Wert der oberen Triggerschwelle aufrechterhalten und erst unterbrochen, wenn der untere Schwellwert des Schmitt-Triggers des Eingangs unterschritten wird. Somit wird mit dem Verhältnis der beiden Widerstandswerte der Spannungsteilungs-Widerstände 48, 49 und der genannten Hysterese ein Spannungswert definiert, ab dem die Taktung durchgeführt wird, wobei weiter gewährleistet ist, daß die Taktung bei einem Absinken unter 20% der Nennspannung unterbrochen wird.Furthermore, as in Fig. 3 shown, in the illustrated embodiments, a voltage divider 47 connected between the rectifier 14 and the clock NAND gate 25 may be provided. This comprises two serially connected resistive voltage dividing resistors 48, 49, of which the voltage dividing resistor 49 is grounded, and a capacitor 50 connected in parallel with the voltage dividing resistor 49. The voltage application of one input of the one clock NAND gate 25 to The clocking of the clock generator 4 is carried out via the voltage divider 47, wherein the clocking must be carried out in compliance with a predetermined condition, when the AC operating voltage is above 80% of its rated voltage and is interrupted when the AC operating voltage drops below 20% of its rated voltage. This takes account of a residual current present in spite of the disconnected voltage source, in order to ensure that, despite this residual current, the timing and thus the tightening of the solenoid 1 is prevented for values below 20% of the nominal voltage. For this purpose, the voltage dividing resistor 48 is adapted to the voltage applied to the terminals 12, 13 AC operating voltage in conjunction with the voltage dividing resistor 49 just so that at a certain percentage of operating AC voltage is greater than 20% and less than 80% of the AC operating voltage, the upper trigger threshold of the coupled to the voltage dividing resistor 48 clock NAND gate 25 is exceeded and the timing starts, so that the timing is performed at the latest at 80% of the rated voltage. Since the clock NAND gate 25 has a "hysteresis" due to Schmitt triggers on the inputs, the clock is maintained even if the voltage drops below the value of the upper trigger threshold and only interrupted when the lower threshold of the Schmitt trigger falls below the input. Thus, with the ratio of the two resistance values of the voltage dividing resistors 48, 49 and the said hysteresis a voltage value is defined, from which the clocking is performed, while it is further ensured that the clocking is interrupted at a drop below 20% of the rated voltage.

Der parallel zum Spannungsteilungs-Widerstand 49 geschaltete Kondensator 50 überbrückt dabei beim Wechselstrombetrieb den Nulldurchgang.The capacitor 50, which is connected in parallel with the voltage-dividing resistor 49, bridges the zero crossing during AC operation.

Claims (20)

  1. A device for actuating an electromagnet, in particular for a safety circuit, which has an armature (3) which is activated in accordance with the actuation of a solenoid (1); comprising a switch (5) which is connected in series to the solenoid (1) and via which a d.c. voltage is applicable to the solenoid (1) by closing the switch (5); wherein
    a device for temporarily interrupting the application of the voltage as long as a predetermined current flowing through the solenoid (1) is detected; and
    a first clock generator (4) for actuating the switch (5) in a predetermined first clock cycle; as well as
    a first and a second ohmic resistor (6, 9), which are each connected in series to the solenoid (1) and in parallel with one another; are provided
    wherein the device comprises a current detection switch (7), connected in series to the switch (5), for detecting the current flowing through the solenoid (1);
    wherein the magnitude of the first ohmic resistor (6) which is connected in parallel with the current detection switch (7) determining, in conjunction with the response threshold of the current detection switch (7), the magnitude of the holding current for the armature (3); and
    wherein the second ohmic resistor (9) is connectable via a further switch (10) in the circuit for generating an attraction current for the armature (3), via a further, second clock generator (8) in a predetermined second clock cycle, which at least partially overlaps with the first clock cycle;
    characterized in that
    the current detection switch (7) and the first clock generator (4) are formed separately from each other and
    the switch (5) is coupled with the first clock generator (4) via a flip-flop (31), the flip-flop (31) also coupling the current detection switch (7) with the switch (5).
  2. The device according to Claim 1, characterized in that the first resistor (6) is larger than the second resistor (9).
  3. The device according to Claim 1 or 2, characterized in that a recovery circuit, comprising a recovery diode (11), is provided for the solenoid (1).
  4. The device according to any one of Claims 1 to 3, characterized in that the clock cycle of the first clock generator (4) is higher than that of the second clock generator (8).
  5. The device according to any one of Claims 1 to 4, characterized in that the clock generator (4) has an upper and a lower input trigger threshold for actuating or terminating the clocking, and is connected to a node which is located between two ohmic voltage divider resistors (48, 49) which are connected in series, one voltage divider resistor (48) of which being connected to an operating voltage, and the other voltage divider resistor (49) being connected to earth, the ratio between the two values of the voltage divider resistors (48, 49) determining the start and the end of the clocking with respect to the operating voltage and the upper and lower input trigger threshold.
  6. The device according to Claim 5, characterized in that the operating voltage is a rectified a.c. voltage, and a capacitor (50) is connected in parallel with the other voltage divider resistor (49).
  7. The device according to any one of Claims 1 to 6, characterized in that the first resistor (6) is connected to earth.
  8. The device according to any one of Claims 1 to 7, characterized in that the second resistor (9) can be connected to earth via a further switch (10) which is actuated by the second clock generator (8).
  9. The device according to Claim 8, characterized in that the further switch (10) is a transistor.
  10. The device according to any one of Claims 1 to 9, characterized in that the switch (5) is a transistor, preferably a field-effect transistor.
  11. The device according to any one of Claims 1 to 10, characterized in that the current detection switch (7) is a transistor, it being possible to record the current which is to be detected by means of the base-emitter voltage of said transistor.
  12. The device according to any one of Claims 1 to 10, characterized in that the current detection switch (7) comprises a comparator.
  13. The device according to any one of Claims 1 to 12, characterized in that in order to temporarily interrupt the application of the voltage it is possible to open the switch (5) by means of the current detection switch (7).
  14. The device according to Claim 13, characterized in that the output of the first clock generator (4) is connected to the SET input of the flip-flop (31), and the current detection switch (7) is connected to the RESET input of the flip-flop (31), the Q output of the flip-flop (31) being connected to the switch (5).
  15. The device according to any one of Claims 1 to 14, characterized in that the flip-flop (31) comprises two NAND gates (29, 30).
  16. The device according to any one of Claims 1 to 15, characterized in that the first clock generator (4) comprises a clock generator NAND gate (25) whose output is fed back to one of the two inputs via a circuit combination comprising a clock generator resistor (26), a clock generator diode (27) and a clock generator capacitor (28), the clock of the output of the clock generator NAND gate (25) being predetermined with a time constant which can be selected essentially by the clock generator resistor (26) and the clock generator capacitor (28).
  17. The device according to Claim 16, characterized in that the other of the two inputs of the clock generator NAND gate (25) is at a constant high level.
  18. The device according to Claim 16, characterized in that the other of the two inputs of the clock generator NAND gate (25) is connected to a node which is located between two ohmic voltage divider resistors (48, 49) which are connected in series, one voltage divider resistor (48) being connected to an operating voltage, and the other voltage divider resistor (49) being connected to earth, the start and the end of the clocking being adjustable in relation to the operating voltage and the upper or lower trigger threshold of the clock generator NAND gate (25) by means of the ratio between the two values of the voltage divider resistors (48,49).
  19. The device according to Claim 18, characterized in that the operating voltage is a rectified a.c. voltage, and a capacitor (50) is connected in parallel with the other voltage divider resistor (49).
  20. The device according to any one of Claims 1 to 19, characterized in that the second clock generator (8) comprises a clock generator NAND gate (33) whose output is fed back to an input of the clock generator NAND gate (33) via a circuit combination comprising two ohmic clock generator resistors (34, 35), a clock generator diode (36) and a clock generator capacitor (37).
EP20020014583 2001-07-14 2002-07-02 Device to control an electromagnet Expired - Lifetime EP1276120B1 (en)

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EP1276120A2 (en) 2003-01-15
CA2393180A1 (en) 2003-01-14
DE10134346A1 (en) 2003-02-06
US6798634B2 (en) 2004-09-28
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JP3803309B2 (en) 2006-08-02
CA2393180C (en) 2010-09-14

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