EP1256168A2 - System carrier for freely programmable blocks - Google Patents

System carrier for freely programmable blocks

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Publication number
EP1256168A2
EP1256168A2 EP00987400A EP00987400A EP1256168A2 EP 1256168 A2 EP1256168 A2 EP 1256168A2 EP 00987400 A EP00987400 A EP 00987400A EP 00987400 A EP00987400 A EP 00987400A EP 1256168 A2 EP1256168 A2 EP 1256168A2
Authority
EP
European Patent Office
Prior art keywords
buses
system carrier
slots
carrier according
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP00987400A
Other languages
German (de)
French (fr)
Other versions
EP1256168B1 (en
Inventor
Helmuth Gesch
Markus Waidelich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IsarTec GmbH
Original Assignee
Helmuth Gesch
Markus Waidelich
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Helmuth Gesch, Markus Waidelich filed Critical Helmuth Gesch
Publication of EP1256168A2 publication Critical patent/EP1256168A2/en
Application granted granted Critical
Publication of EP1256168B1 publication Critical patent/EP1256168B1/en
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means

Definitions

  • the invention relates to a system carrier for freely programmable modules (gate arrays) interconnected by buses.
  • HDL Hardware Description Language
  • FPGA freely programmable logic modules
  • the invention has for its object to provide a universally usable system carrier that does not require a switching matrix, so that very short and always predeterminable signal tents can be achieved and the system can be verified in real time.
  • this task is solved according to the invention in that at least three identically configured slots are arranged on the system carrier for accommodating one module each with a freely programmable module (gate array), which can be changed in its position with the slot can be coupled, the slots being firmly connected to one another via three groups of buses.
  • a freely programmable module gate array
  • the main advantage is achieved because. the system support, which is initially available as an unconfigured board, only contains a dedicated bus system. Only after being equipped with the modules that contain freely programmable modules and have a matching architecture, does the system board receive its logical function through programming and is immediately ready for use. With the help of the individually configurable modules, which can be positioned where they can be changed, it is possible to quickly establish an optimal connection for the application via the bus system, which allows different access to the electronic possibilities of the board.
  • the modular structure of the system has the further advantage that existing FPGA building systems of different sizes can always be used and the latest technological generation of FPGA building systems can be used.
  • the freely programmable module is permanently connected to a circuit board, from the underside of which pins (pins) protrude, which can be inserted into the corresponding receptacles in the slots.
  • the configuration of the pins and the seats are symmetrical.
  • each module can be coupled to the slot by rotating it through two different positions.
  • Each of the bus groups has different tasks and possibly also data transfer capacities.
  • each bus connects two slots directly with each other.
  • the second group of buses local buses
  • all slots are interconnected.
  • the third group of buses connects all slots with each other and also creates a chain with another system carrier.
  • the architecture of the system carrier thus allows several system carriers to be connected in parallel to expand the capacity.
  • Some of the buses can also be connected to a memory.
  • FIG. 1 shows the schematic view of two system carriers (boards) according to the invention, each with a dedicated bus system
  • FIG. 2 shows the schematic view of a conventional board, in which the components are connected to a common switching matrix via fixed wiring,
  • FIG. 3 shows a schematic view of a system carrier according to the example in FIG. 1,
  • FIG. 4 shows the basic representation of a part of the system carrier with a slot onto which a module is plugged
  • FIG. 5 shows the top view of the module from FIG. 4
  • FIG. 6 shows the bottom view of the module
  • FIG. 7 shows the top view of a system carrier (board) with a possible layout and without electrical wiring
  • FIG. 8 shows a section of the board of FIG. 7 with a bus system and possible assignment with modules with maximum utilization of all buses
  • Figure 9 shows a variant of Figure 8 with partial utilization of the buses and
  • Figure 10 is a view corresponding to Figure 9 with different positioning of the modules.
  • FIG. 2 shows the already explained prior art with a system carrier (board 10), on which a total of three programmed modules A, B, C are firmly placed.
  • the modules (modules 12) are also connected to each other and with a via connecting cables 14 (buses) Switch matrix 16 connected.
  • a system carrier board 10
  • the modules modules 12
  • the switching matrix 16 causes unpredictable delay delays, so that no real-time capability is achieved.
  • FIG. 1 shows two system carriers (boards 10, 10 ') designed according to the invention, each of which likewise has three modules 12 with freely programmable FPGA modules.
  • Modules A, B, C carries, which, however, are not fixed on the board 10, but can be replaced and additionally changed in their position.
  • each module 12 contains a freely programmable gate array structure (FPGA) 18, which is fixedly mounted on a circuit board 20.
  • Pins 22 protrude from the underside of the board 20 and can be inserted into the corresponding receiving seats 26 of slots 24 provided on the system carrier (board 10) (cf. also FIG. 7).
  • FIG. 7 shows the top view of a possible embodiment for the system carrier 10 without electrical wiring with three slots 24, the slot 24 with its receiving seats 26 being recognizable in the lower part of FIG. 7, while the other two slots are each occupied by a module 12 .
  • FIGS. 6 and 7 it can be seen that the configuration of the pins 22 on the underside of the module 12 and the receiving seats 26 of the slot 24 correspond to one another, with symmetry being evident both with regard to the two axes and with the center. This results in the extremely advantageous possibility of mounting each module 12 m in at least two different positions on the slot 24.
  • two different positions on the slot 22 can be produced by rotating the modules 12 through 180 °, which will be discussed in more detail below.
  • the system carrier 10 is also essential that this is equipped with a dedicated bus system.
  • Figure 1 it is indicated that all three for the modules 12 provided slots 24 on the board 10 are connected in pairs by ring-shaped, private buses 28.
  • the private buses 28 can have different capacities and tasks, which is symbolized in FIG. 3 by the bus 28 shown as a continuous line, the bus 28 ′ shown in broken lines and the bus 28 ′′ indicated by broken lines.
  • a second group of buses is formed by the so-called local buses 30, which connect all the slots 22 on the board 10 to one another.
  • These local buses 30 are shown in FIG. 3 as zigzag lines.
  • the third group of buses is formed by so-called global buses 32, which are symbolized in FIG. 3 as wavy lines and which connect all the slots 24 to one another and additionally establish a connection to a further system carrier, in the example of FIG. 1 to the system carrier 10 '.
  • the global bus 32 can thus be used to connect several system carriers in order to expand the overall system
  • FIG. 3 indicates that the private bus 28 ′′ is connected to a memory 34 and one of the local buses 30 is connected to another memory 34
  • FIG. 8 shows a section of the right part of FIG. 7 with the three slots 24, which are connected to one another by the private buses 28 (solid lines), 28 '(dashed lines) and 28' (dash-dotted lines).
  • the local buses 30 are shown in accordance with FIG. 3 as zigzag lines and the global buses 32 as serpentine lines
  • All three slots 24 in FIG. 8 are occupied by modules 12 whose freely programmed modules 18 (FPGA) are programmed in this way are that there is a full load, which is indicated in Figure 8 by the completely occupied pin groups of different shades of gray, which correspond to the shades of gray of the connected buses.
  • FPGA freely programmed modules 18
  • FIGS. 9 and 10 show an application example in which there is no maximum utilization of the buses, but only different partial utilization. Again, all pins 22 (pins) of the FPGA construction system 18 are connected to one another by the buses, but are not completely electrically occupied; the unoccupied areas are shown in black. In FIG. 9, due to partial occupancy of the left halves of modules A, B, C, the private buses 28, 28 ', 28' 'are only partially utilized, while the local buses 30 and the global buses 32 are fully utilized (right-hand parts of the slot 24 m Figure 9).
  • modules A, B, C are rotated by 180 °, their only partially occupied areas, which were previously in the left part, are connected to the private buses 28, 28 ', 28' ', so that they are now fully utilized
  • the dedicated bus structure allows an optimal signal connection of the freely programmable gate arrays with each other.
  • the modular structure means that the FPGAs can be freely selected and can be interchanged and positioned, so that the internal bus structure is optimally utilized.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Circuits Of Receivers In General (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Electrotherapy Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Programmable Controllers (AREA)
  • Communication Control (AREA)
  • Stored Programmes (AREA)
  • Bus Control (AREA)

Abstract

A system carrier for freely programmable blocks that are connected to one another by buses, of a carrier body, at least three identically configured connectors disposed on the carrier body and being configured to receive in each case one module with a freely programmable block, the module being couplable to the connector and its position changable, and three groups of buses arranged to fixedly connect the connectors to one another.

Description

Systemtrager für frei programmierbare Bausteine System support for freely programmable blocks
Beschreibungdescription
D e Erfindung betrifft einen Systemtrager für frei programmierbare, durch Busse miteinander verbundene Bausteine (Gate Arrays) .The invention relates to a system carrier for freely programmable modules (gate arrays) interconnected by buses.
Bei der Entwicklung komplexer integrierter Schaltungen (IC) werden zunächst Logikentwurfe erstellt, die auf einer sprachlichen Beschreibung m einer Programmiersprache beruhen, der sogenannten Hardware Description Language (HDL) Zur funktionalen Verifikation hoch integrierter mikroelektronischer Schaltkreise ist es üblich, m der Entwicklungsphase eine Logiksimulation einzusetzen Ergänzend zur Simulation wurden m den letzten Jahren spezielle Plattformen für die Logik-Emulation eingesetzt. Die als Netzliste vorliegende und zu verifizierende Schaltung wurde auf frei programmierbare Logikbausteine (FPGA) partitioniert , die durch spezielle, programmierbare Schaltmatrizen verbunden sind. Diese Technik ist als Rapid Prototypmg bekannt . Der Entwickler wird damit m die Lage versetzt, m einer frühen Entwicklungsphase eines Logikentwurfes die Schaltung auf der Plattform zu testen, bevor diese m Silizium gegossen wird. Der Nachteil dieses Systems besteht darin, daß aufgrund der Schaltmatrix erhebliche Laufzeitverzogerungen m Kauf genommen werden müssen, was die Verifikation des Logikdesigns erschwert oder gar unmöglich macht. Hinzu kommt, daß die programmierbaren Bausteine auf der Plattform fest platziert und durch ebenfalls feste Verbindungen über die Schaltmatrix miteinander verbunden sind.When developing complex integrated circuits (IC), logic designs are first created that are based on a language description in a programming language, the so-called Hardware Description Language (HDL). For functional verification of highly integrated microelectronic circuits, it is common to use a logic simulation in the development phase Special platforms for logic emulation have been used for simulation in recent years. The circuit available and to be verified as a network list was partitioned onto freely programmable logic modules (FPGA), which are connected by special, programmable switching matrices. This technique is known as rapid prototyping. This enables the developer to test the circuit on the platform in an early development phase of a logic design before it is cast in silicon. The disadvantage of this system is that due to the switching matrix, considerable delay delays have to be taken into account, which makes the verification of the logic design difficult or even impossible. In addition, the programmable modules are firmly placed on the platform and are connected to one another by likewise fixed connections via the switching matrix.
Der Erfindung liegt die Aufgabe zugrunde, einen universell verwendbaren Systemtrager zur Verfugung zu stellen, der ohne Schaltmatrix auskommt, so daß sehr kurze und stets fest vorbestimmbare Signallaufzelten erreicht werden und das System in Echtzeit verifiziert werden kann.The invention has for its object to provide a universally usable system carrier that does not require a switching matrix, so that very short and always predeterminable signal tents can be achieved and the system can be verified in real time.
Bei einem Systemtrager der eingangs umπssenen Gattung wird diese Aufgabe erfmdungsgemaß dadurch gelost, daß auf dem Systemtrager mindestens drei identisch konfigurierte Steckplatze für die Aufnahme von jeweils einem Modul mit frei programmierbarem Baustein (Gate-Array) angeordnet sind, das m seiner Position veränderbar mit dem Steckplatz koppelbar ist, wobei die Steckplatze über drei Gruppen von Bussen fest untereinander verbunden sind.In the case of a system carrier of the type initially defined, this task is solved according to the invention in that at least three identically configured slots are arranged on the system carrier for accommodating one module each with a freely programmable module (gate array), which can be changed in its position with the slot can be coupled, the slots being firmly connected to one another via three groups of buses.
Damit wird der wesentliche Vorteil erzielt, da. der Systemtrager, der zunächst als nicht konfiguriertes Board vorliegt, lediglich ein dezidiertes Bus-System enthalt. Erst nach der Bestückung mit den Modulen, die frei programmierbare Bausteine enthalten und eine übereinstimmende Architektur haben, erhalt das System-Board durch Programmierung seine logische Funktion und ist sofort emsatzfahig . Mit Hilfe der individuell konfigurierbaren Bausteine, die m ihrer Position ver nderbar platziert werden können, ist es möglich, rasch eine auf die Anwendungszwecke abgestimmte, optimale Verbindung über das Bus- System herzustellen, das einen unterschiedlichen Zugriff auf die elektronischen Möglichkeiten des Boards erlaubt. Durch den modularen Aufbau des Systems ergibt sich der weitere Vorteil, daß immer auf vorhandene FPGA-Bausteme unterschiedlicher Große zurückgegriffen und die neueste technologische Generation von FPGA-Baustemen eingesetzt werden kann.The main advantage is achieved because. the system support, which is initially available as an unconfigured board, only contains a dedicated bus system. Only after being equipped with the modules that contain freely programmable modules and have a matching architecture, does the system board receive its logical function through programming and is immediately ready for use. With the help of the individually configurable modules, which can be positioned where they can be changed, it is possible to quickly establish an optimal connection for the application via the bus system, which allows different access to the electronic possibilities of the board. By the The modular structure of the system has the further advantage that existing FPGA building systems of different sizes can always be used and the latest technological generation of FPGA building systems can be used.
In jedem Modul ist der frei programmierbare Baustein fest mit einer Platine verbunden, von deren Unterseite Steckstifte (Pins) abstehen, die m entsprechende Aufnahmesitze der Steckplatze eingesteckt werden können. Die Konfiguration der Steckstifte und der Aufnahmesitze ist hierbei symmetrisch.In each module, the freely programmable module is permanently connected to a circuit board, from the underside of which pins (pins) protrude, which can be inserted into the corresponding receptacles in the slots. The configuration of the pins and the seats are symmetrical.
Wenn die Konfiguration der Steckstifte und der Aufnahmesitze punktsymmetrisch ist, kann jedes Modul durch Drehen um 180° m zwei unterschiedlichen Positionen mit dem Steckplatz gekoppelt werden. Daneben ist es auch denkbar, unterschiedlicne Positionen der Module durch Langsverschiebung auf dem Steckplatz zu erzeugen.If the configuration of the pins and the seats are point-symmetrical, each module can be coupled to the slot by rotating it through two different positions. In addition, it is also conceivable to generate different positions of the modules by moving them longitudinally on the slot.
Jeder der Bus -Gruppen hat unterschiedliche Aufgaben und ggf. auch Datenubertragungskapazitaten. Bei einer ersten Gruppe der Busse (private Busse) verbindet jeder Bus jeweils zwei Steckplatze direkt miteinander. Mittels der zweiten Gruppe der Busse (lokale Busse) werden alle Steckplatze untereinander verbunden. Die dritte Gruppe der Busse (globale Busse) verbindet alle Steckplatze untereinander und stellt zusätzlich eine Verkettung mit einem weiteren Systemtrager her. D e Architektur des Systemtragers erlaubt es somit, mehrere Systemtrager zur Erweiterung der Kapazität parallel zu schalten.Each of the bus groups has different tasks and possibly also data transfer capacities. In a first group of buses (private buses), each bus connects two slots directly with each other. Using the second group of buses (local buses), all slots are interconnected. The third group of buses (global buses) connects all slots with each other and also creates a chain with another system carrier. The architecture of the system carrier thus allows several system carriers to be connected in parallel to expand the capacity.
Einige der Busse können zusätzlich mit einem Speicher verbunden sein .Some of the buses can also be connected to a memory.
Die Erfindung ist nachstehend an einem Ausfunrungsbeispiel erläutert, das m der Zeichnung dargestellt ist. Es zeigen. Figur 1 die schematische Ansicht von zwei Systemtragern (Boards) gemäß der Erfindung mit jeweils einem dezidierten Bus-System, Figur 2 die schematische Ansicht eines herkömmlichen Boards, bei dem die Bausteine über feste Verdrahtungen mit einer gemeinsamen Schaltmatrix verbunden sind,The invention is explained below using an exemplary embodiment which is shown in the drawing. Show it. 1 shows the schematic view of two system carriers (boards) according to the invention, each with a dedicated bus system, FIG. 2 shows the schematic view of a conventional board, in which the components are connected to a common switching matrix via fixed wiring,
Figur 3 eine schematische Ansicht eines Systemtragers nach dem Beispiel der Figur 1,FIG. 3 shows a schematic view of a system carrier according to the example in FIG. 1,
Figur 4 die Schmttdarstellung eines Teils des Systemtragers mit Steckplatz, auf den ein Modul aufgesteckt wird, Figur 5 die Draufsicht des Moduls der Figur 4, Figur 6 die Unteransicht des Moduls,FIG. 4 shows the basic representation of a part of the system carrier with a slot onto which a module is plugged, FIG. 5 shows the top view of the module from FIG. 4, FIG. 6 shows the bottom view of the module,
Figur 7 die Draufsicht eines Systemtragers (Board) mit möglichem Layout und ohne elektrische Verdrahtung,FIG. 7 shows the top view of a system carrier (board) with a possible layout and without electrical wiring,
Figur 8 einen Ausschnitt aus dem Board der Figur 7 mit Bus- System und möglicher Belegung mit Modulen bei maximaler Auslastung aller Busse,8 shows a section of the board of FIG. 7 with a bus system and possible assignment with modules with maximum utilization of all buses,
Figur 9 eine Variante der Figur 8 bei Teilauslastung der Busse undFigure 9 shows a variant of Figure 8 with partial utilization of the buses and
Figur 10 eine der Figur 9 entsprechende Ansicht bei unterschiedlicher Positionierung der Module.Figure 10 is a view corresponding to Figure 9 with different positioning of the modules.
Figur 2 zeigt den bereits erläuterten Stand der Technik mit einem Systemtrager (Board 10) , auf dem insgesamt drei programmierte Bausteine A, B, C fest platziert sind Die Bausteine (Module 12) sind über ebenfalls fixe Verbmdungsleitungen 14 (Busse) untereinander und mit einer Schaltmatrix 16 verbunden. Wie bereits erwähnt, ist ein derartiges System nicht flexibel, wodurch Herstellung und Anwendung für Emulationszwecke teuer und zeitaufwendig sind. Von erheblichen Nachteil ist ferner, daß die Schaltmatrix 16 nicht voraussagbare Laufzeitverzogerungen verursacht, so daß keine Echtzeitfahigkeit erreicht wird.Figure 2 shows the already explained prior art with a system carrier (board 10), on which a total of three programmed modules A, B, C are firmly placed. The modules (modules 12) are also connected to each other and with a via connecting cables 14 (buses) Switch matrix 16 connected. As previously mentioned, such a system is not flexible, making it expensive and time consuming to manufacture and use for emulation purposes. A further disadvantage is that the switching matrix 16 causes unpredictable delay delays, so that no real-time capability is achieved.
In Figur 1 sind zwei erfmdungsgemaß ausgebildete Systemtrager (Boards 10, 10') εchematisch dargestellt, von denen jeder ebenfalls drei Module 12 mit frei programmierbaren FPGA- Bausteinen A, B, C tragt, die jedoch nicht fest auf dem Board 10 sitzen, sondern ausgewechselt und zusätzlich m ihrer Position verändert werden können.FIG. 1 shows two system carriers (boards 10, 10 ') designed according to the invention, each of which likewise has three modules 12 with freely programmable FPGA modules. Modules A, B, C carries, which, however, are not fixed on the board 10, but can be replaced and additionally changed in their position.
In den Figuren 4 bis 6 ist schematisch angedeutet, daß jedes Modul 12 einen frei programmierbaren Gate-Array-Baustem (FPGA) 18 enthalt, der fest auf einer Platine 20 angebracht ist. Von der Unterseite des Platine 20 stehen Steckstifte 22 (Pins) ab, die m entsprechende Aufnahmesitze 26 von Steckplatzen 24 eingesteckt werden können, die auf dem Systemtrager (Board 10) vorgesehen sind (vgl. auch Figur 7) .4 to 6 schematically indicate that each module 12 contains a freely programmable gate array structure (FPGA) 18, which is fixedly mounted on a circuit board 20. Pins 22 protrude from the underside of the board 20 and can be inserted into the corresponding receiving seats 26 of slots 24 provided on the system carrier (board 10) (cf. also FIG. 7).
Figur 7 zeigt die Draufsicht einer möglichen Ausfuhrungsform für den Systemtrager 10 ohne elektrische Verdrahtung mit drei Steckplatzen 24, wobei im unteren Teil der Figur 7 der Steckplatz 24 mit seinen Aufnahmesitzen 26 zu erkennen ist, während die beiden anderen Steckplatze mit jeweils einem Modul 12 belegt sind. Em Vergleich der Figuren 6 und 7 laßt erkennen, daß die Kon iguration der Steckstifte 22 auf der Unterseite des Moduls 12 und der Aufnahmesitze 26 des StecKplatzes 24 einander entsprechen, wobei eine Symmetrie sowohl hinsichtlich der beiden Achsen als auch des Zentrums zu erkennen ist. Daraus ergibt sich die äußerst vorteilhafte Möglichkeit, jedes Modul 12 m wenigstens zwei unterschiedlichen Positionen auf dem Steckplatz 24 anzubringen. Bei Punktsymmetrie lassen sich durch Drehen der Module 12 um 180° zwei unterschiedliche Positionen auf dem Steckplatz 22 herstellen, worauf weiter unten noch naher eingegangen wird. Daneben ist es auch denkbar, bei entsprechender Konfiguration der Steckplatze 24 und der Steckstifte 22 unterschiedliche Positionierungen durch Verschieben der Module 12 relativ zum Steckplatz 24 zu erreichen.FIG. 7 shows the top view of a possible embodiment for the system carrier 10 without electrical wiring with three slots 24, the slot 24 with its receiving seats 26 being recognizable in the lower part of FIG. 7, while the other two slots are each occupied by a module 12 , By comparing FIGS. 6 and 7, it can be seen that the configuration of the pins 22 on the underside of the module 12 and the receiving seats 26 of the slot 24 correspond to one another, with symmetry being evident both with regard to the two axes and with the center. This results in the extremely advantageous possibility of mounting each module 12 m in at least two different positions on the slot 24. In the case of point symmetry, two different positions on the slot 22 can be produced by rotating the modules 12 through 180 °, which will be discussed in more detail below. In addition, it is also conceivable to achieve different positions by moving the modules 12 relative to the slot 24 if the slots 24 and the pins 22 are configured accordingly.
Für die universelle Emsaczfahigkeiπ des Systemtragers 10 st ferner wesentlich, das dieser mit einem dezidierten Bus-Systen ausgestattet ist. In Figur 1 ist angedeutet, daß alle drei für die Module 12 vorgesehenen Steckplatze 24 auf dem Board 10 durch ringförmig dargestellte, private Busse 28 paarweise miteinander verbunden sind. Die privaten Busse 28 können unterschiedliche Kapazitäten und Aufgaben haben, was m Figur 3 durch den als durchgehende Linie dargestellten Bus 28, den gestrichelt wiedergegebenen Bus 28' und den strichpunktiert angedeuteten Bus 28' ' symbolisiert ist.For the universal Emsaczfahigkeiπ the system carrier 10 is also essential that this is equipped with a dedicated bus system. In Figure 1 it is indicated that all three for the modules 12 provided slots 24 on the board 10 are connected in pairs by ring-shaped, private buses 28. The private buses 28 can have different capacities and tasks, which is symbolized in FIG. 3 by the bus 28 shown as a continuous line, the bus 28 ′ shown in broken lines and the bus 28 ″ indicated by broken lines.
Eine zweite Gruppe der Busse wird durch die sogenannten lokalen Busse 30 gebildet, die alle Steckplatze 22 auf dem Board 10 untereinander verbinden Diese lokalen Busse 30 sind m Figur 3 als Zickzacklinien eingezeichnet.A second group of buses is formed by the so-called local buses 30, which connect all the slots 22 on the board 10 to one another. These local buses 30 are shown in FIG. 3 as zigzag lines.
Schließlich wird die dritte Gruppe der Busse durch sogenannte globale Busse 32 gebildet, die m Figur 3 als Wellenlinien symbolisiert sind und die alle Steckplatze 24 untereinander verbinden und zusätzlich eine Verbindung zu einem weiteren Systemtrager herstellen, im Beispiel der Figur 1 zum Systemtrager 10' . Durch den globalen Bus 32 können somit mehrere Systemtrager zusammengeschlossen werden, um das Gesamtsystem zu erweiternFinally, the third group of buses is formed by so-called global buses 32, which are symbolized in FIG. 3 as wavy lines and which connect all the slots 24 to one another and additionally establish a connection to a further system carrier, in the example of FIG. 1 to the system carrier 10 '. The global bus 32 can thus be used to connect several system carriers in order to expand the overall system
In Figur 3 ist schließlich angedeutet, daß der private Bus 28' ' mit einem Speicher 34 und einer der lokalen Busse 30 mit einem anderen Speicher 34 verbunden sindFinally, FIG. 3 indicates that the private bus 28 ″ is connected to a memory 34 and one of the local buses 30 is connected to another memory 34
Figur 8 zeigt einen Ausschnitt aus dem rechten Teil der Figur 7 mit den drei Stec platzen 24, die durch die privaten Busse 28 (durchgezogene Linien) , 28 ' (gestrichelte Linien) und 28 ' (strichpunktiert eingezeichnet) miteinander verbunden sind Die lokalen Busse 30 sind m Übereinstimmung mit Figur 3 als Zickzacklinien und die globalen Busse 32 als Schlangenlinien dargestelltFIG. 8 shows a section of the right part of FIG. 7 with the three slots 24, which are connected to one another by the private buses 28 (solid lines), 28 '(dashed lines) and 28' (dash-dotted lines). The local buses 30 are shown in accordance with FIG. 3 as zigzag lines and the global buses 32 as serpentine lines
Alle drei Steckplatze 24 der Figur 8 sind mit Modulen 12 belegt, deren frei programmierte Bausteine 18 (FPGA) so programmiert sind, daß sich eine Vollauslastung ergibt, was in Figur 8 durch die komplett belegten Pin-Gruppen unterschiedlicher Grautone angedeutet ist, die den Grautonen der angeschlossenen Busse entsprechen.All three slots 24 in FIG. 8 are occupied by modules 12 whose freely programmed modules 18 (FPGA) are programmed in this way are that there is a full load, which is indicated in Figure 8 by the completely occupied pin groups of different shades of gray, which correspond to the shades of gray of the connected buses.
Die Figuren 9 und 10 zeigen ein Anwendungsbeispiel, bei dem sich jeweils keine maximale Auslastung der Busse ergibt, sondern nur unterschiedliche Teilauslastungen. Auch hier sind wieder alle Steckstifte 22 (Pins) der FPGA-Bausteme 18 durch die Busse untereinander verbunden, aber nicht vollständig elektrisch belegt; die nicht belegten Bereiche sind schwarz eingezeichnet So sind m Figur 9 aufgrund einer Teilbelegung der linken Hälften der Module A, B, C die privaten Busse 28, 28', 28'' nur teilweise ausgelastet, wahrend die lokalen Busse 30 und die globalen Busse 32 vollständig ausgelastet sind (rechte Teile der Steckplatze 24 m Figur 9) .FIGS. 9 and 10 show an application example in which there is no maximum utilization of the buses, but only different partial utilization. Again, all pins 22 (pins) of the FPGA construction system 18 are connected to one another by the buses, but are not completely electrically occupied; the unoccupied areas are shown in black. In FIG. 9, due to partial occupancy of the left halves of modules A, B, C, the private buses 28, 28 ', 28' 'are only partially utilized, while the local buses 30 and the global buses 32 are fully utilized (right-hand parts of the slot 24 m Figure 9).
Wenn nun, wie m Figur 10 angedeutet, die Module A, B, C um 180° gedreht werden, sind ihre nur teilweise belegten Bereiche, die vorher im linken Teil lagen, mit den privaten Bussen 28, 28', 28' ' verbunden, so daß diese jetzt voll ausgelastet sindIf, as indicated in FIG. 10, the modules A, B, C are rotated by 180 °, their only partially occupied areas, which were previously in the left part, are connected to the private buses 28, 28 ', 28' ', so that they are now fully utilized
Daraus ergibt sich, daß durch einfaches Drehen - oder, wie angedeutet, Verschieben - der Module 12 die Kapazität und dar unterschiedliche Verwendungszweck der Busse optimal genutzt werden können Einer der Verwendungszwecke kann beispielsweise der Zugriff auf einen Speicher 34 sein.It follows from this that by simply rotating - or, as indicated, moving - the modules 12, the capacity and the different uses of the buses can be optimally used. One of the uses can be, for example, access to a memory 34.
Bei der Erfindung besteht die Möglichkeit, das System mit nur einem oder zwe Modulen zu betreiben oder Module zu verwenden, die kleiner als die Steckplatze 24 sind, so daß - wie angedeutet - die unterschiedliche Positionierung statt durch Drehen durch Verschieben hergestellt werden kann.In the invention, it is possible to operate the system with only one or two modules or to use modules that are smaller than the slots 24, so that - as indicated - the different positioning can be produced by moving instead of rotating.
Die Vorteile der Erfindung sind vor allem darin zu sehen, daß eine weitgehende Echtzeitfahigkeit realisiert wird, so daß viele unterschiedliche Schalti ngsentwurfe simuliert und einer spater realisierten Halbleiterschaltung m Funktion und zeitlichem Verhalten nachgebildet werden können. Da keine Schaltmatrix zur Verbindung kritischer Signalpfade erforderlich ist, können die sehr kurzen Signallaufzelten vorhergesagt werden.The advantages of the invention can be seen above all in the fact that extensive real-time capability is realized, so that many different circuit designs can be simulated and a later implemented semiconductor circuit can be reproduced in terms of function and temporal behavior. Since no switching matrix is required to connect critical signal paths, the very short signal tents can be predicted.
Die dezidierte Busstruktur erlaubt eine optimale Signalver- bindung der frei programmierbaren Gate-Arrays untereinander. Der modulare Aufbau hat zur Folge, daß die FPGAs frei gewählt werden können und untereinander austauschbar und positionierbar sind, so daß die interne Busstruktur optimal ausgelastet wird. The dedicated bus structure allows an optimal signal connection of the freely programmable gate arrays with each other. The modular structure means that the FPGAs can be freely selected and can be interchanged and positioned, so that the internal bus structure is optimally utilized.

Claims

Patentansprüche claims
1. Systemtrager für frei programmierbare, durch Busse miteinander verbundene Bausteine (Gate-Arrays) , dadurch gekennzeichnet, daß auf dem Systemtrager (10) mindestens drei identisch konfigurierte Steckplatze (24) für die Aufnahme von jeweils einem Modul (12) mit frei programmierbarem Baustein (18) angeordnet sind, das m seiner Position veränderbar mit dem Steckplatz (24) koppelbar ist, wobei die Steckplatze (24) über drei Gruppen von Bussen (28, 30, 32) fest untereinander verbunden sind.1. System support for freely programmable modules (gate arrays) interconnected by buses, characterized in that on the system support (10) at least three identically configured slots (24) for accommodating one module (12) each with a freely programmable module (18) are arranged, which can be changed in its position and coupled to the slot (24), the slots (24) being firmly connected to one another via three groups of buses (28, 30, 32).
2. Systemtrager nach Anspruch 1, dadurch gekennzeichnet, daß jeder frei programmierbare Baustein (FPGA 18) fest mit einer Platine (20) verbunden ist, von deren Unterseite Steckstifte (Pins 22) abstehen, die m entsprechende Aufnahmesitze (26) der Steckplatze (24) einsteckbar sind.2. System carrier according to claim 1, characterized in that each freely programmable module (FPGA 18) is firmly connected to a circuit board (20), from the underside of which pins (pins 22) protrude, the m corresponding receiving seats (26) of the slots (24 ) can be inserted.
3. Systemtrager nach Anspruch 2, dadurch gekennzeichnet, daß die Konfiguration der Steckstifte (22) und der Aufnahmesitze (26) symmetrisch ist .3. System carrier according to claim 2, characterized in that the configuration of the pins (22) and the receiving seats (26) is symmetrical.
4. Systemtrager nach Anspruch 3, dadurch gekennzeichnet, daß die Konfiguration der Steckstifte (22) und der Aufnahmesitze (26) punktsymmetrisch ist, wodurch das Modul (12) durch Drehen um 180° m zwei unterschiedlichen Positionen mit dem Steckplatz (24) koppelbar ist.4. System carrier according to claim 3, characterized in that the configuration of the pins (22) and the receiving seats (26) is point-symmetrical, whereby the module (12) by rotating 180 ° m two different positions with the slot (24) can be coupled ,
5. Systemtrager nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß bei einer ersten Gruppe der Busse (private Busse) jeder Bus (28) jeweils zv/ei Steckplatze (24) direkt miteinander verαmdet . 5. System carrier according to one of the preceding claims, characterized in that in a first group of buses (private buses) each bus (28) each zv / ei slots (24) verαmdet directly with each other.
6. Systemtrager nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß mittels der zweiten Gruppe der Busse (lokale Busse 30) alle Steckplatze (24) untereinander verbunden werden.6. System carrier according to one of the preceding claims, characterized in that by means of the second group of buses (local buses 30) all slots (24) are interconnected.
7. Systemtrager nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die dritte Gruppe der Busse (globale Busse 32) alle Steckplatze (24) untereinander verbindet und zusatzlich eine Verbindung zu einem weiteren Systemtrager (10 ') herstellt.7. System carrier according to one of the preceding claims, characterized in that the third group of buses (global buses 32) connects all slots (24) to one another and additionally creates a connection to a further system carrier (10 ').
8. Systemtrager nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß einzelne Busse (28, 30) mit einem Speicher8. System carrier according to one of the preceding claims, characterized in that individual buses (28, 30) with a memory
(34) verbunden sind. (34) are connected.
EP00987400A 2000-02-18 2000-12-14 System carrier for freely programmable blocks Expired - Lifetime EP1256168B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE20003010U DE20003010U1 (en) 2000-02-18 2000-02-18 System carrier for freely programmable modules
DE20003010U 2000-02-18
PCT/EP2000/012712 WO2001061852A2 (en) 2000-02-18 2000-12-14 System carrier for freely programmable blocks

Publications (2)

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EP1256168A2 true EP1256168A2 (en) 2002-11-13
EP1256168B1 EP1256168B1 (en) 2004-03-10

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EP (1) EP1256168B1 (en)
JP (1) JP2003523570A (en)
AT (1) ATE261632T1 (en)
AU (1) AU2001223655A1 (en)
CA (1) CA2400231A1 (en)
DE (2) DE20003010U1 (en)
IL (1) IL151023A0 (en)
WO (1) WO2001061852A2 (en)

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DE10159480B4 (en) * 2001-12-04 2006-05-24 Daimlerchrysler Ag control device
US8004855B2 (en) * 2006-07-07 2011-08-23 Itt Manufacturing Enterprises, Inc. Reconfigurable data processing system

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JPS62150404A (en) 1985-12-25 1987-07-04 Mitsubishi Electric Corp Program controller
US5000692A (en) * 1988-09-14 1991-03-19 Matsushita Electric Works, Ltd. I/O relay interface module
EP0498544B1 (en) * 1991-02-04 1997-08-06 International Business Machines Corporation Multimedia expansion unit
US5424589A (en) 1993-02-12 1995-06-13 The Board Of Trustees Of The Leland Stanford Junior University Electrically programmable inter-chip interconnect architecture
US5935232A (en) * 1995-11-20 1999-08-10 Advanced Micro Devices, Inc. Variable latency and bandwidth communication pathways
US5703759A (en) 1995-12-07 1997-12-30 Xilinx, Inc. Multi-chip electrically reconfigurable module with predominantly extra-package inter-chip connections
US6351786B2 (en) * 1998-08-24 2002-02-26 Racal Instr Inc VXI backplane system improvements and methods
US6567518B1 (en) * 1998-08-28 2003-05-20 Teltronics, Inc. Method of field programmable gate array configuration

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Title
See references of WO0161852A2 *

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WO2001061852A3 (en) 2002-01-03
DE50005636D1 (en) 2004-04-15
DE20003010U1 (en) 2000-05-04
EP1256168B1 (en) 2004-03-10
US20030005198A1 (en) 2003-01-02
WO2001061852A2 (en) 2001-08-23
IL151023A0 (en) 2003-02-12
US6874051B2 (en) 2005-03-29
CA2400231A1 (en) 2001-08-23
JP2003523570A (en) 2003-08-05
ATE261632T1 (en) 2004-03-15
AU2001223655A1 (en) 2001-08-27

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