EP1253498B1 - Voltage regulator - Google Patents

Description

The present invention relates to a device according to claim 1, i. a voltage regulator whose output voltage depends on the control of a transistor contained in the voltage regulator.

A voltage regulator of this type is shown in FIG.

The arrangement shown in FIG. 5 contains a DC voltage regulator and a load resistor Zout connected thereto.

The voltage regulator includes a differential amplifier (a differential transconductance amplifier) OTA1, an NMOS transistor MN1, a first resistor Rfb, a second resistor Re, a third resistor Rs, a first capacitor Cs1, a second capacitor Cs2, and a third capacitor Cs3.

The voltage regulator generates an output voltage Vout, which is tapped at the source terminal of the transistor MN1, and which is supplied to the load Zout as a supply voltage. The drain terminal of the transistor MN1 is supplied with a power voltage supplying the voltage regulator, and the gate terminal is connected to the output terminal of the transconductance amplifier OTA1. The transconductance amplifier OTA1 has two input terminals from which one input voltage Vin is supplied and from which the other is supplied with a voltage (feedback) dependent on the output voltage Vout; the transconductance amplifier OTA1 forms the difference between these voltages and outputs the result to the gate of the transistor MN1. The feedback voltage is applied to one between the resistors Rfb and Re lying node x2 tapped; the resistors Rfb and Re are connected in series and arranged between the source of the transistor MN1 and ground.

FIG. 6 shows the small-signal equivalent circuit of the arrangement shown in FIG.

The voltage regulator described is a series regulator (Series Voltage Regulator) with an NMOS transistor in drain basic circuit as a driver stage. It will be understood and need not be further explained that the voltage regulator shown is capable of producing a constant output voltage Vout dependent solely on Vin and the feedback factor (determined by resistors Rfb and Re). However, this is especially true for complex loads Zout, i. In the case of loads with inductive and / or capacitive components, this is not guaranteed under all circumstances: the system may become unstable in this case.

The stability problems would not occur if it were ensured by a suitable dimensioning of Rfb and Re that the current Is1 flowing through the transistor MN1 does not fall below a certain minimum value even with a large Zout, ie low load current, the transistor MN1 thus has a certain value Minimum slope (a certain minimum output conductance). The provision of a large (transverse) current flowing through the transistor MN1 and the resistors Rfb and Re, however, is associated with various disadvantages. In particular, such a voltage regulator has a high intrinsic energy requirement and the transistor MN1 must be made larger than would be the case with a small cross-current. In addition, the necessary minimum cross-flow to ensure the stability is not available for driving the load Zout available.

The dependence of the stability of the voltage regulator on the minimum cross-flow can be explained as follows: The arrangement according to FIG. 5 can be understood simply as a two-terminal system. The stability criterion here requires that the two poles are at least a factor of n≥10 apart.

The first pole fp1 is simplified according to equation 1.1. $${\mathrm{<figure-callout\; id="1"\; label="f\; p"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">f\; </figure-callout>}}_{\mathrm{p}}\cong \frac{1}{2*\mathrm{\pi }*{\mathrm{<figure-callout\; id="1"\; label="C\; m"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_{\mathrm{m}}*1/\mathrm{<figure-callout\; id="1"\; label="G\; m\; OTA"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{OTA}}{\mathrm{}1}_{}}$$

It can be seen that the first dominant pole is determined by the transconductance gm of the transconductance amplifier OTA1 as well as by the stabilization capacitance Cm1. In practice, the first pole is invariant. it is determined by the necessary bandwidth of the arrangement.

The second pole is simplified by the load capacitance Cout at the output Vout, the load impedance Zout, and the output conductance gds of the driving transistor MN1. Equation 1.2 gives the mathematical relationship to the calculation of the second pole. $${\mathrm{f}}_{\mathrm{p}2}\cong \frac{1}{2*\mathrm{\pi }*{\mathrm{C}}_{\mathrm{out}}*\left(1/\mathrm{G}\mathrm{<figure-callout\; id="1"\; label="d\; s\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">d\; </figure-callout>}{\mathrm{s}}_{\mathrm{MN}}{\mathrm{}1}_{}\Vert \mathrm{Z}\mathrm{out}\Vert \left(\mathrm{R}\mathrm{e}+\mathrm{R}\mathrm{f}\mathrm{b}\right)\right)}$$

With the above-mentioned simplified dimensioning rule, according to which afp2 ≥ 10 * fp1 should apply for a given load, the necessary minimum cross-current and thus the resistance Rmin (the sum of the resistances Re and Rfb) can be calculated.

The second pole fp2 is directly proportional to the output conductance of the driving transistor. The minimum output conductance of the transistor is directly proportional to the set minimum cross-current Iq = Is1 and thus ultimately the minimum phase margin of the device.

These relationships are, as already explained above, disadvantageous.

It has therefore long been looking for alternatives to influence the stability of voltage transformers that do not have these disadvantages.

• der Widerstand Rs1 und der Kondensator Cs1 in Reihe geschaltet und zwischen dem Ausgangsanschluß des Transkonduktanzverstärkers OTA1 und Masse angeordnet,
• der Kondensator Cs2 zwischen dem Rückkoppelzweig und Masse angeordnet, und
• der Kondensator Cs3 parallel zum Widerstand Rfb angeordnet.

One way of doing this is to provide additional elements which allow the transfer function of the system, more specifically the position of the poles and zeroes, to be used to guarantee a minimum phase margin for stabilization. In the case of the voltage regulator shown in FIG. 5, use was made of this possibility. The additional elements include resistor Rs1 and capacitors Cs1, Cs2, and Cs3. Of the mentioned elements are

• the resistor Rs1 and the capacitor Cs1 are connected in series and arranged between the output terminal of the transconductance amplifier OTA1 and ground,
• the capacitor Cs2 is arranged between the feedback branch and ground, and
• the capacitor Cs3 arranged parallel to the resistor Rfb.

By means of the mentioned elements influence on the position of the poles and zeros of the transfer function and thus also on the stability behavior of the system can be taken. However, it is difficult and expensive, and sometimes even impossible, to dimension the elements mentioned so that the voltage regulator operates stably over the entire load range.

• Thomas M. Frederiksen: "A Monolithic High-Power Series Voltage Regulator", IEEE Journal of Solid-State Circuits, Dezember 1968, Seite 380 ff.,
• Gabriel A. Rincon-Mora et al.: "A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator", IEEE Journal of Solid-State Circuits, Vol.33, No. 1., January 1998, Seiten 36 ff., und
• Gerrit W. den Besten et al.: "Embedded 5V-to-3.3V Voltage Regulator for Supplying Digital IC's in 3.3V CMOS Technology", IEEE Journal of Solid-State Circuits, Vol 33, No. 7, July 1998, Seite 956 ff.

und die darin genannten weiteren Fundstellen verwiesen.There are a variety of publications in which these and other ways to stabilize voltage regulators are described. It will be up for example

• Thomas M. Frederiksen: "A Monolithic High-Power Series Voltage Regulator", IEEE Journal of Solid-State Circuits, December 1968, page 380 et seq.,
• Gabriel A. Rincon-Mora et al .: "Low Voltage, Low Quiescent Current, Low Dropout Regulator", IEEE Journal of Solid State Circuits, Vol.33, no. 1st, January 1998, pages 36 ff., And
• Gerrit W. den Besten et al .: "Embedded 5V-to-3.3V Voltage Regulator for Supplying Digital ICs in 3.3V CMOS Technology", IEEE Journal of Solid-State Circuits, Vol. 7, July 1998, page 956 et seq.

and the other references cited therein.

Among the known possibilities for the stabilization of voltage regulators is none that can be easily designed and realized and can guarantee a stable stabilization under all circumstances with low own energy requirements.

This applies not only to the above-described Series Voltage Regulator, but also to the so-called Low Drop Output Regulators (LDO), which have as a driving transistor, a PMOS transistor in source-ground circuit.

The present invention is therefore based on the object of finding a voltage regulator which, with minimum own energy requirement, provides reliable stabilization under all circumstances and is also easy to design and implement.

This object is achieved by the claimed in claim 1 voltage regulator.

The stabilizing circuit can ensure that the current flowing through the transistor in phases, and only in phases in which this would be too small to ensure a stable operation of the voltage regulator is increased.

This eliminates the need to allow the transistor to flow permanently from a high cross-flow. The voltage regulator can be constructed so that the cross-current flowing through the transistor in phases in which it is not increased by the stabilizing circuit, is very low, whereby the current flowing through the transistor at high loads is only slightly larger than that of the Load drawn electricity.

This has the positive effect that the transistor can be dimensioned in sole dependence on the maximum load, so it must not be made larger for reasons of stability of the voltage regulator. In addition, the voltage regulator according to the invention has a lower own energy demand, because the flow of the additional cross-flow is indeed caused only in certain phases.

The stabilization circuit is also easy to design and implement and easily adaptable to the particular circumstances. It can also be used substantially unchanged in all types of voltage regulators be whose output voltage depends on the driving of a transistor.

Advantageous developments of the invention are the dependent claims, the following description and the figures removable.

Figur 1

einen Series Voltage Regulator mit einer im folgenden näher beschriebenen Stabilisierungsschaltung,

Figur 2

einen Low Drop Output Regulator mit der im folgenden näher beschriebenen Stabilisierungsschaltung,

Figur 3

die zeitlichen Verläufe ausgewählter Ströme und Spannungen in der in der Figur 1 gezeigten Anordnung,

Figur 4

einen Series Voltage Regulator mit einer modifizierten Stabilisierungsschaltung,

Figur 5

einen herkömmlichen Series-Voltage Regulator, und

Figur 6

ein vereinfachtes Kleinsignal-Ersatzschaltbild der in der Figur 5 gezeigten Anordnung.

The invention will be explained in more detail by means of embodiments with reference to the figures. Show it

FIG. 1

a series voltage regulator with a stabilization circuit described in more detail below,

FIG. 2

a low drop output regulator with the stabilization circuit described in more detail below,

FIG. 3

the time profiles of selected currents and voltages in the arrangement shown in FIG. 1,

FIG. 4

a series voltage regulator with a modified stabilization circuit,

FIG. 5

a conventional Series Voltage Regulator, and

FIG. 6

a simplified small-signal equivalent circuit diagram of the arrangement shown in Figure 5.

The voltage regulators described below are DC voltage regulators. However, it should be noted at this point that the peculiarities of the voltage regulator described below can also be used in voltage regulators for time-varying voltages.

FIG. 1 shows an arrangement which comprises a particularly stabilized voltage regulator and a load impedance Zout connected thereto.

The voltage regulator is a series-voltage regulator which, like the voltage regulator shown in FIG. 5 and initially described with reference thereto, includes a differential amplifier (a differential transconductance amplifier) OTA1, an NMOS transistor MN1, a first resistor Rfb and a second resistor Re, which are also interconnected and cooperate as in the voltage regulator shown in FIG. The voltage regulator shown in FIG. 1 furthermore contains a stabilization circuit which, however, has a completely different construction and functions as the elements Rs, Cs1, Cs2 and Cs3 of the voltage regulator according to FIG. 5 which serve for the stabilization.

The stabilization circuit consists of a second differential amplifier (a second differential transconductance amplifier) OTA2, NMOS transistors MN2, MN3, MN4, MN5, and MN6, and a PMOS transistor MP3.

Transistor MN2 has its drain connected to a supply voltage supplying power to the voltage regulator, the gate is connected to the output terminal of first transconductance amplifier OTA1, and the source is connected to node x3.

From the transistor MP3, the source terminal is connected to the node x3, the gate terminal is connected to the output terminal of the second transconductance amplifier OTA2, and the drain terminal is connected to the source terminal of the transistor MN4.

The transconductance amplifier OTA2 has two input terminals from which one is supplied with the voltage set at the node x3 and from which the other is supplied with the voltage Vout; the transconductance amplifier OTA2 is the difference between them Voltages and outputs them to the gate terminal of the transistor MP3.

The (lying on the ground side of the source) transistor MN4 is connected to the transistor MN5 to a current mirror, wherein a current flowing through the transistor MN4 Irep causes the transistor MN3 is traversed by a current Irep '.

The drain terminal of the transistor MN3 (which is also grounded on the source side) is connected to a node x1. Further, a reference current source outputting a current Iref and the drain terminal of the transistor MN5 are connected to this node x1.

The (on the source side grounded) transistor MN5 is connected to the transistor MN6 to a current mirror, wherein a current flowing through the transistor MN5 Ic causes the transistor MN6 is traversed by a current Ic '.

The drain terminal of the transistor MN6 (which is also grounded on the source side) is connected to the drain of the transistor MN1; This transistor MN6 represents an additional load for the transistor MN1, by which the magnitude of the current Is1 flowing through the transistor MN1 can be varied while the transistor MN1 remains at the same level.

The transistor MN1 is traversed by a current corresponding to the sum of the currents Ic ', Iq, and Iout, where Ic' is the current flowing through the transistor MN6, Iq is the current flowing through the voltage divider Rfb, Re, and Iout the load Zout is flowing through current.

The transconductance amplifier OTA2 and the transistor MP3 ensure that the same potential is set at the source terminal of the transistor MN2 (at the node x3) as on Source of the transistor MN1. This means that the potential Vout also sets at node x3. In simple terms, the arrangement of transconductance amplifier OTA2 and transistor MP3 can be understood as a voltage follower which generates a replica of the output voltage Vout at node x3. The transistors MN1 and MN2 are thus in terms of voltage in the same operating point, which serves to improve the synchronization of both transistors to each other.

Therefore, and because the transistor MN2 is driven on the gate side by the same signal as the transistor MN1, a current flowing through the transistor MN2 is in a certain proportion to the current flowing through the transistor MN1. The transistor is preferably much weaker than the transistor MN1, so that the current Irep flowing through the transistor MN2 is much smaller than the current Ic '+ Iq + Iout flowing through the transistor MN1. The transistor MN2 thus produces a replica current Irep to the transistor MN1 flowing through current Ic '+ Iq + Iout.

The current Irep flowing through the transistor MN2 also flows through the transistor MP3 and the transistor MN4. The passage of the current Irep through the transistor MN4 causes the transistor MN3 is traversed by a current Irep 'in a certain proportion to the current Irep.

When the current Irep 'is greater than or equal to the current Iref, the node x1 is pulled to ground potential, whereby the current Ic flowing from the node x1 to the source of the transistor MN5 and thus also the mirrored current Ic' become 0 and through the transistor MN1 no additional cross-flow flows. This is the case when the load impedance Zout is small enough, i. the load current Iout is big enough.

On the other hand, if the current Irep 'is smaller than the current Iref, then the difference of Irep' and of the node x1 flows Iref corresponding current Ic through the transistor MN5. The flow of the current Ic through the transistor MN5 causes the transistor MN6 is traversed by a standing in a certain proportion to the current Ic current Ic '. As a result, the transistor MN1 is traversed by an additional cross-current Ic '. This is the case when the load impedance Zout is large, ie, the load current Iout is small.

By the stabilization circuit can thus be achieved that the transistor MN1 is traversed by an additional cross-current Ic 'when the sum of the currents Iout and Iq is small, and that the transistor MN1 is traversed by any additional cross-current Ic' when the sum of Currents Iout and Iq is large, more specifically large enough to ensure stable operation of the voltage regulator.

In addition, the voltage regulator according to FIG. 1 also contains capacitors Cm1 and Cm2 via which the output terminals of the transconductance amplifiers OTA1 and OTA2 are connected to ground and which serve for frequency compensation of the transconductance amplifiers OTA1 and OTA2.

Essentially the same stabilization circuit can be used in a so-called low drop output regulator. A low drop output regulator with a stabilization circuit which corresponds to the stabilization circuit described above is shown in FIG.

• daß anstelle des NMOS-Treibertransistors MN1 in Drain-Grundschaltung ein PMOS-Treibertransistor MP1 in Source-Grundschaltung verwendet wird, und
• daß die Frequenzkompensation des ersten Transkonduktanzverstärkers OTA1 durch eine zwischen dem Ausgangsanschluß des Transkonduktanzverstärkers OTA1 und dem Ausgangsanschluß des Spannungsreglers (dem Drainanschluß des Transistors MP1) angeordnete Reihenschaltung eines Kondensators Cm1 und eines Widerstandes Rm1 erfolgt (Stichwort: Millerkompensation bzw. Polsplitting) .

The arrangement shown in FIG. 2 differs from the arrangement shown in FIG. 1 only in that

• in that, instead of the NMOS driver transistor MN1 in the drain basic circuit, a PMOS driver transistor MP1 in source basic circuit is used, and
• in that the frequency compensation of the first transconductance amplifier OTA1 is effected by a connection between the output terminal of the Transconductance amplifier OTA1 and the output terminal of the voltage regulator (the drain terminal of the transistor MP1) arranged series connection of a capacitor Cm1 and a resistor Rm1 takes place (keyword: Miller compensation or Polsplitting).

The function of the arrangements shown in FIGS. 1 and 2 and their dimensioning will be described in more detail below.

The output voltage Vout of the voltage regulator results, ignoring non-idealities: $$\mathrm{V}\mathrm{out}\cong \mathrm{Vin}*\frac{\mathrm{R}\mathrm{f}\mathrm{b}+\mathrm{R}\mathrm{e}}{\mathrm{R}\mathrm{e}}$$

When the load changes, the output voltage Vout changes. The transconductance amplifier OTA1 (also called an error amplifier) regulates the gate-source voltage of the transistor MN1 (MP1) until the voltage at the output has returned to the nominal value.

If the load current Iout is above a lower threshold Ioutmin, the current Ic 'is equal to 0, and applies to the sum of the currents at the tap point of Vout referred to below as node Vout: $$\mathrm{I}\mathrm{out}+\mathrm{I}\mathrm{q}-\mathrm{I}\mathrm{s}1=0$$

wobei W die Breite des im jeweiligen Index genannten Transistors, L die Länge des im jeweiligen Index genannten Transistors, und β die Prozesskonstante des im jeweiligen Index genannten Transistors und Transistortyps bezeichnen. Zur Vereinfachung wird davon ausgegangen, dass die Prozeßkonstante für Transistoren gleichen Typs identisch sind und somit, wenn nicht erforderlich, nachfolgend nicht genannt werden.The current flowing through the transistor MN2 is given neglecting non-idealities (mismatch etc.) as: $$\mathrm{I}\mathrm{rep}\cong \frac{\mathrm{\beta }{\mathrm{n}}_{\mathrm{MN}2}*{\mathrm{W}}_{\mathrm{MN}2}*{\mathrm{<figure-callout\; id="1"\; label="L\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">L\; </figure-callout>}}_{\mathrm{MN}}}{\mathrm{\beta }{\mathrm{n}}_{\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">MN</figure-callout>}1}*{\mathrm{<figure-callout\; id="1"\; label="W\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">W\; </figure-callout>}}_{\mathrm{MN}}*{\mathrm{L}}_{\mathrm{MN}2}}*\mathrm{I}\mathrm{s}1$$

where W denotes the width of the transistor mentioned in the respective index, L the length of the transistor named in the respective index, and β the process constant of the transistor and transistor type named in the respective index. For the sake of simplicity, it is assumed that the process constants are identical for transistors of the same type and thus, if not required, are not mentioned below.

The current Is1 is minimal when Iout and Ic 'are equal to 0 and equal $$\begin{gathered} \mathrm{I}\mathrm{s}{1}_{\min }=\frac{\mathrm{V}\mathrm{out}}{\mathrm{R}\mathrm{f}\mathrm{b}+\mathrm{R}\mathrm{e}} \\ =\mathrm{Vin}*\frac{\left(\mathrm{R}\mathrm{f}\mathrm{b}+\mathrm{R}\mathrm{e}\right)}{\mathrm{R}\mathrm{e}}*\frac{1}{\left(\mathrm{R}\mathrm{f}\mathrm{b}+\mathrm{R}\mathrm{e}\right)} \\ =\frac{\mathrm{V}\mathrm{in}}{\mathrm{R}\mathrm{e}} \end{gathered}$$

Ferner gilt $$\mathrm{I}\mathrm{ref}-\mathrm{I}\mathrm{c}-\mathrm{I}\mathrm{re}{\mathrm{p}}^{\prime }=0$$

$$\mathrm{I}\mathrm{re}{\mathrm{p}}^{\prime }\cong \frac{{\mathrm{W}}_{\mathrm{MN}3}*{\mathrm{L}}_{\mathrm{MN}4}}{{\mathrm{W}}_{\mathrm{MN}4}*{\mathrm{L}}_{\mathrm{MN}3}}*\mathrm{I}\mathrm{rep}$$

$$\mathrm{I}{\mathrm{c}}^{\prime }\cong \frac{{\mathrm{W}}_{\mathrm{MN}6}*{\mathrm{L}}_{\mathrm{MN}5}}{{\mathrm{W}}_{\mathrm{MN}5}*{\mathrm{L}}_{\mathrm{MN}6}}*\mathrm{I}\mathrm{c}$$

Is1 = Islmin adjusting current Irep (see equations 1.5 and 1.6) $$\mathrm{I}{\mathrm{rep}}_{\min }=\frac{{\mathrm{W}}_{\mathrm{MN}2}*{\mathrm{L}}_{\mathrm{MN}1}}{{\mathrm{<figure-callout\; id="1"\; label="W\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">W\; </figure-callout>}}_{\mathrm{MN}}*{\mathrm{L}}_{\mathrm{MN}2}}*\frac{\mathrm{V}\mathrm{in}}{\mathrm{R}\mathrm{e}}$$

Furthermore, applies $$\mathrm{I}\mathrm{ref}-\mathrm{I}\mathrm{c}-\mathrm{I}\mathrm{re}{\mathrm{p}}^{\text{'}}=0$$

$$\mathrm{I}\mathrm{re}{\mathrm{p}}^{\text{'}}\cong \frac{{\mathrm{W}}_{\mathrm{MN}3}*{\mathrm{L}}_{\mathrm{MN}4}}{{\mathrm{W}}_{\mathrm{MN}4}*{\mathrm{L}}_{\mathrm{MN}3}}*\mathrm{I}\mathrm{rep}$$

$$\mathrm{I}{\mathrm{c}}^{\text{'}}\cong \frac{{\mathrm{W}}_{\mathrm{MN}6}*{\mathrm{L}}_{\mathrm{MN}5}}{{\mathrm{W}}_{\mathrm{MN}5}*{\mathrm{L}}_{\mathrm{MN}6}}*\mathrm{I}\mathrm{c}$$

If the load current Iout decreases starting from a maximum value, then the current Is1 in the transistor MN1 (MP1) decreases and thus also the current in transistor MN2. When the current Irep 'becomes smaller than Iref, the potential at the node x1 increases. If the voltage V (x1) which is established at the node x1 becomes greater than Vthn (threshold voltage of the transistor MN5), a current Ic flows through the transistor MN5 and a current Ic 'through the transistor MN6. At this moment, the current in node Vout is composed as follows. $$\mathrm{I}\mathrm{out}+\mathrm{I}\mathrm{q}+\mathrm{I}{\mathrm{c}}^{\text{'}}-\mathrm{I}\mathrm{s}1=0$$

$$\mathrm{I}{\mathrm{c}}^{\prime }\cong \left(\mathrm{I}\mathrm{ref}-\left[\left(\frac{{\mathrm{W}}_{\mathrm{MN}2}\ast {\mathrm{L}}_{\mathrm{MN}1}}{{\mathrm{W}}_{\mathrm{MN}1}\ast {\mathrm{L}}_{\mathrm{MN}2}}\right)\ast \left(\mathrm{I}\mathrm{out}+\frac{\mathrm{V}\mathrm{in}}{\mathrm{R}\mathrm{e}}\right)\right]\ast \frac{{\mathrm{W}}_{\mathrm{MN}3}\ast {\mathrm{L}}_{\mathrm{MN}4}}{{\mathrm{W}}_{\mathrm{MN}4}\ast {\mathrm{L}}_{\mathrm{MN}3}}\right)\ast \frac{{\mathrm{W}}_{\mathrm{MN}6}\ast {\mathrm{L}}_{\mathrm{MN}5}}{{\mathrm{W}}_{\mathrm{MN}5}\ast {\mathrm{L}}_{\mathrm{MN}6}}$$

From the equations 1.3 to 1.11 results $$\mathrm{I}\mathrm{re}{\mathrm{p}}^{\text{'}}\cong \left[\left(\frac{{\mathrm{W}}_{\mathrm{MN}2}*{\mathrm{L}}_{\mathrm{MN}1}}{{\mathrm{<figure-callout\; id="1"\; label="W\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">W\; </figure-callout>}}_{\mathrm{MN}}*{\mathrm{L}}_{\mathrm{MN}2}}\right)*\left(\mathrm{I}\mathrm{out}+\frac{\mathrm{V}\mathrm{in}}{\mathrm{R}\mathrm{e}}\right)\right]*\frac{{\mathrm{W}}_{\mathrm{MN}3}*{\mathrm{L}}_{\mathrm{MN}4}}{{\mathrm{W}}_{\mathrm{MN}4}*{\mathrm{L}}_{\mathrm{MN}3}}$$

$$\mathrm{I}{\mathrm{c}}^{\text{'}}\cong \left(\mathrm{I}\mathrm{ref}-\left[\left(\frac{{\mathrm{W}}_{\mathrm{MN}2}*{\mathrm{L}}_{\mathrm{MN}1}}{{\mathrm{<figure-callout\; id="1"\; label="W\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">W\; </figure-callout>}}_{\mathrm{MN}}*{\mathrm{L}}_{\mathrm{MN}2}}\right)*\left(\mathrm{I}\mathrm{out}+\frac{\mathrm{V}\mathrm{in}}{\mathrm{R}\mathrm{e}}\right)\right]*\frac{{\mathrm{W}}_{\mathrm{MN}3}*{\mathrm{L}}_{\mathrm{MN}4}}{{\mathrm{W}}_{\mathrm{MN}4}*{\mathrm{L}}_{\mathrm{MN}3}}\right)*\frac{{\mathrm{W}}_{\mathrm{MN}6}*{\mathrm{L}}_{\mathrm{MN}5}}{{\mathrm{W}}_{\mathrm{MN}5}*{\mathrm{L}}_{\mathrm{MN}6}}$$

$$\mathrm{für\hspace{1em}\hspace{0.17em}}\mathrm{I}\mathrm{out}>\mathrm{I}\mathrm{ref}*\frac{{\mathrm{W}}_{\mathrm{MN}1}\ast {\mathrm{L}}_{\mathrm{MN}2}}{{\mathrm{W}}_{\mathrm{MN}2}\ast {\mathrm{L}}_{\mathrm{MN}1}}\ast \frac{{\mathrm{W}}_{\mathrm{MN}4}\ast {\mathrm{L}}_{\mathrm{MN}3}}{{\mathrm{W}}_{\mathrm{MN}3}\ast {\mathrm{L}}_{\mathrm{MN}4}}-\mathrm{I}\mathrm{q}\Rightarrow \mathrm{I}{\mathrm{c}}^{\prime }=0$$

This results in the conditions for the current Ic ': $$\mathrm{For}\mathrm{I}\mathrm{out}<\mathrm{I}\mathrm{ref}*\frac{{\mathrm{<figure-callout\; id="1"\; label="W\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">W\; </figure-callout>}}_{\mathrm{MN}}*{\mathrm{L}}_{\mathrm{MN}2}}{{\mathrm{W}}_{\mathrm{MN}2}*{\mathrm{<figure-callout\; id="1"\; label="L\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">L\; </figure-callout>}}_{\mathrm{MN}}}*\frac{{\mathrm{W}}_{\mathrm{MN}4}*{\mathrm{L}}_{\mathrm{MN}3}}{{\mathrm{W}}_{\mathrm{MN}3}*{\mathrm{L}}_{\mathrm{MN}4}}-\mathrm{I}\mathrm{q}\Rightarrow \mathrm{I}{\mathrm{c}}^{\text{'}}>0$$

$$\mathrm{For}\mathrm{I}\mathrm{out}>\mathrm{I}\mathrm{ref}*\frac{{\mathrm{<figure-callout\; id="1"\; label="W\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">W\; </figure-callout>}}_{\mathrm{MN}}*{\mathrm{L}}_{\mathrm{MN}2}}{{\mathrm{W}}_{\mathrm{MN}2}*{\mathrm{<figure-callout\; id="1"\; label="L\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">L\; </figure-callout>}}_{\mathrm{MN}}}*\frac{{\mathrm{W}}_{\mathrm{MN}4}*{\mathrm{L}}_{\mathrm{MN}3}}{{\mathrm{W}}_{\mathrm{MN}3}*{\mathrm{L}}_{\mathrm{MN}4}}-\mathrm{I}\mathrm{q}\Rightarrow \mathrm{I}{\mathrm{c}}^{\text{'}}=0$$

With the equation 1.14a and 1.14b, the circuit can now be dimensioned in consideration of the stability of the transistor MN1 (MP1) necessary for stability.

First, it will be described how the necessary current Ic 'can be determined from the requirement for stability and thus a minimum phase reserve. It is assumed that the transconductance amplifier OTA1 has a simplified transfer function with a dominant pole. Parasitic poles and zeros are ignored.

und deren Polfrequenz beträgt $${\mathrm{f}}_{\mathrm{p}1}=\frac{1}{2*\mathrm{\pi }*{\mathrm{C}}_{\mathrm{m}1}*1/\mathrm{g}{\mathrm{m}}_{\mathrm{OTA}1}}$$

wobei gm_OTA1 die Steilheit des Transkonduktanzverstärkers OTA1 bezeichnet.The Laplace transfer function in the frequency domain of the transconductance amplifier is then $${\mathrm{A}}_{\mathrm{OTA}1}\left(\mathrm{s}\right)\cong \frac{1}{1+\mathrm{s}*{\mathrm{<figure-callout\; id="1"\; label="C\; m"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_{\mathrm{m}}*1/\mathrm{<figure-callout\; id="1"\; label="G\; m\; OTA"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{OTA}}{\mathrm{}1}_{}}$$

and whose pole frequency is $${\mathrm{<figure-callout\; id="1"\; label="f\; p"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">f\; </figure-callout>}}_{\mathrm{p}}=\frac{1}{2*\mathrm{\pi }*{\mathrm{<figure-callout\; id="1"\; label="C\; m"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_{\mathrm{m}}*1/\mathrm{<figure-callout\; id="1"\; label="G\; m\; OTA"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{OTA}}{\mathrm{}1}_{}}$$

where gm OTA1 _denotes the transconductance of the transconductance amplifier OTA1.

$$\mathrm{C}1=\mathrm{C}\mathrm{g}{\mathrm{s}}_{\mathrm{MP}1}+\mathrm{C}\mathrm{g}{\mathrm{d}}_{\mathrm{MP}1}*\left(1+\left|\mathrm{A}\mathrm{v}{11}_{\mathrm{MP}1}\right|\right)$$

$$\mathrm{R}2=\frac{1}{\mathrm{g}\mathrm{d}{\mathrm{s}}_{\mathrm{MP}1}}\Vert \mathrm{R}\mathrm{out}\Vert \mathrm{R}\min ;\mathrm{\hspace{0.17em}}\mathrm{R}\min =\frac{\mathrm{V}\mathrm{in}}{\mathrm{I}{\mathrm{s}}_{\min }}$$

$$\mathrm{C}2=\mathrm{C}1+\mathrm{C}\mathrm{g}{\mathrm{d}}_{\mathrm{MP}1}*\left(1+\left|\mathrm{A}\mathrm{v}{11}_{\mathrm{MP}1}\right|\right)$$

$$\mathrm{A}\mathrm{v}11=\mathrm{g}{\mathrm{m}}_{\mathrm{MP}1}*\left(\frac{1}{\mathrm{g}\mathrm{d}{\mathrm{s}}_{\mathrm{MP}1}}\Vert \mathrm{R}\min \right)$$

wobei

• R1 den Ausgangswiderstand des Transkonduktanzverstärkers OTA1,
• gdsp den Ausgangsleitwert eines P-Kanal MOS-Transistors,
• gdsn den Ausgangsleitwert eines N-Kanal MOS-Transistors,
• C1 die Summe der Lastkapazitäten am Knoten X4 (Ausgang OTA1),
• Cgs_MP1 die Gate-Source-Kapazität des Transistors MP1,
• Cgd_MP1 die Gate-Drain-Kapazität des Transistors MP1,
• Av11 die Gleichspannungsverstärkung der Ausgangsstufe (z.B. Transistor MP1),
• R2 den Ausgangswiderstand der Treiberanordnung,
• gds_MP1 den Ausgangsleitwert des Transistors MP1,
• Rout den rein resistiven Lastwiderstand am Knoten Vout,
• Rmin die minimalste Summenresitivität aus Rfb und Re als Hilfsgröße zur Dimensionierung,
• C2 die transformierte Lastkapazität zur Berechnung des zweiten Pols fp2', und
• gm_MP1 die Steilheit des Ausgangstransistors MP1

bezeichnen.For the further considerations, the frequency response compensation circuit consisting of Cm1 and Rm1 is neglected for the time being. For the transconductance amplifier OTA1 and the output stage, the following definitions can be made: $$\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">R</figure-callout>}1=\frac{1}{\mathrm{G}\mathrm{d}\mathrm{s}\mathrm{p}}+\frac{1}{\mathrm{G}\mathrm{d}\mathrm{s}\mathrm{<figure-callout\; id="1"\; label="n\; C"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">n\; </figure-callout>}}$$

$$\mathrm{C}$$$$\mathrm{}1=\mathrm{C}\mathrm{G}{\mathrm{s}}_{\mathrm{<figure-callout\; id="1"\; label="MP"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">MP</figure-callout>}1}+\mathrm{C}\mathrm{<figure-callout\; id="1"\; label="G\; d\; MP"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{d}}_{\mathrm{MP}}{\mathrm{}1}_{}*\left(1+\left|\mathrm{A}\mathrm{v}{11}_{\mathrm{<figure-callout\; id="1"\; label="MP"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">MP</figure-callout>}1}\right|\right)$$

$$\mathrm{R}2=\frac{1}{\mathrm{G}\mathrm{d}{\mathrm{s}}_{\mathrm{<figure-callout\; id="1"\; label="MP"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">MP</figure-callout>}1}}\Vert \mathrm{R}\mathrm{out}\Vert \mathrm{R}\min ;\mathrm{}\mathrm{R}\min =\frac{\mathrm{V}\mathrm{in}}{\mathrm{I}{\mathrm{s}}_{\min }}$$

$$\mathrm{C}2=\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C</figure-callout>}1+\mathrm{C}\mathrm{<figure-callout\; id="1"\; label="G\; d\; MP"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{d}}_{\mathrm{MP}}{\mathrm{}1}_{}*\left(1+\left|\mathrm{A}\mathrm{v}{11}_{\mathrm{<figure-callout\; id="1"\; label="MP"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">MP</figure-callout>}1}\right|\right)$$

$$\mathrm{A}\mathrm{v}11=\mathrm{<figure-callout\; id="1"\; label="G\; m\; MP"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{MP}}{\mathrm{}1}_{}*\left(\frac{1}{\mathrm{G}\mathrm{d}{\mathrm{s}}_{\mathrm{<figure-callout\; id="1"\; label="MP"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">MP</figure-callout>}1}}\Vert \mathrm{R}\min \right)$$

in which

• R1 the output resistance of the transconductance amplifier OTA1,
• gdsp the output conductance of a p-channel MOS transistor,
• gdsn the output conductance of an N-channel MOS transistor,
• C1 is the sum of the load capacities at node X4 (output OTA1),
• Cgs _MP1, the gate-source capacitance of the transistor MP1,
• Cgd _MP1 the gate-drain capacitance of the transistor MP1,
• Av11 the DC gain of the output stage (eg transistor MP1),
• R2 the output resistance of the driver arrangement,
• gds _MP1 the output conductance of the transistor MP1,
• Rout the purely resistive load resistor at node Vout,
• Rmin the minimum sum resistivity of Rfb and Re as an auxiliary size for sizing,
• C2 the transformed load capacitance for the calculation of the second pole fp2 ', and
• gm _MP1, the transconductance of the output transistor MP1

describe.

$$\mathrm{f}\mathrm{p}{2}^{\prime }=\frac{1}{2\mathrm{*}\mathrm{\pi }\mathrm{*}\mathrm{R}2*\mathrm{C}2}$$

For series shunt feedback configuration, such as the voltage regulator shown in FIGS. 1 and 2, two poles may be omitted, ignoring the frequency response compensation: $$\mathrm{f}\mathrm{p}{1}^{\text{'}}=\frac{1}{2*\mathrm{\pi }\mathrm{*}\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">R</figure-callout>}1*\mathrm{C}1}$$

$$\mathrm{f}\mathrm{p}{2}^{\text{'}}=\frac{1}{2\mathrm{*}\mathrm{\pi }\mathrm{*}\mathrm{R}2*\mathrm{C}2}$$

From the general stability theory it is known that in order to guarantee a sufficiently large phase reserve, fp2 'must be >> fp1'. If now the load current Iout approaches 0 (Rl approaches infinity), the pole fp2 'moves to the pole fp1'. The phase reserve decreases, the system becomes unstable.

$$\mathrm{f}\mathrm{c}2=\frac{1}{2\mathrm{*}\mathrm{\pi }\mathrm{*}\mathrm{R}2*\left(\mathrm{C}1+\mathrm{C}\mathrm{m}1+\mathrm{C}\mathrm{g}{\mathrm{s}}_{\mathrm{MP}1}\right)}$$

Taking into account the frequency response compensation, the poles are as follows: $$\mathrm{<figure-callout\; id="1"\; label="f\; c"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">f\; </figure-callout>}\mathrm{c}\mathrm{}1=\frac{1}{2*\mathrm{\pi }*\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">R</figure-callout>}1*\left[\mathrm{C}\mathrm{G}{\mathrm{s}}_{\mathrm{<figure-callout\; id="1"\; label="MP"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">MP</figure-callout>}1}+\left(\mathrm{C}\mathrm{<figure-callout\; id="1"\; label="G\; d\; MP"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{d}}_{\mathrm{MP}}{\mathrm{}1}_{}+{\mathrm{C}}_{\mathrm{m}1}\right)\mathrm{*}\left[1+\left|\mathrm{A}\mathrm{v}11\right|\right]\right]}$$

$$\mathrm{f}\mathrm{c}2=\frac{1}{2\mathrm{*}\mathrm{\pi }\mathrm{*}\mathrm{R}2*\left(\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C</figure-callout>}1+\mathrm{<figure-callout\; id="1"\; label="C\; m"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C\; </figure-callout>}\mathrm{m}\mathrm{}1+\mathrm{C}\mathrm{G}{\mathrm{s}}_{\mathrm{MP}1}\right)}$$

From the equations 1.22 and 1.23 one can now represent the total transfer function in the frequency plane as a second-order system. $$\mathrm{A}\mathrm{v}\mathrm{dead}\left(\mathrm{s}\right)=\frac{\mathrm{V}\mathrm{out}\left(\mathrm{s}\right)}{\mathrm{V}\mathrm{in}\left(\mathrm{s}\right)}=\frac{\mathrm{<figure-callout\; id="1"\; label="G\; m\; OTA"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{OTA}}{\mathrm{}1}_{}*\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">R</figure-callout>}1*\mathrm{A}\mathrm{v}11}{\left(1+\mathrm{s}\mathrm{*}\mathrm{f}/\mathrm{f}\mathrm{c}1\right)\mathrm{*}\left(1+\mathrm{s}*\mathrm{f}/\mathrm{f}\mathrm{c}2\right)}$$

$$\mathrm{f}\mathrm{u}=\mathrm{f}\mathrm{c}1\mathrm{*}\mathrm{g}{\mathrm{m}}_{\mathrm{OTA}1}*\mathrm{R}1*\mathrm{A}\mathrm{v}11$$

Assuming that f1c << f2c, and considering that at a frequency of fu the amount of gain | Avtot (s) | = 1 yields: $$\left|\mathrm{A}\mathrm{v}\mathrm{dead}\left(\mathrm{s}\right)\right|=\frac{\mathrm{<figure-callout\; id="1"\; label="G\; m\; OTA"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{OTA}}{\mathrm{}1}_{}*\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">R</figure-callout>}1*\mathrm{A}\mathrm{v}11}{\sqrt{1+{\left(\mathrm{f}/\mathrm{f}\mathrm{c}1\right)}^2}}=1$$

$$\mathrm{f}\mathrm{u}=\mathrm{<figure-callout\; id="1"\; label="f\; c"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">f\; </figure-callout>}\mathrm{c}\mathrm{}1\mathrm{*}\mathrm{<figure-callout\; id="1"\; label="G\; m\; OTA"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{OTA}}{\mathrm{}1}_{}*\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">R</figure-callout>}1*\mathrm{A}\mathrm{v}11$$

Assuming that the load capacitance, the maximum load current, and the minimum load current are known, one can now calculate either the compensation capacitance Cm1 and / or the minimum cross current Is1 in the transistor MP1 / MN1. To guarantee stability, the following should apply: $$\mathrm{f}\mathrm{c}2>10\mathrm{*}\mathrm{f}\mathrm{u}\Rightarrow \mathrm{f}\mathrm{c}2>10*\mathrm{<figure-callout\; id="1"\; label="f\; c"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">f\; </figure-callout>}\mathrm{c}\mathrm{}1\mathrm{*}\mathrm{<figure-callout\; id="1"\; label="G\; m\; OTA"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{OTA}}{\mathrm{}1}_{}*\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">R</figure-callout>}1*\mathrm{A}\mathrm{v}11$$

Thus, taking into account Equation 1.25, Rmin and Cm1 have the following relationships: $$\mathrm{R}\min =\frac{\mathrm{V}\mathrm{in}}{\mathrm{I}\mathrm{q}+\mathrm{I}{\mathrm{c}}^{\text{'}}}=1/\left[2\mathrm{\pi }*10\mathrm{<figure-callout\; id="1"\; label="f\; c"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">f\; </figure-callout>}\mathrm{c}\mathrm{}1\mathrm{*}\mathrm{<figure-callout\; id="1"\; label="G\; m\; OTA"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{OTA}}{\mathrm{}1}_{}*\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">R</figure-callout>}1*\mathrm{A}\mathrm{v}11\mathrm{*}\left(\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C</figure-callout>}1+\mathrm{<figure-callout\; id="1"\; label="C\; m"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C\; </figure-callout>}\mathrm{m}\mathrm{}1+\mathrm{C}\mathrm{G}{\mathrm{d}}_{\mathrm{MP}1}\right)-\mathrm{G}\mathrm{d}{\mathrm{s}}_{\mathrm{MP}1}-\frac{1}{\mathrm{R}\mathrm{out}}\right]$$

With the equations 1.29, 1.14 and 1.15, the circuit can now be dimensioned accordingly. For the transconductance gm _{OTA1 of} the OTA1, a structure and a value must be defined at the beginning of the dimensioning. This can be done from a specification for the bandwidth of the OTA according to equation 1.16. For the gain of the driving transistor one can make the assumption that the minimum current Iq flows as Is1. Thus, the circuit gets according reserve in the stability.

$$\mathrm{R}{2}^{\prime }=\frac{1}{\mathrm{g}{\mathrm{m}}_{\mathrm{MN}1}+\mathrm{g}\mathrm{m}{\mathrm{b}}_{\mathrm{MN}1}+\mathrm{g}\mathrm{d}{\mathrm{s}}_{\mathrm{MN}1}}\Vert \mathrm{R}\mathrm{out}\Vert \mathrm{R}\min$$

$$\mathrm{C}{2}^{\prime }=\mathrm{C}1+\mathrm{C}\mathrm{d}\mathrm{b}1$$

$$\mathrm{C}{1}^{\prime }=\mathrm{C}\mathrm{g}\mathrm{s}1+\mathrm{C}\mathrm{g}\mathrm{d}1*\left(1+\left|\frac{\mathrm{g}{\mathrm{m}}_{\mathrm{MN}1}*\mathrm{R}\mathrm{out}}{\mathrm{g}{\mathrm{m}}_{\mathrm{MN}1}*\mathrm{R}\mathrm{out}+1}\right|\right)$$

$$\mathrm{f}\mathrm{c}{1}^{\prime }=\frac{1}{2\mathrm{*}\mathrm{\pi }\mathrm{*}\mathrm{R}1\mathrm{*}\left[\mathrm{C}\mathrm{g}{\mathrm{s}}_{\mathrm{MN}1}+\left(\mathrm{C}\mathrm{g}{\mathrm{d}}_{\mathrm{MN}1}+\mathrm{C}\mathrm{m}1\right)\mathrm{*}\left[1+\left|\mathrm{A}\mathrm{v}12\right|\right]\right]}$$

As can be seen from the above equations, these have been made in part for the Low Drop Output Voltage Regulator shown in FIG. The relationships deduced therefrom may be transferred to the Series Voltage Regulator shown in FIG. 1 taking into account the following formulas. $$\mathrm{A}\mathrm{v}12=\frac{\mathrm{<figure-callout\; id="1"\; label="G\; m\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{MN}}{\mathrm{}1}_{}*\mathrm{R}\mathrm{out}}{\mathrm{<figure-callout\; id="1"\; label="G\; m\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{MN}}{\mathrm{}1}_{}*\mathrm{R}\mathrm{out}+1}$$

$$\mathrm{R}{2}^{\text{'}}=\frac{1}{\mathrm{<figure-callout\; id="1"\; label="G\; m\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{MN}}{\mathrm{}1}_{}+\mathrm{G}\mathrm{m}{\mathrm{<figure-callout\; id="1"\; label="b\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">b\; </figure-callout>}}_{\mathrm{MN}}+\mathrm{G}\mathrm{d}{\mathrm{s}}_{\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">MN</figure-callout>}1}}\Vert \mathrm{R}\mathrm{out}\Vert \mathrm{R}\min$$

$$\mathrm{C}{2}^{\text{'}}=\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C</figure-callout>}1+\mathrm{C}\mathrm{d}\mathrm{b}1$$

$$\mathrm{C}{1}^{\text{'}}=\mathrm{C}\mathrm{G}\mathrm{s}1+\mathrm{<figure-callout\; id="1"\; label="C\; G\; d"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C\; </figure-callout>}\mathrm{G}\mathrm{d}\mathrm{}1*\left(1+\left|\frac{\mathrm{<figure-callout\; id="1"\; label="G\; m\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{MN}}{\mathrm{}1}_{}*\mathrm{R}\mathrm{out}}{\mathrm{<figure-callout\; id="1"\; label="G\; m\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{MN}}{\mathrm{}1}_{}*\mathrm{R}\mathrm{out}+1}\right|\right)$$

$$\mathrm{f}\mathrm{c}{1}^{\text{'}}=\frac{1}{2\mathrm{*}\mathrm{\pi }\mathrm{*}\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">R</figure-callout>}1\mathrm{*}\left[\mathrm{C}\mathrm{G}{\mathrm{s}}_{\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">MN</figure-callout>}1}+\left(\mathrm{C}\mathrm{<figure-callout\; id="1"\; label="G\; d\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{d}}_{\mathrm{MN}}{\mathrm{}1}_{}+\mathrm{C}\mathrm{m}1\right)\mathrm{*}\left[1+\left|\mathrm{A}\mathrm{v}12\right|\right]\right]}$$

Under the same assumptions as for the LDO configuration, the series-voltage regulator has an Rmin ': $$\begin{array}{ll}\mathrm{R}\mathrm{Wed.}{\mathrm{n}}^{\text{'}}& =\frac{\mathrm{V}\mathrm{in}}{\mathrm{I}\mathrm{q}+\mathrm{I}{\mathrm{c}}^{\text{'}}}\\ \mathrm{}& =1/\left[2\mathrm{\pi }*10\mathrm{f}\mathrm{c}{1}^{\text{'}}*\mathrm{<figure-callout\; id="1"\; label="G\; m\; OTA"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{OTA}}{\mathrm{}1}_{}*\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">R</figure-callout>}1*\mathrm{A}\mathrm{v}12*\left(\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C</figure-callout>}1+\mathrm{<figure-callout\; id="1"\; label="C\; m"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">C\; </figure-callout>}\mathrm{m}\mathrm{}1+\mathrm{C}\mathrm{G}{\mathrm{s}}_{\mathrm{MN}1}\right)-\mathrm{<figure-callout\; id="1"\; label="G\; m\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">G\; </figure-callout>}{\mathrm{m}}_{\mathrm{MN}}{\mathrm{}1}_{}+\mathrm{G}\mathrm{m}{\mathrm{<figure-callout\; id="1"\; label="b\; MN"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">b\; </figure-callout>}}_{\mathrm{MN}}+\mathrm{G}\mathrm{d}{\mathrm{s}}_{\mathrm{MN}1}-\frac{1}{\mathrm{R}\mathrm{out}}\right]\end{array}$$

With Equations 1.35 and 1.29, for the arrangements shown in Figures 1 and 2, the minimum cross current which must flow through the output transistors MN1 and MP1, respectively, can now be determined to provide stability for a given load capacitance. Here again it should be noted that the resistor Rmin (Rmin ') serves as an auxiliary size for sizing. The current through an assumed resistance Rmin (Rmin ') can now be divided between the current Iq by voltage divider Rfb and Re and the current Ic' accordingly. The circuit is thus completely dimensioned.

$$\mathrm{G}\mathrm{a}{\mathrm{v}}_{\mathrm{d}\mathrm{c}}\cong 20\mathrm{*}\log \left(\frac{\mathrm{R}\mathrm{e}+\mathrm{R}\mathrm{f}}{\mathrm{R}\mathrm{e}}\right)$$

In order to check the mathematical results, the transfer function in the frequency level of the closed loop can be derived from the small signal equivalent circuit shown in FIG. $$\mathrm{G}\mathrm{a}{\mathrm{v}}_{\mathrm{a}\mathrm{c}}\left(\mathrm{s}\right)=20\mathrm{*}\log \left(\frac{\frac{\mathrm{Z}\mathrm{in}\left(\mathrm{s}\right)}{\mathrm{Z}\mathrm{in}\left(\mathrm{s}\right)+\mathrm{R}\mathrm{e}\Vert \mathrm{R}\mathrm{f}\mathrm{b}}\mathrm{*}\mathrm{A}\mathrm{v}\mathrm{dead}\left(\mathrm{s}\right)\mathrm{*}\frac{\left(\mathrm{R}\mathrm{e}+\mathrm{R}\mathrm{f}\mathrm{b}\right)\Vert \mathrm{C}1}{\left(\mathrm{R}\mathrm{e}+\mathrm{R}\mathrm{f}\mathrm{b}\right)<figure-callout\; id="1"\; label="\Vert \; C"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">\Vert \; </figure-callout>\mathrm{C}\mathrm{}1+\mathrm{R}\mathrm{out}}}{1+\frac{\mathrm{R}\mathrm{e}}{\mathrm{R}\mathrm{e}+\mathrm{R}\mathrm{f}\mathrm{b}}\mathrm{*}\left(\frac{\mathrm{Z}\mathrm{in}\left(\mathrm{s}\right)}{\mathrm{Z}\mathrm{in}\left(\mathrm{s}\right)+\mathrm{R}\mathrm{e}\Vert \mathrm{R}\mathrm{f}\mathrm{b}}\mathrm{*}\mathrm{A}\mathrm{v}\mathrm{dead}\left(\mathrm{s}\right)\mathrm{*}\frac{\left(\mathrm{R}\mathrm{e}+\mathrm{R}\mathrm{f}\mathrm{b}\right)\Vert \mathrm{C}1}{\left(\mathrm{R}\mathrm{e}+\mathrm{R}\mathrm{f}\mathrm{b}\right)<figure-callout\; id="1"\; label="\Vert \; C"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">\Vert \; </figure-callout>\mathrm{C}\mathrm{}1+\mathrm{R}\mathrm{out}}\right)}\right)$$

$$\mathrm{G}\mathrm{a}{\mathrm{v}}_{\mathrm{d}\mathrm{c}}\cong 20\mathrm{*}\log \left(\frac{\mathrm{R}\mathrm{e}+\mathrm{R}\mathrm{f}}{\mathrm{R}\mathrm{e}}\right)$$

If the transfer function shows an increase in the frequency range to the expected DC gain, instability or at least ringing (overshoot) can be assumed.

With the above equations, the circuit can be dimensioned accordingly.

FIG. 3 shows, by way of example, current and voltage profiles in a properly dimensioned voltage regulator with a stabilization circuit of the type described above.

FIG. 4 shows a stabilization circuit in which a hysteresis is provided for switching on and off the additional cross-current Ic '.

The arrangement shown in Figure 4 largely corresponds to the arrangement shown in Figure 1; Elements denoted by the same reference numerals are identical or corresponding elements.

The stabilization circuit shown in FIG. 4 additionally contains NMOS transistors MN7 and MN8 as well as a current source supplying a reference current Iref2.

The transistors MN7 and MN8 are connected to a current mirror, wherein the drain of the transistor MN7 and the gates of the transistors MN7 and MN8 are connected to the node x1, the drain of the transistor MN8 to the drain of the transistor MN4, the gates of the transistors MN3 and MN4 and the reference current Iref2 supplying power source is connected, and the sources of the transistors MN7 and MN8 are connected to ground.

As a result of the additional measures it is achieved that the threshold, which must be exceeded by Irep, so that the additional cross-current Ic 'flows, is smaller than the threshold, which must be exceeded by Irep, so that no additional cross-current Ic' flows more.

The hysteresis is characterized by: $${\mathrm{I}}_{\mathrm{hys}}=\left(\frac{{\mathrm{W}}_{\mathrm{MN}4}\mathrm{*}{\mathrm{L}}_{\mathrm{MN}3}}{{\mathrm{W}}_{\mathrm{MN}3}\mathrm{*}{\mathrm{L}}_{\mathrm{MN}4}}-\frac{{\mathrm{W}}_{\mathrm{MN}7}\mathrm{*}{\mathrm{L}}_{\mathrm{MN}\mathrm{8th}}}{{\mathrm{W}}_{\mathrm{MN}\mathrm{8th}}\mathrm{*}{\mathrm{L}}_{\mathrm{MN}7}}\right)\mathrm{*}\mathrm{<figure-callout\; id="1"\; label="I\; ref"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">I\; </figure-callout>}\mathrm{ref}\mathrm{}1$$

The described stabilizer circuits can be modified in a variety of ways.

For example, it can be provided that the size of the additional cross-current Ic 'is set so that the current flowing through the transistor MN1 or MP1 is just large enough, ie. is not significantly greater than is necessary to ensure stable operation of the voltage regulator.

It could also be provided to make the size of the additional cross-flow Ic 'in several stages to be changeable.

Furthermore, it could be provided that the cross-flow flowing through the transistor is made large by default, and that the stabilizing circuit ensures that the cross-flow is reduced when the magnitude of the current flowing through the transistor (or a current dependent on the magnitude of this current) exceeds a certain threshold.

Regardless of this, it can be provided that the change in the current flowing through the transistor MN1 or MP1 is achieved by a reconfiguration of the arrangement, for example by opening, closing or switching of switches via which the transistor can be connected to components or current sinks acting as load elements.

The stabilization circuits of the described voltage regulators are easy to design and implement independently of the details of the practical implementation, and can ensure reliable stabilization under all circumstances with minimum self-energy consumption of the voltage regulators.

Claims (10)

1. Voltage regulator, having a transistor (MN1, MP1) and a variable load (Rfb, Re, MN6) connected in series with the transistor,

   - where the output voltage (Vout) of the voltage regulator is tapped off at a point situated between the transistor (MN1, MP1) and the load (Rfb, Re, MN6), and where the output voltage (Vout) of the voltage regulator is dependent on the actuation of the transistor (MN1, MP1), and

   - where the voltage regulator contains a stabilization circuit which produces a replica current (Irep) for the current (Is1) flowing through the transistor (MN1) and, if the generated current (Irep) has a magnitude below a particular limit value, increases the variable load (Rfb, Re, MN6) and consequently also the current (Is1) flowing through the transistor (MN1, MP1).
2. Voltage regulator according to Claim 1,
   characterized
   in that the current (Is1) flowing through the transistor (MN1, MP1) is varied by opening or closing a switch via which the transistor (MN1, MP1) is connected to a component acting as load element or to a current sink.
3. Voltage regulator according to Claim 1,
   characterized
   in that the current (Is1) flowing through the transistor (MN1, MP1) is varied by varying the actuating of a component which is arranged in a circuit path containing the transistor.
4. Voltage regulator according to Claim 3,
   characterized
   in that the current (Is1) flowing through the transistor (MN1, MP1) is varied by varying the actuation of a second transistor (MN6) connected in series with the transistor.
5. Voltage regulator according to Claim 4,
   characterized
   in that the second transistor (MN6) is connected up to a third transistor (MN5) to form a current mirror, and in that the current flowing through the second transistor is dependent on the current flowing through the third transistor.
6. Voltage regulator according to Claim 1,
   characterized
   in that the current (Irep) generated by the stabilization circuit is generated using a fourth transistor (MN2, MP2) which is actuated like the transistor (MN1, MP1).
7. Voltage regulator according to Claim 6,
   characterized
   in that the fourth transistor (MN2, MP2) has smaller dimensions than the transistor (MN1, MP1).
8. Voltage regulator according to Claim 6 or 7,
   characterized
   in that the stabilization circuit ensures that the fourth transistor (MN2, MP2) is operated at the same operating point as the transistor (MN1, MP1) .
9. Voltage regulator according to one of Claims 6 to 8,
   characterized
   in that the fourth transistor (MN2, MP2) has a fifth transistor (MN4) connected in series with it, where this fifth transistor is connected up to a sixth transistor (MN3) to form a second current mirror, where the drain connection of the sixth transistor is supplied with a reference current (Iref), and where the drain connection of the sixth transistor is connected to the drain connection of the primary transistor (MN5) of the first current mirror (MN5, MN6).
10. Voltage regulator according to one of the preceding claims,
    characterized
    in that the current (Is1) flowing through the transistor (MN1, MP1) is varied by the stabilization circuit using a hysteresis loop.

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