EP1230741A1 - Interface de communication unifilaire unidirectionnelle - Google Patents

Interface de communication unifilaire unidirectionnelle

Info

Publication number
EP1230741A1
EP1230741A1 EP00975459A EP00975459A EP1230741A1 EP 1230741 A1 EP1230741 A1 EP 1230741A1 EP 00975459 A EP00975459 A EP 00975459A EP 00975459 A EP00975459 A EP 00975459A EP 1230741 A1 EP1230741 A1 EP 1230741A1
Authority
EP
European Patent Office
Prior art keywords
data
line
processor
slave
data line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00975459A
Other languages
German (de)
English (en)
Other versions
EP1230741A4 (fr
Inventor
Daniel D. Friel
Gary V. Zanders
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
PowerSmart Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PowerSmart Inc filed Critical PowerSmart Inc
Publication of EP1230741A1 publication Critical patent/EP1230741A1/fr
Publication of EP1230741A4 publication Critical patent/EP1230741A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/16—Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to a device for the transmission of signals between two data processors. More particularly, the disclosure relates to a device for the exchange of data between a host processor and a slave processor. A connection between the two processors is provided by a single data line, and communications are conducted in one direction, from the slave processor to the host processor.
  • a simple example is a battery pack (a "slave” component) that is removably connectable to a portable electronic device (a "host” device). At the very least, the battery pack should be able to communicate with the portable electronic device to inform the camcorder of the amount of energy contained in the battery.
  • the communication architecture is designed with as few connections as possible.
  • SM system management
  • a currently popular protocol for use over the SM bus is the Inter-Integrated Circuit (I C), which was originally developed by Philips Semiconductor. The protocol utilizes a synchronous signal and has the advantage of accommodating multiple master and multiple slave components (including multiple batteries, wherein the system monitors various aspects of the condition of each battery).
  • the DQ system uses a single wire and a ground wire to connect a host device to multiple slave components. Data is transmitted in two directions on the one non-ground wire.
  • the architecture includes a pull up resistor that maintains the line in a high state, and allows data to be transmitted by pulling the line down, so that the state of the line is up or down for each transmitted bit.
  • bi-directional, one-wire bus Another drawback of the bi-directional, one-wire bus is that some use of time- domain or frequency-domain relations, to track the two half-channels of communication is required.
  • a crude time base is provided by using an unstable oscillator. This crude time base, together with electrical relationships, provides the necessary reference for two-way communication over a one- wire bus.
  • a further drawback of the bi-directional, one- wire bus is that, because of the bi-directional nature of the communications, the slave component must require the ability to sample the data line and receive messages from the host.
  • a slave component of an I 2 C system therefore, will in most cases require the architecture necessary to allow the slave to receive messages, thereby increasing the cost and complexity of the slave.
  • the new architecture/protocol will be simple and inexpensive in comparison to the above describe I 2 C and DQ systems.
  • the present disclosure provides a data communication interface for transferring at least one data bit to a host processor.
  • the interface includes a one- wire data line, and a slave processor connected to the data line and including a pulldown circuit for varying voltage on the data line.
  • the slave processor is incapable of sampling data from the data line, but is programmed to vary voltage on the data line using the pull-down circuit when the data line is energized, to signal at least one data bit.
  • the slave processor is programmed to pull the voltage low on the energized data line to signal a "0" and to raise the voltage high on the energized data line to signal a " 1 ".
  • the interface includes a host processor connected to the data line and including a pull-down circuit for varying voltage on the data line at the request of the host processor.
  • the host processor is capable of sampling data from the data line, and is programmed to energize the data line using the pull-down circuit when at least one data bit is desired from the slave processor.
  • the host processor is also programmed to sample the voltage on the energized data line to determine the value of a bit signaled by the slave processor.
  • the presently disclosed communications architecture/protocol uses a minimum amount of hardware to communicate pre- selected information from the slave to the host.
  • the communication format is simple and does not require continuous monitoring, resulting in a reduction of power consumption for both the host and the slave, which is of course important in portable electronic devices.
  • the presently disclosed one-way, single wire communication interface accordingly, is particularly attractive for hand-held or other low-power portable electronic devices, such as cell phones, personal digital assistants and camcorders, for example.
  • FIG. 1 is a simplified schematic illustrating a communications interface according to the present disclosure, including a slave component connected to a host device through a unidirectional, one-wire bus;
  • FIG. 2 shows graphs of data line voltage versus time, illustrating unidirectional communication according to the present disclosure for use with the interface of FIG. 1;
  • FIG. 3 shows a flow chart illustrating a "data initiation" algorithm according to the present disclosure for use by the host device of FIG. 1 ;
  • FIG. 4 shows a flow chart illustrating a "send data" algorithm according to the present disclosure for use by the slave component of FIG. 1 ;
  • FIG. 5 shows a flow chart illustrating a "send data" algorithm according to the present disclosure for use by the guest device of FIG. 1 ;
  • FIG. 6 is a simplified schematic illustrating a communications interface according to the present disclosure, including a unidirectional, one-wire bus connecting a slave component comprising a battery pack to a host device comprising a portable electronic product;
  • FIG. 7 is a simplified schematic illustrating a computer processing unit according to the present disclosure adapted to be connected in series with other, similar computer processing units for sequential communications with a host device; and
  • FIG. 8 is a simplified schematic illustrating a battery pack constructed in accordance with the present disclosure and including a plurality of the computer processing units of FIG. 7 connected together in series for sequentially communicating with a host device.
  • the present disclosure provides a method of signaling at least one data bit to a host processor from a slave processor over a one- wire data line.
  • the method includes providing a slave processor that is incapable of sampling data from the data line.
  • the method also includes energizing the data line using a host processor when at least one data bit is desired from the slave processor, varying the voltage on the energized data line using the slave processor, and sampling the voltage on the energized data line using the host processor to determine the value of a bit signaled by the slave processor.
  • the host processor de-energizes the data line.
  • the slave processor doesn't start varying the voltage on the energized data line to signal the data bit, until a pre-selected time period after the line is energized by the host so that the host is prepared to receive the entire data signal.
  • the host processor energizes the data line by raising the data line to a high logic level. Then, the slave processor pulls the voltage low on the energized data line to signal a "0", and raises the voltage high on the energized data line to signal a " 1 ".
  • the method of communication is preferably designed to minimize the charge transfer out of the battery in the module. Thus, the slave processor never sources current to the data line, but only sinks current.
  • a host device having a computer processing unit includes the host processor.
  • the CPU also includes a pull-down transistor controlled by the host processor for varying the voltage on the data line.
  • a slave component has a CPU including the slave processor and also including a very high-impedance pulldown resistor for varying the voltage on the data line. (A very high-impedance pulldown resistor is used in the slave component merely to avoid the risk of floating nodes.)
  • the system also includes a power line and a ground line extending between the device and the component. All of the lines are connectably split between the slave component and the host component such that the lines can be re-connected when desired, whereby the slave can be plugged into the host (e.g., like a battery pack being plugged into a cell phone).
  • FIG. 3 shows a "data initiation” algorithm according to the present disclosure for use by the host processor of FIG. 1
  • FIG. 4 shows a "send data” algorithm according to the present disclosure for use by the slave processor of FIG. 1.
  • the slave processor doesn't act until it is woken by the host processor when the host processor energizes the data line.
  • FIG. 5 shows an alternative "send data" algorithm according to the present disclosure for use by the guest device of FIG. 1.
  • the slave processor simply attempts to signal data at pre-selected intervals, even if the data line has not been energized by the host.
  • a slave component comprising a battery pack is shown that includes the slave CPU of FIG. 1.
  • the battery pack includes a battery, at least one measurement device for measuring a variable property of the battery and for producing an analog signal indicative of the measurement, and an analog to digital converter for converting the analog signal indicative of the measurement to at least one data bit.
  • the slave CPU is connected to the converter and includes memory (not shown) for receiving the at least one data bit from the converter and storing the at least one data bit until the data line is energized.
  • the at least one measurement device of the battery pack comprises means for measuring the voltage level, the current, the temperature, and the current usage.
  • the battery pack is connectable to a portable product (e.g., a cell phone) including the host CPU of FIG. 1.
  • a portable product e.g., a cell phone
  • FIG. 7 another slave CPU including a signal-in line, a data-out line, and a signal-out line.
  • the slave CPU also includes a processor including a pulldown circuit for varying voltage on the signal-out line.
  • the processor is connected to the signal-in line and the data-out line and is programmed to transfer at least one data bit over the data-out line when the voltage of the signal-in line is varied.
  • the processor is also programmed to vary the voltage on the signal-out line when completed transferring the at least one data bit over the data line.
  • the slave CPU of FIG. 7 is adapted to be connected in series with other slave components for sequential communications with a host device.
  • FIG. 8 shows a battery pack constructed in accordance with the present disclosure and including a plurality of the slave components of FIG. 7 connected together in series for sequentially communicating with a host device.
  • Each of the slave components is connected to a battery.
  • each slave component includes at least one measurement device for measuring a variable property of the battery, and an analog to digital converter for converting an analog signal produced by the measurement device into a digital signal.
  • the assembly also includes an assembly CPU having a processor, a one- wire data line for connection to a host component (not shown), an information line arranged to receive the signals from each of the data-out lines of the slave components, and a command line connected to the signal-in line of a first of the connected slave components.
  • the assembly processor is connected to the assembly data line and includes a first pull-down circuit for varying voltage on the data line to signal a host connected to the data line.
  • the processor is also connected to the command line and includes a second pull-down circuit for varying voltage on the command line.
  • the processor is further connected to the information line.
  • the processor is programmed to vary voltage on the command line using the second pull-down circuit when the data line is energized to signal the first slave CPU to report information.
  • the assembly processor is also programmed to vary voltage on the data line using the first pull-down circuit when at least one data bit from the slave components is received on the information line to signal information over the data line including identification of the slave component (i.e., first slave, second slave . . . ) and the at least one data bit of the particular slave component (i.e., information about the slave's respective battery).
  • the assembly processor pulls down the voltage on the command line to instruct the first slave CPU to signal information regarding the first battery to the assembly CPU over the information line.
  • the assembly processor then signals the battery number and information to the host over the data line utilizing the protocol of FIG. 2.
  • the second, third and fourth slaves then sequentially report their battery information to the assembly CPU, which in turn sequentially reports the battery identifier and battery information to the host.
  • the signal-out line of the last of the slave CPU's (the fourth slave in the particular embodiment) is also connected to the information line of the assembly processor.
  • the last slave When the last slave is finished reporting information to the assembly CPU, the last slave signal the assembly that the last slave has reported in through the signal-out line of the slave and the information line of the assembly CPU.
  • the assembly CPU can then signal the host that all the slaves of the assembly have reported.
  • the signal-in and the signal-out lines of the slave CPU's are preferably connected through voltage level shifters, and the data-out lines are preferably connected to the information line of the assembly CPU through optoisolators.
  • the signal-out line of the slave and the information line of the assembly CPU are connected through an optoisolator.
  • the present disclosure provides a new and improved communications architecture and protocol that includes connecting a single data wire between a host processor and a slave processor.
  • the host processor (which may be in a portable electronic component, such as a cell phone, PDA, or camcorder) contains a switch for coupling a positive voltage to the data line.
  • the slave processor (which may be contained within a battery pact for monitoring the battery) then signals data at a set rate using a predetermined protocol, but in only one direction along the data line.
  • the host processor when the host processor needs information the host energizes the data line and the slave processor is able to send information to the host.
  • the host processor can remove the voltage source from the data line, causing the data line to go low.
  • the slave may be programmed to become activated and only send data when the data line is energized, or may continuously send data regardless of the state of the data line.
  • each slave can include a storage device, such as shift register, which can be continuously updated in real time with desired information for transmittal to the host. Then, when activated by the host, the slave provides the most recently updated information to the host.
  • a storage device such as shift register
  • the slave when activated by the host, the slave provides the most recently updated information to the host.
  • a further embodiment might comprise a system for monitoring multiple batteries with periodic and staggered time delay, or a wired OR logic arrangement to determine which slave is being interrogated.
  • Various arbitration schemes, or logic arrangements can also be used to determine whether another slave is using the single data wire.

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Telephone Function (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)

Abstract

L'invention concerne une interface de communication de données destinée au transfert d'au moins un bit de données vers un processeur hôte. Cette interface comprend une ligne de données unifilaire ainsi qu'un processeur esclave connecté à cette ligne de données et comprenant un circuit d'excursion basse destiné à faire varier la tension sur cette ligne de données. Le processeur esclave est passif et incapable d'échantillonner des données à partir de la ligne de données. Ledit processeur esclave est programmé pour faire varier la tension sur la ligne de données lorsque celle-ci est mise sous tension, de façon à signaler au moins un bit de données.
EP00975459A 1999-10-28 2000-10-27 Interface de communication unifilaire unidirectionnelle Withdrawn EP1230741A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16194099P 1999-10-28 1999-10-28
US161940P 1999-10-28
PCT/US2000/029726 WO2001031801A1 (fr) 1999-10-28 2000-10-27 Interface de communication unifilaire unidirectionnelle

Publications (2)

Publication Number Publication Date
EP1230741A1 true EP1230741A1 (fr) 2002-08-14
EP1230741A4 EP1230741A4 (fr) 2006-04-26

Family

ID=22583467

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00975459A Withdrawn EP1230741A4 (fr) 1999-10-28 2000-10-27 Interface de communication unifilaire unidirectionnelle

Country Status (8)

Country Link
EP (1) EP1230741A4 (fr)
JP (1) JP2003513504A (fr)
KR (1) KR20020033794A (fr)
CN (1) CN1382326A (fr)
AU (1) AU1350901A (fr)
MX (1) MXPA02002334A (fr)
TW (1) TW531985B (fr)
WO (1) WO2001031801A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008021038A (ja) * 2006-07-11 2008-01-31 Fujitsu Ltd コモンクロック方式におけるクロック信号制御方法、及び集積回路装置
US9235545B2 (en) * 2012-08-03 2016-01-12 Microsoft Technology Licensing, Llc Single wire concurrent bi-directional communication for PSU
US20140143588A1 (en) * 2012-11-21 2014-05-22 Nokia Corporation Instant Communication Error Indication From Slave
CN102968082B (zh) * 2012-11-21 2014-10-01 成都金亚科技股份有限公司 用于单片机单线通讯的实现方法
CN106201973B (zh) * 2016-06-30 2020-08-11 珠海智融科技有限公司 一种单线串行通信接口的方法与系统
CN108872830A (zh) * 2018-06-07 2018-11-23 苏州纳芯微电子股份有限公司 一种用于传感器调理芯片的单线测试方法
TWI705335B (zh) * 2018-10-15 2020-09-21 新唐科技股份有限公司 積體電路、匯流排系統以及其控制方法
CN112003817B (zh) * 2020-06-30 2021-10-15 上海美仁半导体有限公司 一种信号转换方法、芯片以及家用电器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023778A (en) * 1990-03-23 1991-06-11 General Motors Corporation Interprocessor communication method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396639A (en) * 1991-09-16 1995-03-07 Rohm Co., Ltd. One chip microcomputer having programmable I/O terminals programmed according to data stored in nonvolatile memory
JP3406444B2 (ja) * 1995-01-10 2003-05-12 富士通株式会社 データ転送システムのバス制御装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023778A (en) * 1990-03-23 1991-06-11 General Motors Corporation Interprocessor communication method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO0131801A1 *

Also Published As

Publication number Publication date
WO2001031801A1 (fr) 2001-05-03
TW531985B (en) 2003-05-11
CN1382326A (zh) 2002-11-27
AU1350901A (en) 2001-05-08
EP1230741A4 (fr) 2006-04-26
MXPA02002334A (es) 2002-07-30
KR20020033794A (ko) 2002-05-07
JP2003513504A (ja) 2003-04-08

Similar Documents

Publication Publication Date Title
US6697897B1 (en) Data communication interface between host and slave processors
JP3450829B2 (ja) バッテリー情報を記憶および通信する方法および装置
US7478188B2 (en) System and method for connecting a WUSB device to multiple WUSB hosts
CN100456772C (zh) 电源控制电路、电子仪器、及其充电方法
KR100663598B1 (ko) 배터리를 식별하고 배터리와 전자 장치간의 인터페이스를 통해서 통신시키는 장치 및 방법
CN1640083B (zh) 附件控制接口
CN105471051A (zh) 双向电源管理技术
KR20160065206A (ko) 카메라 제어 인터페이스 슬레이브 디바이스 대 슬레이브 디바이스 통신
CN213934874U (zh) 一种基于监听技术的rs485串行总线通信设备
WO2001031801A1 (fr) Interface de communication unifilaire unidirectionnelle
CN108599530A (zh) 一种供电模式转换器以及供电模式转换方法
CN201336032Y (zh) 一种软件模拟串行数据传输装置
CN102332617B (zh) 便携式终端及识别该便携式终端的电池的方法
JP4491146B2 (ja) 電子装置におけるバッテリと通信手段への通信手段の同期方法、及び装置、及びバッテリ
CN101471463A (zh) 电子装置及其充电方法
JP2002536719A (ja) 電子デバイスと電池との間の通信を可能にする方法、電子デバイスと電池とから成る装置、及び通信を可能にする電池
CN114661646A (zh) 串口转接控制电路
US6246600B1 (en) Multi-use battery
CN101625667A (zh) 数据传输装置及其数据传输的方法
CN2678200Y (zh) 移动终端用便携式数据传输装置
WO2001031844A3 (fr) Communication de donnees bi-mode permettant de surveiller et de diagnostiquer des biens a distance
CN201821140U (zh) 一种usb设备的电源
CN118827453A (zh) 通信系统坏点检测方法、信号传输模块、菊花链通信电路、电池管理系统以及电子设备
CN211375350U (zh) 一种适用于rs485传感器的单点式数据采集模块
JPH0635573A (ja) 電源回路装置

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20020528

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: MICROCHIP TECHNOLOGY INCORPORATED

A4 Supplementary search report drawn up and despatched

Effective date: 20060315

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 13/42 20060101ALI20060309BHEP

Ipc: G06F 13/40 20060101AFI20060309BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20060615