EP1224764A1 - Correlateur numerique - Google Patents

Correlateur numerique

Info

Publication number
EP1224764A1
EP1224764A1 EP99955038A EP99955038A EP1224764A1 EP 1224764 A1 EP1224764 A1 EP 1224764A1 EP 99955038 A EP99955038 A EP 99955038A EP 99955038 A EP99955038 A EP 99955038A EP 1224764 A1 EP1224764 A1 EP 1224764A1
Authority
EP
European Patent Office
Prior art keywords
code
ssc
data
correlator
data stream
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99955038A
Other languages
German (de)
English (en)
Other versions
EP1224764A4 (fr
Inventor
Ephraim Mendelovicz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority claimed from PCT/US1999/024425 external-priority patent/WO2001030015A1/fr
Publication of EP1224764A1 publication Critical patent/EP1224764A1/fr
Publication of EP1224764A4 publication Critical patent/EP1224764A4/fr
Withdrawn legal-status Critical Current

Links

Definitions

  • This invention relates to spread spectrum communication of a plurality of messages received simultaneously, from different sources and particularly where the communications employ one of several pseudo random codes at baseband or on a carrier frequency, and. where the data communicated, can be recovered only by the identification of the particular code and its time of arriv l .
  • the signals to be correlated are spread spectrum communication signals.
  • the data, communicated is digital data, which consists of a sequence of ones and zeros.
  • the spectrum of the data is spread by modulation with a Signal Spreading Code (SSO) to form a digital spread signal.
  • SSO Signal Spreading Code
  • This signal is then used to bi -phase modulate an RF carrier to form the RF spread spectrum signal.
  • the ones and zeros of the digital sprea signal are transformed into the differential phase of the RF carrier at o° and 180°. when the RF spread spectrum signal is received, it is processed to recover the ones and zeros of the digital spread signal.
  • a possible receiver processor is illustrated in FIGURE 1.
  • the RF spread spectrum signal is received via antenna 11, then converted to a baseband signal by heterodyning it against the local oscillator 1 .
  • the RF center frequency of the transmitter is accurately known and. the receiver local oscillator is set to that frequency.
  • the two frequencies are nearly identical differing only by a Doppler shift generated by the motion of the transmitter or receiver, and the relative frequency drift of the two oscillators.
  • the baseband signal is essentially the sum of the Doppler and drift frequencies bi -phase modulated by the digital spread spectrum signal .
  • the relative phase of the baseband signal is not known at this point in the system and therefore, the phase relationship of the baseband signal and the receiver clock and receiver generated SSC are also not known.
  • the effect of this uncertainty is removed by carrying out the heterodyne process using a Quadrature IF Mixer (QIFM) 14.
  • QIFM Quadrature IF Mixer
  • the QIFM produces two baseband signals: sin ( (LO-Sign) • t+ ⁇ ) and Cos ((LO-Sig) .
  • correlator is of FIGURE 1, is described in terms of processing a sinusoid function. 5
  • the expansion from sine to sine and cosine processing adds complexity but does not alter the principles of prior art processors or the principles of the processor described in this invention.
  • the first step in extracting the digital data is to ⁇ _ 0 identify the SSC or SSC's present and to determine the start time of the SSC. Once the SSC has been determined it can be cross correlated with the baseband signal to demodulate the baseband spread signal and recover the data.
  • the trail reference SSC generator 17 ⁇ _5 provides one or several SSC's which may be present in the received signal.
  • the correlator 18 tests each of these codes against the received binary spread signal.
  • the correlator functions and processes are the subject of this invention.
  • each data bit is modulated by one or more entire SSC sequences.
  • the code is a sequence of
  • each data bit is transformed either to the SSC or to the bit wise complement of the SSC.
  • a 7 bit code /00o 11 o 1 / is used. if the corresponding data were / 1 / 0 / the result of modulation would be 5 /oooi 101/1110010/, as illustrated in Table I below.
  • the modulation process is essentially that of multiplication.
  • the multiplication is modified to provide an assert, a 1 when the two signals are alike and a negate, a 0, when they are different.
  • T correlation proceeds by multiplying the binary spread signal by the SSC. The results are summed to an accumulator to form the cross-correlation function.
  • the trail SSC is the correct SSC, the baseband spread spectrum signal, the Data, and SSC are perfectly synchronized and no noise is present.
  • the accumulator ramps up or down smoothly reaching the appropriate 1 or 0 threshold. The result approximates the mathematical form of the cross-correlation given in Table II below.
  • codes actually in use are much longer, such as 1023 bits in the case of the Global Positioning satellite, even longer codes are common.
  • communication transmitters contain variations of the spreading code, constructed so that they are not easily confused with one another, codes having this property of avoiding confusion are nearly orthogonal.
  • the code received may differ from the code transmitted because of Doppler shift.
  • the frequency of the received signal will be shifted in frequency. If the Doppler frequency is such that one cycle occurs over the duration of the code, then the last bits in the code will be reversed relative to the first bits so that /0001101/ might become /0001010/ where the last three bits are reversed to represent the change in the phase of the received signal due to the Doppler shift.
  • the uncompensated Doppler frequency limits the duration of the correlation process.
  • FIGURES 1, 2a and 2b are presented to properly describe the prior art.
  • FIGURES 3 and 4 which are incorporated and constitute a part of the specification, illustrate the preferred, embodiments of the invention, and together with the description serve to explain the principles of the invention. Acquisition of h P t si ⁇ nal
  • FIGURES 2a serial correlator illustrated by FIGURES 2a .
  • the reference SSC elements, R(j), generated for use in the correlator, as shown in FIGURE ⁇ , elements 17 and 18 enter one port of EXNOR (FIGURE 2a, element 17) and the data elements D(i) enter the other port .FIGURE 2a, element 16), These digital elements are effectively multiplied by the ExNOR.
  • the "truth table" for the ExNOR function is given in the Table III above. So that when the elements match the result is 1 when they do not match the result is o.
  • the resulting products are added to the previous accumulat ion of products until the sum of all such products data and reference SSC are complete.
  • One possible means of accumulation of such a sum consists of the Arithmetic Logic Unit (ALU) is and register 19 in FIGURE za .
  • ALU Arithmetic Logic Unit
  • ⁇ D_R j .
  • the acquisition process requires that each code and each code as modified by Doppler be correlated against each possible time of arrival until a match is found.
  • the number of possible times of arrival correspond to the length of the SSC in a favorable signal to noise environment a satisfactory result may be obtained by observing the correlation over a fraction of the SSC length. In less favorable environments it may be necessary to observe over the entire duration of the SSC or even longer.
  • the code contained N. bits so that there are N, possible delays or times of arrival, there were N legal codes and N. possible Doppler frequencies and Tint is the integration or accumulation time.
  • the data and reference sequence would have to be compared on the average for a duration of 2 • • N. • N • N. Tint to identify the source transmitter, the Doppler and the code time offset (phase) before the message can be decoded.
  • Each trial correlation may require processing of an entire sequence or more. This amount of computation requires a substantial time as illustrated in Table VI below.
  • the time required to search all possible codes is 41 seconds on the average and this is far from the most extreme condition.
  • some applications such as navigating a small boat, there is plenty of time, in others, such as guiding a missile (in which case in all likelihood N.> 1 increasing the acquisition time), time is at a premium and a long synchronization time may jeopardize the effectivity of the system.
  • the serial correlator processor does not work like a passive linear matched filter in the sense that it does not use partially overlapped input sequences to produce matched filter output at different time instants; rather it uses temporarily non-overlapped input segments to produce all the required outputs in sequence, when one output is obtained, the computation of the next one begins, leaving many output gaps (corresponding to various shifts between reference and data) to be completed over a longer duration. in this sense time is wasted.
  • the second prior art device is the matched filter correlator.
  • the matched filter correlator was developed to ameliorate the time required to acquire the signal.
  • This device as adapted to a 1023 chip code, performs the functions of 1023 serial correlators operating together. Again the result corresponds to one value of T , one SSC and one Doppler but the result is obtained in one chip time, 1 /1023th the time required of the serial correlator. The increase is speed is obtained at a proportional increase in complexity and power consumption.
  • the reference SSC is entered into the Reference shift Register 13 while the Data elements are entered into the Data shift Register 12.
  • each stage in the Reference shift Register is multiplied by the value of the corresponding stage in the data shift register in one of the four quadrant multipliers 11.
  • the products of all multipliers are entered into the summing bus 14 and then to the summing device 15.
  • the summation of all 1023 products, for one delay are generated simultaneously and appear at the output of summing device 15.
  • the time required to perform the correlation is reduced by 2 • 1023, to 0.020 seconds.
  • the 5,680,414 patent discloses an apparatus and method for synchronizing a spread spectrum receiver which includes a preamble matched filter and a plurality of symbol code correlators for receiving and correlating to a received spread spectrum signal.
  • the preamble matched filter outputs a correlation signal including a correlation pulse of variable width.
  • the pulse is converted to a square wave having a duration of a discrete number of chip periods.
  • the correlation pulse is used as a timing reference for the symbol code correlators.
  • a center seeking circuit provides an offset to the timing reference according to the width of the correlation pulse.
  • a timing window is used for a subsequent time frame for defining a period of time in which the correlation signal output from the preamble matched filter can yield a valid correlation pulse.
  • the 5,438,532 patent discloses a separation filter having a memory for storing sequential input data.
  • a multiplier multiplies the sequential input data, read from the memory, and an accumulator sequentially accumulates the resulting multiplication from the multiplier.
  • An adder/subtracter adds or subtracts two accumulation results, obtained from a pair of registers, and outputs the operation result as two pieces of sequential output data.
  • an adder/subtracter adds or subtracts two pieces of sequential input data together or one from the other
  • a multiplier multiplies the operation result, read from a memory
  • an accumulator accumulates the result from the multiplication and outputs the result as sequential output data which is the two pieces of sequential input data synthesized.
  • the 4,660,164 patent discloses a high speed multiplexed digital correlator device for correlating serial data against reference data.
  • the device includes digital correlators configured to operate in parallel with thrir operations overlapping in time.
  • the serial data is divided between the correlators by a multiplexing circuit.
  • the outputs of the correlators are summed to produce an overall correlation output s ignal .
  • the 2,115,192 (U.K.) patent discloses a digital signal processor having timing means for providing a succession of sample intervals in which incoming digital signals may have discrete values.
  • a single bit shift register produces a delayed signal and an arithmetic section has a plurality of bit multipliers, or difference squarers.
  • An accumulator has a plurality of channels each associated with an arithmetic element. Collectively the channels provide the required mathematical operation, auto or cross correlation function or structure function calculation.
  • the overall delay increase may be variable and geometric although increases between adjacent channels may be approximations to a geometric increase.
  • the delay lock discriminator This device generates the reference sequence as determined by the acquisition process at several delays both greater and smaller than delay determined by the acquisition process. Correlation results for the greater delays are aggregated and subtracted from an aggregation of smaller delays to form the output of the delay lock discriminator. The output of the discriminator trend positive as the delay becomes too long and negative as the delay becomes too short. This result is used to adjust the clock frequency of the receiver to maintain synchronization.
  • This invention provides improvements in the serial correlator of FIGURE 2a by adding the capability for multiple, simultaneous, parallel correlations. At the same time the invention avoids the intractable complexity of the fully matched filter correlator of FIGURE 2b. in addition, this invention provides a means by which the degree of parallelism may be selected according to the application to provide a "best value" solution for a particular application.
  • FIGURE 1 is a block diagram of a spread spectrum receiver as used in the prior art.
  • FIGURE 2a is a block diagram of a serial correlator as used in the prior art.
  • FIGURE 2b is a block diagram of a matched filter correlator as used in the prior art.
  • FIGURE 3a is a block diagram of an improved correlator with ALU and registers.
  • FIGURE 3b is a block diagram of an improved correlator having four quadrant multipliers and a RAM.
  • FIGURE is a block diagram of the preferred embodiment of the improved correlator.
  • FIGURE 3 illustrates multiple delay cross-correlation processing.
  • the elements of a data stream enter the serial port of a four stage shift register 30.
  • the four parallel outputs of the shift register are each connected to the inputs of a multiplexer 31.
  • the multiplexer selects one input and connects it to one data input of the ALU 32.
  • the output from the ALU is distributed by demultiplexer 33 to the input of one of the registers 34 which serve as one word memories.
  • Multiplexer 35 selects the output of one of the registers and connects it to the second data input of ALU 32.
  • the multiplexer and demultiplexer act quickly, sequentially connecting each element of the shift register to the ALU and each memory output to the ALU within the signal spreading code (SSC) chip time.
  • SSC signal spreading code
  • the indicated product, f(t) • g.t+7 " ) is a four quadrant function which can be implemented in a number of ways as a function of how f() is represented. Note that f() and g() can be interchange without changing the functionality. In the simplest case, where f() is expressed as a binary number, the ExNOR function may be used. In a more complex case a four quadrant digital multiplication may be used. In the preferred implementation the multiplication is implemented by noting that g() is always a binary function even though f() may be binary or a multi bit digital number. Since g() is either +1 or -1 the multiplication can be implemented by using an Arithmetic Logic unit ALU, and causing g() to cause either addition or subtraction.
  • ALU Arithmetic Logic unit
  • FIGURE 3b illustrates the identical process to that of FIGURE 3a. It is provided to illustrate a compact implementation where the demultiplexer 33, registers 34 and second multiplexer 35 are replaced by random access memory RAM 36. Those skilled in the art will recognize that the referenced demultiplexer register multiplexer arrangement is essentially the structure of a RAM.
  • FIGURE 3b further illustrates multiplication using a four quadrant multiplier separate from the accumulator RAM arrangement.
  • FIGURES 2 and 3 then illustrate multiplication by ExNOR, Four Quadrant
  • FIGURE The preferred embodiment of this invention is shown in FIGURE .
  • the embodiment of FIGURE 4 multiples using the controlled ALU and accumulation in multiplexed registers. It should be understood that the other multiplication methods described above or the RAM storage described above could be used equally well in this embodiment.
  • the primary importance of FIGURE is flexibility of the concept, its ability to provide a capability intermediate between the serial correlator and matched filter of the prior art. This capability is not present in the prior art from those concepts.
  • the user who wishes to expand capability of the serial correlator or the matched filter has only one option, that is to add more circuits of the same kind. Neither can take advantage of the increased speed capability of modern circuit elements since they are tied to chip rate of the data.
  • the preferred embodiment of this invention allows that flexibility.
  • Shift register 40 is of arbitrary length, here indicated as M x N, where M is the number of partitions and N is the number of data elements in each partition. (Note that FIGURE 4 does not show all elements in detail and only the components corresponding to the left most processing element are shown. M such processing elements are indicated and corresponding components of all processing element are identical).
  • M processing circuits each consisting of an input multiplexer 41, ALU 42, acting as multiplication means, demultiplexer 43, an N word memory 44, consisting of N registers and an output multiplexer 45.
  • Each input multiplexer 41 has access to a partition N stages of the data shift register.
  • the multiplexers and demultiplexers are driven at N times the chip rate and every element in the processing circuits is capable of operating at N times during each chip of the SSC.
  • the reference SSC is connected to the control port, +/- of each ALU 42. This element of the SSC multiplies each of the M x N elements of the data stored in the input shift register 40 during the SSC chip time. The accumulations of each multiplication appear sequentially at the outputs of the M multiplexers 45, and re labele the 1st through the Mth Muxed sum.
  • the multiplexed sums are multiplexed onto a single conduit by multiplexer 46, This conduit contains a sequential sampling of each of the M x N multiplexed sums. These multiplexed sums are in fact the cross correlation products for delays 1 through M x N. The sequence is completed during a single chip time of the SSC, and therefore operates at an effective rate equal to the SSC chip rate x M x N.
  • FIGURE 1 indicates that the correlator operates on a data word comparing I and Q heterodyne products.
  • the output conduit of multiplexer 46 contains the I and Q correlation products. These products are transformed to magnitude and phase by the magnitude computation 47, the phase term m y be made available but is not commonly used.
  • the compute statistics function 48 monitors the magnitude function and indicates for which delay if any of it exceeds the correlation threshold (by also selecting the largest magnitude over the delays). A magnitude greater than threshold signal indicates that the trial SSC has been found in the data and its relative delay. This completes the acquisition function for one SSC. Another of the SSC which may be present is selected and the process is repeated.
  • each processing block made up of components 42-45, is similar to the processing block of FIGURE 3b.
  • FIGURE 4 is then made UP of N such processing blocks according to FIGURE 3b, each such block is connected to the data shift register 40, by the input multiplexers 41 with output formed by multiplexers 45; each being identified as a Muxed Sum.
  • the preferred embodiment provides flexibility to the user in both the number of stages N x M, the number of processing blocks or partitions N and. the width of each block M. It is important to realize that the number of stages in the data shift register is not limited but can be extended indefinitely to suit the speed requirements and complexity limitations of a particular application.
  • the acquisition time in such a configuration is reduced by a nominal factor M x N relative to a serial cross correlator found in the prior art.
  • One possible configuration, capable of performing 60 simultaneous correlations would employ 12 processing blocks each with a span of 5 data elements. The result is a 60 fold decrease in processing time. The 41 seconds estimated for the single serial correlator is reduced to 0.70 seconds. In addition it provides the advantage of examining 60 delays simultaneously. Note the distinction between this and the possible modification of the basic parallel correlator of the prior art FIGURE 2 to a length of 60. That modification would provide the same 60 fold decrease in overall processing time but with more processing hardware and more complex interconnect lvity. Both provide the unique advantage of scanning 60 adjacent delays. The results from these correlations, even though partial, may provide sufficient information to allow selecting a new reference sequence early in the search process. Also note that the reference sequence s not stored, in a shift register so that an alternate sequence may be substituted very quickly. Track in ⁇ APDI i ra ion
  • FIGURE 4 is provided to illustrate that by a minor modification the structure of FIGURE 4 provides a means of simultaneously tracking several SSCs. This transition between acquisition and tracking is appropriately made immediately after the presence or absence of all possible SSCs, timing and doppler has been made and identified. At that time the identified SSCs are generated with appropriate delays as determined in the acquisition process. The properly delayed codes are applied, one to each processing block at the control terminal of the ALU, +/-. In FIGURE 4 these SSC inputs were driven by a single trial SSC, a configuration to minimize the time acquisition. In trackin g , these individual SSCs replace the single trial SSC which was applied to all processing block
  • the M Muxed Sum provide tracking data for the S S C a pp lied to that block.
  • These multiplexed sums scan out correlation result for N delays covered by the associated in p ut shift register partition. They are the cross correlation result of data and identified reference ssc over a span of delays from less than to greater than the acquired delay. The nominal result is that the cross correlation result increases as the delay error ma g nitude decreases, reaching a maximum at the correct delay. This behavior is indicated in Table IX below for a case where the correct delays is properly centered in the span of a 7 delay processor block.
  • a delay error detector is implemented. The magnitude and sign of this result corresponds to the magnitude and sign of the delay error.
  • the delay error thus detected can be utilized to track and correct slow changes in delay error for the individual SSC and maintain synchronism. improved delay resolution, sometimes required in tracking operation, may be obtained . by increasing the clock frequency used.
  • the architecture presented herein can be extended in obvious manner to correlate arbitrary digital waveform references to like waveforms that can be found in the received signals.
  • the extension amounts to inserting four quadrant multiples at the control inputs of the ALU's and feeding a sample and digitized reference waveform samples to one input of the multiplier instead of the binary code sequence. (In the binary case multiplication by one renders the multipliers redundant).

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne un dispositif destiné à recevoir un flux de données comportant une pluralité de messages à étalement du spectre de domaine temporel dans le même canal de fréquence. Chaque message est indépendant et étalé de manière spectrale avec un code unique, et le flux de données contient un sous-ensemble de tous les codes connus. Le dispositif détermine un code spécifique et un décalage de phase constant entre le code entrant et un code de référence par déplacement sériel du flux de données dans un registre de décalage (40), soumission de toutes les sorties de registre de décalage à un code de référence prévu unique, et accumulation des résultats pour chaque sortie au moyen d'une pluralité d'accumulateurs (42). Le décalage de code et de phase est indiqué par la gamme d'accumulation la plus large, au dessus d'un seuil produit par un circuit (48), correspondant à la sortie du registre de décalage pour le décalage de phase correct entre le code entrant et la référence. Lorsqu'un cycle d'intégration s'achève, le délai de décalage temporel augmente de la longueur du registre de décalage (40). Le processus continue pour tous les décalages temporels relatifs possibles et tous les codes de référence.
EP99955038A 1999-10-18 1999-10-18 Correlateur numerique Withdrawn EP1224764A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1999/024425 WO2001030015A1 (fr) 1996-07-08 1999-10-18 Correlateur numerique

Publications (2)

Publication Number Publication Date
EP1224764A1 true EP1224764A1 (fr) 2002-07-24
EP1224764A4 EP1224764A4 (fr) 2003-02-19

Family

ID=22273857

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99955038A Withdrawn EP1224764A4 (fr) 1999-10-18 1999-10-18 Correlateur numerique

Country Status (2)

Country Link
EP (1) EP1224764A4 (fr)
AU (1) AU1123500A (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3735374A1 (de) * 1987-10-19 1989-05-03 Siemens Ag Digitale korrelatorschaltung
EP0874471A2 (fr) * 1997-04-24 1998-10-28 Sharp Kabushiki Kaisha Correlateur de spectre étalé à séquence directe
US5933447A (en) * 1996-08-22 1999-08-03 Golden Bridge Technology, Inc. Symbol-matched filter having a low silicon and power requirement

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3735374A1 (de) * 1987-10-19 1989-05-03 Siemens Ag Digitale korrelatorschaltung
US5933447A (en) * 1996-08-22 1999-08-03 Golden Bridge Technology, Inc. Symbol-matched filter having a low silicon and power requirement
EP0874471A2 (fr) * 1997-04-24 1998-10-28 Sharp Kabushiki Kaisha Correlateur de spectre étalé à séquence directe

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
POVEY G J R: "SPREAD SPECTRUM PN CODE ACQUISITION USING HYBRID CORRELATOR ARCHITECTURES" WIRELESS PERSONAL COMMUNICATIONS, KLUWER ACADEMIC PUBLISHERS, NL, vol. 8, no. 2, 1 September 1998 (1998-09-01), pages 151-164, XP000765361 ISSN: 0929-6212 *
See also references of WO0130015A1 *

Also Published As

Publication number Publication date
EP1224764A4 (fr) 2003-02-19
AU1123500A (en) 2001-04-30

Similar Documents

Publication Publication Date Title
US6005903A (en) Digital correlator
CA2360061C (fr) Filtre adapte multibandes multicanaux a acquisition sequentielle
US7505511B2 (en) Matched filter and spread spectrum receiver
US8630331B2 (en) Method and system for spread spectrum signal acquisition
US7526015B2 (en) Parallel correlator implementation using hybrid correlation in spread-spectrum communication
EP0083480A1 (fr) Récepteurs pour des systèmes de navigation par satellites
US20070160117A1 (en) Satellite signal receiver apparatus and satellite signal reception method
US7558312B2 (en) Parallel correlator implementation using block integration for spread-spectrum communication
US6847676B1 (en) All-lag spread-spectrum correlators with rotating references
EP1224764A1 (fr) Correlateur numerique
CN115856956A (zh) 一种gnss基带接收通道电路
US6668012B1 (en) Identification of an identifiable code sequence in a received signal by correlation with summed different-phase replicas of the sequence
Lee et al. Matched-filter-based low-complexity correlator for simultaneously acquiring global positioning system satellites
US7277476B2 (en) Determining the correlation between received samples and available replica samples
US7342953B2 (en) Synchronization detection circuit
US6400757B1 (en) Symbol-matched filter having a low silicon and power management
WO2005062479A1 (fr) Poursuite d'un signal module par un code
KR20020075770A (ko) 정합 필터 및 확산 스팩트럼 수신기
Akopian et al. Fast DS-SS Acquisition Implementation for High Sensitivity Receivers
JPH11205193A (ja) マッチドフィルタバンク

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20020422

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

R17P Request for examination filed (corrected)

Effective date: 20020417

A4 Supplementary search report drawn up and despatched

Effective date: 20030109

RIC1 Information provided on ipc code assigned before grant

Ipc: 7G 06F 17/15 B

Ipc: 7H 04L 7/00 A

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20050307