EP1218940A1 - On-chip electric power supply having optimized electromagnetic compatibility - Google Patents

On-chip electric power supply having optimized electromagnetic compatibility

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Publication number
EP1218940A1
EP1218940A1 EP00962539A EP00962539A EP1218940A1 EP 1218940 A1 EP1218940 A1 EP 1218940A1 EP 00962539 A EP00962539 A EP 00962539A EP 00962539 A EP00962539 A EP 00962539A EP 1218940 A1 EP1218940 A1 EP 1218940A1
Authority
EP
European Patent Office
Prior art keywords
power supply
modules
chip
capacitive
buffer means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00962539A
Other languages
German (de)
French (fr)
Inventor
Thomas Steinecke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1218940A1 publication Critical patent/EP1218940A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to an integrated circuit implemented on a chip, which has a plurality of modules, common power supply pins for the modules and capacitive buffering means for buffering the power supply.
  • FIGS. 1, la and 2, 2a Two different conventional power supply concepts for powering an integrated circuit implemented on a chip are shown in FIGS. 1, la and 2, 2a, with FIGS. 1 and 2 showing schematic plan views of the IC and the integrated circuit, respectively, while FIGS 2a shows the respective equivalent circuit diagrams of the circuits according to
  • Dynamic current flow is to be understood as the current flow for supplying the modules of the integrated circuit which corresponds to the current current requirement or switching current of the modules.
  • FIGS. 1 and 1a A power supply concept for an integrated circuit of the previous type implemented on a chip without any buffer means is shown in FIGS. 1 and 1a.
  • the chip is generally designated by the reference number 1.
  • An integrated circuit is formed on the chip 1, which comprises four modules 2, 3, 4 and 5 by way of example.
  • the power supply for these modules, which can be any circuit, is carried out, for example, from two supply pins 6, 7, which can be arranged on the edge of the chip 1.
  • the supply pins 6, 7 are connected to two laterally spaced supply tracks 8, 9, which extend in a straight line and parallel to each other.
  • the power supply connections of the modules 2, 3, 4, 5 are each connected to the supply tracks 8, 9 via a pair or more pairs of connecting tracks. These connecting tracks are hatched schematically in FIG.
  • FIGS. 2 and 2a Apart from these capacitive buffer means, the circuit of FIGS. 2, 2a corresponds to the circuit of FIG. 1, la explained above, which is why corresponding parts are provided with the same reference numbers and their explanation is unnecessary.
  • the capacitive buffer means are in the form of two capacitors 15, 16, which are implemented as on-chip capacitors, and parallel to the supply tracks 8, 9 switched, with the help of connecting tracks that run parallel to the connecting tracks for the modules 2, 3, 4 and 5.
  • the two capacitive buffer means or capacitors 15, 16 are arranged between the module pairs 2, 3 and 4, 5 and are represented in the equivalent circuit diagram according to FIG.
  • resistors R2, R4 in the supply lines 8, 9 of FIG. 1a are shown as resistors R2a, R2b and R4a, R4b.
  • this fact can also be represented as follows: in the capacitors 15, 16, electrical charge is stored, which the downstream modules 4, 5 can access in the case of switching currents, so that these modules from the capacitors 15, 16 Indirectly or buffered and not taking current directly from the supply pins 6, 7, starting from which charging current flows into the capacitors 15, 16.
  • a correspondingly buffered current source is however not available for the modules 2, 4 immediately following the supply pins 6, 7, which is why they charge directly in the case of switching currents from the supply pins 6, 7 and thus from the current source 14.
  • the buffer means in the form of capacitors 15, 16 for the buffered power supply of the modules 2, 3 are out of the question, for which reason switching current drawn from these modules directly loads the direct current source 14 and thus generates interference radiation.
  • the invention has for its object to provide an integrated circuit on a chip with a common power supply of the type mentioned, which is optimized with respect to electromagnetic interference.
  • the invention therefore provides a complete impedance separation of the on-chip power supply system from the external power supply.
  • each module of the integrated circuit implemented on the chip is supplied with current via capacitive buffer means and not only selected modules as in the prior art explained above.
  • each module of the integrated circuit draws its current from an upstream capacitive buffering means, so that the externally supplied current is used exclusively for refilling the capacitive buffering means with electrical charge.
  • EMC electromagnetic interference
  • the on-chip power supply system according to the invention is advantageously in the form of a ring supply concept with rings around the modules arranged in the center of the chip
  • the capacitance of the capacitive buffer means is preferably selected so that it is at least essentially sufficient to cover the dynamic current requirement of the modules of the integrated circuit.
  • the capacitive buffer means are advantageously formed as on-chip capacitors.
  • Fig. 1 shows a first embodiment of an integrated circuit executed on a chip without capacitive
  • La is an equivalent circuit diagram of the integrated circuit of Fig. 1,
  • FIG. 2 shows a first embodiment of an integrated circuit implemented on a chip with capacitive buffering means partially effective for selected modules according to the prior art
  • FIG. 2a is an equivalent circuit diagram of the integrated circuit of FIG. 2,
  • FIG. 3 shows an integrated circuit implemented on a chip with on-chip power supply components separated in terms of impedance from an external power supply system. system for all modules according to the invention, and FIG. 3a shows an equivalent circuit diagram of the integrated circuit from FIG. 3.
  • an integrated circuit with modules 2, 3, 4, 5 is implemented on a chip 1.
  • the four modules 2, 3, 4, 5 are arranged in the center of the chip 1 next to one another in outline forming a square.
  • the power supply tracks belonging to the circuit are shown in FIG. 3 with black areas and the capacitive buffer means provided according to the invention are arranged under the power supply tracks in a neutral manner and are shown hatched in FIG. 3. Accordingly, the power supply tracks and the capacitive buffer means each form a ring system, which is why the power supply concept according to the invention can be referred to as a ring power supply concept.
  • each of the module pairs 2, 3 or A and 4, 5 or B obtains its dynamic current requirement from capacitive buffer means or capacitors C1 and C2 which are dimensioned in this way that they are able to provide the required dynamic switching currents, so that the
  • Power supply pins 6, 7 from the external power source 14 only charge current for the capacitors C1 and C2 is supplied to the chip 1.
  • This power supply concept ensures that the circuit implemented on the chip 1 produces essentially no or only a very low electromagnetic radiation for the environment in comparison with the prior art.
  • the core of this design of the A circuit implemented on a chip is accordingly the provision of the electrical charge required for the dynamic switching currents of the modules on the chip 1, at least essentially in its entirety, while minimizing interference radiation (EMC).

Abstract

The invention relates to an integrated circuit which is realized on a chip (1) and which comprises several modules (2, 3, 4, 5), common power supply pins (6, 7) for the modules (2, 3, 4, 5) and capacitive back-up means (C1, C2) for backing-up the power supply. The invention provides that capacitive back-up means (C1, C2) are assigned to each module (2, 3, 4, 5).

Description

Beschreibungdescription
EMV-optimierte On-Chip-Stro versorgungEMC-optimized on-chip power supply
Die vorliegende Erfindung betrifft eine auf einem Chip ausgeführte integrierte Schaltung, die mehrere Module, gemeinsame Stromversorgungspins für die Module und kapazitive Puffermittel zur Pufferung der Stromversorgung aufweist.The present invention relates to an integrated circuit implemented on a chip, which has a plurality of modules, common power supply pins for the modules and capacitive buffering means for buffering the power supply.
Zwei unterschiedliche herkömmliche Stromversorgungskonzepte zur Stromversorgung einer auf einem Chip ausgeführten integrierten Schaltung sind in Fig. 1, la und 2, 2a gezeigt, wobei Fig. 1 und Fig. 2 schematische Draufsichten des IC bzw. der integrierten Schaltung zeigen, während Fig. la und Fig. 2a die jeweiligen Ersatzschaltbilder der Schaltungen gemäßTwo different conventional power supply concepts for powering an integrated circuit implemented on a chip are shown in FIGS. 1, la and 2, 2a, with FIGS. 1 and 2 showing schematic plan views of the IC and the integrated circuit, respectively, while FIGS 2a shows the respective equivalent circuit diagrams of the circuits according to
Fig. 1 und 2 zeigen. In diesen Figuren ist der jeweilige dynamische Stromfluß mit Pfeilen gezeigt. Unter dynamischem Stromfluß ist derjenige Stromfluß zur Versorgung der Module der integrierten Schaltung zu verstehen, welcher dem aktuel- len Strombedarf bzw. Schaltstrom der Module entspricht.1 and 2 show. The respective dynamic current flow is shown in these figures with arrows. Dynamic current flow is to be understood as the current flow for supplying the modules of the integrated circuit which corresponds to the current current requirement or switching current of the modules.
Ein Stromversorgungskonzept für eine auf einem Chip ausgeführte integrierte Schaltung bisheriger Bauart ohne jegliches Puffermittel ist in Fig. 1 und Fig. la gezeigt. In Fig. 1 ist der Chip allgemein mit der Bezugsziffer 1 bezeichnet. Auf dem Chip 1 ist eine integrierte Schaltung gebildet, die beispielhaft vier Module 2, 3, 4 und 5 umfaßt. Die Stromversorgung dieser Module, bei welchen es sich um beliebige Schaltkreise handeln kann, erfolgt zum Beispiel ausgehend von zwei Versor- gungspins 6, 7, die randseitig am Chip 1 angeordnet sein können. Die Versorgungspins 6, 7 sind mit zwei seitlich voneinander beabstandeten Versorgungsbahnen 8, 9 verbunden, die sich geradlinig und parallel zueinander erstrecken. Die Stro versorgungsanschlüsse der Module 2, 3, 4, 5 sind jeweils über ein Paar oder mehrere Paare von Anschlußbahnen mit den Versorgungsbahnen 8, 9 verbunden. Diese Anschlußbahnen sind in Fig. 1 schematisch schraffiert als senkrecht zu den Ver- sorgungsbahnen 8, 9 verlaufend dargestellt und im zu Fig. 1 gehörigen Ersatzschaltbild Fig. la mit den Bezugsziffern lo bis 13 bezeichnet. In Fig. la sind der Einfachheit halber die jeweils auf derselben Höhe in bezug auf Versorgungsbahnen 8, 9 liegenden Module 2, 3 und 4, 5 als einheitliches Modul A und B verdeutlicht. Der Ohm* sehe Charakter der Versorgungsbahnen 8, 9 ist in Fig. la durch Widerstände dargestellt, nämlich durch die in diesen Leitungen liegenden Widerstände Rl, R2 und R3, R4. Die Anschlußbahnen (Doppel)Modul A sind mit 10, 11 bezeichnet und die entsprechenden Anschlußbahnen für das (Doppel)Modul B sind mit 12, 13 bezeichnet. Anstelle der Anschlußpins, 6, 9 ist in dem Ersatzschaltbild gemäß Fig. la eine externe Gleichstromquelle gezeigt, die mit der Bezugsziffer 14 bezeichnet und mit den Anschlußpins 6, 7 ver- bunden ist. Die niederohmige Auslegung der Versorgungsbahnen 8, 9 und der Anschlußbahnen 10, 11 und 12, 13 gewährleistet die im wesentlichen ungehinderte Zuführung auch hoher benötigter Schaltströme von der externen Stromquelle 14 über die Versorgungspins 6, 7 zu den Modulen. Da bei diesem Stromver- sorgungskonzept jedoch keine Maßnahmen getroffen sind, um die von den Modulen 1 bis 4 im Betrieb gezogenen dynamischen Ströme vom äußeren System, beispielsweise Bauteile auf einer Schaltkarte, auf welchem der Chip 1 angeordnet ist, abzuschirmen, besteht die Gefahr, daß der Chip 1 in diese Umge- bung eine relativ hohe elektromagnetische Störstrahlung (EMV) abgibt.A power supply concept for an integrated circuit of the previous type implemented on a chip without any buffer means is shown in FIGS. 1 and 1a. In Fig. 1, the chip is generally designated by the reference number 1. An integrated circuit is formed on the chip 1, which comprises four modules 2, 3, 4 and 5 by way of example. The power supply for these modules, which can be any circuit, is carried out, for example, from two supply pins 6, 7, which can be arranged on the edge of the chip 1. The supply pins 6, 7 are connected to two laterally spaced supply tracks 8, 9, which extend in a straight line and parallel to each other. The power supply connections of the modules 2, 3, 4, 5 are each connected to the supply tracks 8, 9 via a pair or more pairs of connecting tracks. These connecting tracks are hatched schematically in FIG. 1 as perpendicular to the connections Care tracks 8, 9 shown running and designated in the equivalent circuit diagram associated with FIG. 1 with the reference numerals lo to 13. In FIG. 1 a, for the sake of simplicity, the modules 2, 3 and 4, 5, which are each at the same level with respect to supply lines 8, 9, are illustrated as uniform modules A and B. The ohm * see character of the supply tracks 8, 9 is shown in Fig. La by resistors, namely by the resistors Rl, R2 and R3, R4 located in these lines. The connecting tracks (double) module A are labeled 10, 11 and the corresponding connecting tracks for the (double) module B are labeled 12, 13. Instead of the connection pins 6, 9, an external direct current source is shown in the equivalent circuit diagram according to FIG. 1 a, which is designated by the reference number 14 and is connected to the connection pins 6, 7. The low-resistance design of the supply tracks 8, 9 and the connecting tracks 10, 11 and 12, 13 ensures the substantially unimpeded supply of even high switching currents required from the external power source 14 via the supply pins 6, 7 to the modules. However, since no measures have been taken in this power supply concept to shield the dynamic currents drawn by the modules 1 to 4 during operation from the external system, for example components on a circuit card on which the chip 1 is arranged, there is a risk that the chip 1 emits a relatively high level of electromagnetic interference (EMC) in this environment.
Um dieses Problem einer relativ hohen Störstrahlung einzuschränken ist bei der in Fig. 2 und 2a gezeigten integrierten Schaltung eine entsprechende Abschirmmaßnahme in Gestalt von kapazitiven Puffermitteln getroffen. Abgesehen von diesen kapazitiven Puffermitteln entspricht die Schaltung von Fig. 2, 2a der vorstehend erläuterten Schaltung von Fig. 1, la, weshalb entsprechende Teile mit denselben Bezugsziffern versehen sind und deren Erläuterung sich erübrigt. Die kapazitiven Puffermittel sind in Gestalt von zwei Kondensatoren 15, 16, die als On-Chip-Kapazitäten realisiert sind, und parallel zu den Versorgungsbahnen 8, 9 geschaltet, und zwar mit Hilfe von Anschlußbahnen, die parallel zu den Anschlußbahnen für die Module 2, 3, 4 und 5 verlaufen. Die beiden kapazitiven Puffermittel bzw. Kondensatoren 15, 16 sind zwischen den Modul- paaren 2, 3 und 4, 5 angeordnet und in dem Ersatzschaltbild gemäß Fig. 2a durch einen einzigen Kondensator C dargestellt, der zwischen den Modulpaaren A, B angeordnet, stromab vom (Doppel)Modul A und stromauf vom (Doppel) Modul B ist. Aufgrund dieser Zuordnung des Kondensators C sind die Widerstän- de R2, R4 in den Versorgungsleitungen 8, 9 von Fig. la aufgeteilt dargestellt als Widerstände R2a, R2b und R4a, R4b.In order to limit this problem of relatively high interference radiation, a corresponding shielding measure in the form of capacitive buffering means has been taken in the integrated circuit shown in FIGS. 2 and 2a. Apart from these capacitive buffer means, the circuit of FIGS. 2, 2a corresponds to the circuit of FIG. 1, la explained above, which is why corresponding parts are provided with the same reference numbers and their explanation is unnecessary. The capacitive buffer means are in the form of two capacitors 15, 16, which are implemented as on-chip capacitors, and parallel to the supply tracks 8, 9 switched, with the help of connecting tracks that run parallel to the connecting tracks for the modules 2, 3, 4 and 5. The two capacitive buffer means or capacitors 15, 16 are arranged between the module pairs 2, 3 and 4, 5 and are represented in the equivalent circuit diagram according to FIG. 2a by a single capacitor C, which is arranged between the module pairs A, B, downstream of the (Double) Module A and upstream from (Double) Module B. Because of this assignment of the capacitor C, the resistors R2, R4 in the supply lines 8, 9 of FIG. 1a are shown as resistors R2a, R2b and R4a, R4b.
Bei der Konzeption dieser Chip-Stromversorgung wurde davon ausgegangen, daß die kapazitiven Puffermittel verhindern, daß Störströme aufgrund von hohen Schaltströmen für die Module in das externe System ausgekoppelt werden. Es hat sich jedoch erwiesen, daß diese Entstörungsmaßnahme im wesentlichen ausschließlich für die Module 4, 5 bzw. B zutrifft, vor welchen, bezogen auf die Versorgungspins 6, 7 die Kondensatoren 15, 16 angeordnet sind, während für die vor den Kondensatoren 15, 16 in bezug auf die Versorgungspins 6, 7 angeordneten Module 2, 3 eine Pufferung durch die Kondensatoren 15, 16 so gut wie nicht stattfindet; d.h. diese Module 2, 3 werden weiterhin unmittelbar ohne Abpufferung aus den Versorgungspins 6, 7 mit Strom versorgt, so daß deren Schaltströme nach wie vor eine relativ hohe elektromagnetische Störstrahlung für die Umgebung erzeugen. Dieser Sachverhalt kann mit anderen Worten auch wie folgt dargestellt werden: In den Kondensatoren 15, 16 ist elektrische Ladung abgespeichert, auf welche die nach- geschalteten Module 4, 5 im Fall von Schaltströmen zugreifen können, so daß diese Module aus den Kondensatoren 15, 16 indirekt bzw. gepuffert und nicht unmittelbar aus den Versorgungspins 6, 7 Strom entnehmen, ausgehend von welchem Ladestrom in die Kondensatoren 15, 16 nachfließt. Eine entspre- chend gepufferte Stromquelle steht jedoch für die unmittelbar auf die Versorgungspins 6, 7 folgenden Module 2, 4 nicht bereit, weshalb diese im Fall von Schaltströmen Ladung direkt aus den Versorgungspins 6, 7 und damit der Stromquelle 14 entnehmen. Jedenfalls kommen die Puffermittel in Gestalt von Kondensatoren 15, 16 zur gepufferten Stromversorgung der Module 2, 3 nicht in Betracht, weshalb von diesen Modulen gezo- gener Schaltstrom die Gleichstromquelle 14 unmittelbar belasten und damit Störstrahlung erzeugen.When designing this chip power supply, it was assumed that the capacitive buffer means prevent interference currents due to high switching currents for the modules from being coupled out into the external system. However, it has been found that this interference suppression measure applies essentially only to modules 4, 5 and B, in front of which, based on supply pins 6, 7, capacitors 15, 16 are arranged, while for those in front of capacitors 15, 16 with respect to the modules 2, 3 arranged for the supply pins 6, buffering by the capacitors 15, 16 practically does not take place; that is, these modules 2, 3 continue to be supplied with current directly from the supply pins 6, 7 without buffering, so that their switching currents still generate a relatively high electromagnetic interference radiation for the environment. In other words, this fact can also be represented as follows: in the capacitors 15, 16, electrical charge is stored, which the downstream modules 4, 5 can access in the case of switching currents, so that these modules from the capacitors 15, 16 Indirectly or buffered and not taking current directly from the supply pins 6, 7, starting from which charging current flows into the capacitors 15, 16. A correspondingly buffered current source is however not available for the modules 2, 4 immediately following the supply pins 6, 7, which is why they charge directly in the case of switching currents from the supply pins 6, 7 and thus from the current source 14. In any case, the buffer means in the form of capacitors 15, 16 for the buffered power supply of the modules 2, 3 are out of the question, for which reason switching current drawn from these modules directly loads the direct current source 14 and thus generates interference radiation.
Angesichts dieses Standes der Technik liegt der Erfindung die Aufgabe zugrunde, eine auf einem Chip ausgeführte integrierte Schaltung mit gemeinsamer Stromversorgung der eingangs genannten Art zu schaffen, die bezüglich der elektromagnetischen Störstrahlung optimiert ist.In view of this prior art, the invention has for its object to provide an integrated circuit on a chip with a common power supply of the type mentioned, which is optimized with respect to electromagnetic interference.
Gelöst wird diese Aufgabe durch die kennzeichnenden Merkmale des Anspruchs 1. Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen angegeben.This object is achieved by the characterizing features of claim 1. Advantageous developments of the invention are specified in the subclaims.
Demnach schafft die Erfindung mit anderen Worten eine vollständige impedanzmäßige Trennung des On-Chip-Stromversor- gungssystems von der externen Stromversorgung. Erreicht wird dies, indem jedem Modul der auf dem Chip ausgeführten integrierten Schaltung Strom über kapazitive Puffermittel zugeführt wird und nicht nur ausgewählten Modulen wie bei dem vorstehend erläuterten Stand der Technik. Mit anderen Worten zieht jedes Modul der integrierten Schaltung seinen Strom aus einem stromauf liegenden kapazitiven Puffermittel, so daß der extern zugeführte Strom ausschließlich zum Nachfüllen der kapazitiven Puffermittel mit elektrischer Ladung dient. Damit ist gewährleistet, daß elektromagnetische Störstrahlung (EMV) zumindest erheblich reduziert wird im Vergleich zum Stand der Technik, da auf dem Chip gezogene dynamische Ströme vom externen System ferngehalten werden und lediglich ein mehr oder weniger gleichmäßiger Nachladestrom aus der externen Stromversorgung in das Stromversorgungssystem auf dem Chip ge- speist wird. Bei Tests konnte ermittelt werden, daß Störstrahlung bei der erfindungsgemäß ausgelegten Schaltung im Vergleich zu dem in Fig. 2 und 2a gezeigten und einleitend erläuterten System um den Faktor 10 reduziert werden kann. Vorteilhafterweise ist das erfindungsgemäße On-Chip-Stro ver- sorgungssystem als Ringversorgungskonzept mit um die im Zen- trum des Chips angeordneten Modulen ringförmig geführtenIn other words, the invention therefore provides a complete impedance separation of the on-chip power supply system from the external power supply. This is achieved in that each module of the integrated circuit implemented on the chip is supplied with current via capacitive buffer means and not only selected modules as in the prior art explained above. In other words, each module of the integrated circuit draws its current from an upstream capacitive buffering means, so that the externally supplied current is used exclusively for refilling the capacitive buffering means with electrical charge. This ensures that electromagnetic interference (EMC) is at least considerably reduced compared to the prior art, since dynamic currents drawn on the chip are kept away from the external system and only a more or less uniform recharging current from the external power supply into the power supply system on the Chip is fed. Tests have shown that interference radiation in the circuit designed according to the invention in Comparison to the system shown in FIGS. 2 and 2a and explained in the introduction can be reduced by a factor of 10. The on-chip power supply system according to the invention is advantageously in the form of a ring supply concept with rings around the modules arranged in the center of the chip
Stromversorgungsbahnen und flächenneutral unter diesen Stromversorgungsbahnen angeordneten kapazitiven Puffermitteln ausgeführt. Die Kapazität der kapazitiven Puffermittel ist bevorzugt so gewählt, daß sie zumindest im wesentlichen zur Ab- deckung des dynamischen Strombedarfs der Module der integrierten Schaltung hinreichen.Power supply tracks and capacitive buffer means arranged area-neutral under these power supply tracks. The capacitance of the capacitive buffer means is preferably selected so that it is at least essentially sufficient to cover the dynamic current requirement of the modules of the integrated circuit.
Ferner sind vorteilhafterweise die kapazitiven Puffermittel als On-Chip-Kapazitäten gebildet.Furthermore, the capacitive buffer means are advantageously formed as on-chip capacitors.
Nachfolgend wird die Erfindung anhand der Zeichnung beispielhaft näher erläutert; es zeigen:The invention is explained in more detail below using the drawing as an example; show it:
Fig. 1 eine erste Ausführungsform einer auf einem Chip ausgeführten integrierten Schaltung ohne kapazitiveFig. 1 shows a first embodiment of an integrated circuit executed on a chip without capacitive
Puffermittel gemäß dem Stand der Technik,Buffering agents according to the prior art,
Fig. la ein Ersatzschaltbild der integrierten Schaltung von Fig. 1,La is an equivalent circuit diagram of the integrated circuit of Fig. 1,
Fig. 2 eine erste Ausführungsform einer auf einem Chip ausgeführten integrierten Schaltung mit partiell für ausgewählte Module wirksamem kapazitiven Puffermittel gemäß dem Stand der Technik,2 shows a first embodiment of an integrated circuit implemented on a chip with capacitive buffering means partially effective for selected modules according to the prior art,
Fig. 2a ein Ersatzschaltbild der integrierten Schaltung von Fig. 2,2a is an equivalent circuit diagram of the integrated circuit of FIG. 2,
Fig. 3 eine auf einem Chip ausgeführten integrierte Schal- tung mit impedanzmäßig von einem externen Stromversorgungssystem getrennten On-Chip-Stromversorgungs- system für sämtliche Module gemäß der Erfindung, und Fig. 3a ein Ersatzschaltbild der integrierten Schaltung von Fig. 3.3 shows an integrated circuit implemented on a chip with on-chip power supply components separated in terms of impedance from an external power supply system. system for all modules according to the invention, and FIG. 3a shows an equivalent circuit diagram of the integrated circuit from FIG. 3.
Fig. 1, la und Fig. 2, 2a sind einleitend zum Stand der Technik erläutert. Nunmehr wird die Erfindung anhand von Fig. 3 und 3a unter bezug auf Fig. 2, 2a näher erläutert, und zwar unter Nutzung derselben Bezugsziffern für gleiche Teile.1, la and Fig. 2, 2a are explained in the introduction to the prior art. The invention will now be explained in more detail with reference to FIGS. 3 and 3a with reference to FIGS. 2, 2a, using the same reference numbers for the same parts.
Gemäß Fig. 3 ist eine integrierte Schaltung mit Modulen 2, 3, 4, 5 auf einem Chip 1 ausgeführt. Die vier Module 2, 3, 4, 5 sind im Zentrum des Chips 1 nebeneinander im Umriß ein Qua- drat bildend angeordnet. Die zur Schaltung gehörenden Strom- versorgungsbahnen sind in Fig. 3 mit schwarzen Bereichen gezeigt und die erfindungsgemäß vorgesehen kapazitiven Puffermittel sind flächenneutral unter den Stromversorgungsbahnen angeordnet und in Fig. 3 schraffiert gezeigt. Demnach bilden die Stromversorgungsbahnen und die kapazitiven Puffermittel jeweils ein Ringsystem, weshalb bei dem erfindungsgemäßen Stromversorgungskonzept von einem Ringstromversorgungskonzept gesprochen werden kann.According to FIG. 3, an integrated circuit with modules 2, 3, 4, 5 is implemented on a chip 1. The four modules 2, 3, 4, 5 are arranged in the center of the chip 1 next to one another in outline forming a square. The power supply tracks belonging to the circuit are shown in FIG. 3 with black areas and the capacitive buffer means provided according to the invention are arranged under the power supply tracks in a neutral manner and are shown hatched in FIG. 3. Accordingly, the power supply tracks and the capacitive buffer means each form a ring system, which is why the power supply concept according to the invention can be referred to as a ring power supply concept.
Wie aus dem Ersatzschaltbild der Schaltung gemäß Fig. 3 in Fig. 3a hervorgeht, bezieht jedes der Modulpaare 2, 3 bzw. A und 4, 5 bzw. B seinen dynamischen Strombedarf aus kapazitiven Puffermitteln bzw. Kondensatoren Cl und C2, die derart dimensioniert sind, daß sie in der Lage sind, die benötigten dynamischen Schaltströme bereitzustellen, so daß über dieAs can be seen from the equivalent circuit diagram of the circuit according to FIG. 3 in FIG. 3a, each of the module pairs 2, 3 or A and 4, 5 or B obtains its dynamic current requirement from capacitive buffer means or capacitors C1 and C2 which are dimensioned in this way that they are able to provide the required dynamic switching currents, so that the
Stromversorgungspins 6, 7 von der externen Stromquelle 14 lediglich Ladestrom für die Kondensatoren Cl und C2 dem Chip 1 zugeführt wird. Durch dieses Stromversorgungskonzept wird gewährleistet, daß die auf dem Chip 1 verwirklichte Schaltung im wesentlichen keine bzw. nur eine sehr geringe elektromagnetische Abstrahlung für die Umgebung im Vergleich zu dem Stand der Technik erzeugt. Kern dieser Ausgestaltung der auf einem Chip realisierten Schaltung ist demnach die Bereitstellung der für die dynamischen Schaltströme der Module benötigten elektrischen Ladung auf dem Chip 1 zumindest im wesentlichen im gesamten benötigen Umfang unter Minimierung von Störstrahlung (EMV) . Power supply pins 6, 7 from the external power source 14 only charge current for the capacitors C1 and C2 is supplied to the chip 1. This power supply concept ensures that the circuit implemented on the chip 1 produces essentially no or only a very low electromagnetic radiation for the environment in comparison with the prior art. The core of this design of the A circuit implemented on a chip is accordingly the provision of the electrical charge required for the dynamic switching currents of the modules on the chip 1, at least essentially in its entirety, while minimizing interference radiation (EMC).
BezugszeichenlisteLIST OF REFERENCE NUMBERS
1 Chip1 chip
2 Modul2 module
3 Modul3 module
4 Modul4 module
5 Modul5 module
6 Stromversorgungspin6 power supply pin
7 Stromversorgungspin7 power supply pin
8 Stromversorgungsbahn8 power supply track
9 Stromversorgungsbahn9 power supply rail
10 Anschlußbahn10 connecting track
11 Anschlußbahn11 connecting track
12 Anschlußbahn12 connecting track
13 Anschlußbahn13 connecting track
14 Gleichstromquelle14 DC power source
Cl PuffermittelCl buffering agent
C2 PuffermittelC2 buffering agent
Rl WiderstandRl resistance
R2 WiderstandR2 resistance
R3 WiderstandR3 resistance
R4 Widerstand R4 resistance

Claims

Patentansprüche claims
1. Auf einem Chip (1) ausgeführte integrierte Schaltung, die mehrere Module (2, 3, 4, 5) , gemeinsame Stromversorgungspins1. On a chip (1) executed integrated circuit, the multiple modules (2, 3, 4, 5), common power supply pins
(6, 7) für die Module (2, 3, 4, 5) und kapazitive Puffermittel (Cl, C2) zur Pufferung der Stromversorgung aufweist, d a d u r c h g e k e n n z e i c h n e t, daß jedem Modul(6, 7) for the modules (2, 3, 4, 5) and capacitive buffering means (Cl, C2) for buffering the power supply, so that each module
(2, 3, 4, 5) kapazitive Puffermittel (Cl, C2) zugeordnet sind.(2, 3, 4, 5) capacitive buffering agents (Cl, C2) are assigned.
2. Schaltung nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, daß die kapazitiven Puffermittel (Cl, C2) in Stromversorgungsbahnen (8, 9) von den Stromversorgungspins (6, 7) zu Stromanschlüssen der Module (2, 3, 4, 5) integriert sind.2. Circuit according to claim 1, so that the capacitive buffer means (Cl, C2) in power supply tracks (8, 9) from the power supply pins (6, 7) to power connections of the modules (2, 3, 4, 5) are integrated.
3. Schaltung nach Anspruch 2, d a d u r c h g e k e n n z e i c h n e t, daß die Module (2, 3, 4, 5) im Zentrum des Chips (1) angeordnet und die Stromversorgungsbahnen (8, 9) ringförmig um die Module (2, 3,3. Circuit according to claim 2, so that the modules (2, 3, 4, 5) are arranged in the center of the chip (1) and the power supply tracks (8, 9) are ring-shaped around the modules (2, 3,
4. 5) geführt sind.4. 5) are performed.
4. Schaltung nach Anspruch 2 oder 3, d a d u r c h g e k e n n z e i c h n e t, daß die kapaziti- ven Puffermittel (Cl, C2) flächenneutral unter den Stromversorgungsbahnen (8, 9) angeordnet sind.4. Circuit according to claim 2 or 3, so that the capacitive buffer means (Cl, C2) are arranged area-neutral under the power supply tracks (8, 9).
5. Schaltung nach einem der Ansprüche 1 bis 4, d a d u r c h g e k e n n z e i c h n e t, daß die kapaziti- ven Puffermittel (Cl, C2) eine Kapazität zur Abdeckung des dynamischen Strombedarfs der Module (2, 3, 4, 5) aufweisen.5. Circuit according to one of claims 1 to 4, that the capacitive buffer means (Cl, C2) have a capacity to cover the dynamic current requirement of the modules (2, 3, 4, 5).
6. Schaltung nach einem der Ansprüche 1 bis 5, d a d u r c h g e k e n n z e i c h n e t, daß kapazitiven Puffermittel (Cl, C2) als On-Chip-Kapazitäten gebildet sind. 6. Circuit according to one of claims 1 to 5, d a d u r c h g e k e n n z e i c h n e t that capacitive buffer means (Cl, C2) are formed as on-chip capacitors.
EP00962539A 1999-09-30 2000-09-27 On-chip electric power supply having optimized electromagnetic compatibility Withdrawn EP1218940A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19947021 1999-09-30
DE19947021A DE19947021A1 (en) 1999-09-30 1999-09-30 EMC-optimized on-chip power supply
PCT/EP2000/009458 WO2001024262A1 (en) 1999-09-30 2000-09-27 On-chip electric power supply having optimized electromagnetic compatibility

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EP1218940A1 true EP1218940A1 (en) 2002-07-03

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EP (1) EP1218940A1 (en)
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WO (1) WO2001024262A1 (en)

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US20020131281A1 (en) 2002-09-19
WO2001024262A1 (en) 2001-04-05
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US6646475B2 (en) 2003-11-11

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