EP1216509B1 - Circuit arrangement for generating a clock-pulse signal having a frequency synchronous with a reference clock-pulse signal - Google Patents

Description

In digital communication systems, individual communication system components require a precise system clock to synchronize an exchange of communication data. Typically, individual communication system components for this purpose, highly accurate reference clock signals, eg. B. over the public network supplied. As a rule, the supplied reference clock signals do not directly effect a clock control of a communication system component, but are routed to a phase locked loop in which system clock signals are formed and transmitted to individual modules.

Since a trouble-free transmission of an external reference clock signal can not be guaranteed at any time, a separate highly stable reference clock source is often provided in a communication system component, which is used in case of failure of the external reference clock to stabilize the clock generator via a second phase locked loop.

Such a circuit arrangement is known for example from European Patent Application 0 262 481. This circuit includes a reference receiving part receiving the external reference clock signals and connected to a first input of a first phase comparator. The output of the first phase comparison device is passed through an integration device and a filter whose output can be connected by means of a switching element to a downstream voltage-controlled oscillator. The frequency-synchronous clock signals formed in the voltage-controlled oscillator are fed via its output both to an output of the circuit arrangement and to a second input of the first phase comparator.

The known circuit arrangement further includes a highly stable reference clock source whose output is connected to a first input of a second phase comparator. The second input of this second phase comparator is also connected to the output of the voltage controlled oscillator. The output of the second phase comparison device can be connected with the aid of a further switching element either with an additional filter or with a minuende input of a subtractor. The output of the subtractor, at the subtrahend input of which the output of the additional filter is connected, is connected via a further filter to a further input of the switching element.

The known circuit arrangement thus includes two phase locked loops, wherein the first phase locked loop is controlled by the external reference clock signals and the second phase locked loop by the reference clock signals of the highly stable reference clock source. Usually, the voltage controlled oscillator is synchronized to the supplied external reference clock signals. Bie failure of the external reference clock signals or exceeding predetermined phase differences is switched to the highly stable reference clock source. In the additional filter, during the synchronization by the external reference clock signals, the deviations of the frequency-synchronous clock signals to the reference clock signals of the high-stability reference clock source are collected and correction adjustment information is formed. These are drawn after switching to the highly stable reference clock source by means of the subtractor in the formation of setting information for the voltage controlled oscillator.

In this circuit arrangement, however, there is the problem that the frequency of the highly stable reference clock source should be relatively high to avoid too long a control delay. However, a high clock frequency also requires a relatively high power consumption, so that such Circuit arrangement for battery operation is less suitable. Furthermore, switching means are to be provided in such a circuit arrangement in order to detect periodically occurring phase overflows in the second phase comparison device. As a phase overflow while exceeding a phase difference of 360 degrees is called. Such phase overruns occur periodically when the frequency of the reference clock source and the frequency of the voltage controlled oscillator synchronized with the external reference clock signal, optionally after each pass through a frequency divider, differ systematically from each other.

It is an object of the present invention to provide a circuit arrangement for generating a frequency synchronous to the reference clock signals clock signal having an improved control characteristic, in particular when supplying a reference clock signal with relatively low clock frequency having.

This object is achieved by a circuit arrangement having the features of patent claim 1.

The circuit arrangement according to the invention has an oscillator whose clock frequency is synchronized in a first operating mode of the circuit arrangement by means of a first phase-locked loop comprising a first phase-locked loop with a supplied, first reference clock signal. Furthermore, a phase actuator and a second phase comparison device is provided, by means of which in the first operating mode a deviation of a supplied, second reference clock signal to the frequency-synchronous clock signal of the oscillator is detected and a phase correction information is formed. In a second operating mode of the circuit arrangement, for example in the event of failure of the first reference clock signal, the oscillator is no longer synchronized on the basis of the first reference clock signal, but on the basis of the second reference clock signal. Such a second mode becomes frequent also referred to as "hold-over mode". In the phase control while the phase correction information formed in the first mode is included. This is done by the fact that in the clock signal of the oscillator before a phase comparison with the second reference clock signal, clock phases depending on the phase correction information by a phase actuator or be ausgefügt.

By correcting the oscillator phase or oscillator frequency before the phase comparison with the second reference clock signal cyclically occurring phase overflows in the phase comparison can be avoided in a simple way in a systematic deviation of the first reference clock signal frequency synchronous oscillator clock signal to the second reference clock signal.

An advantage of the circuit arrangement according to the invention consists in a very good control characteristic and in short control time constants, which are ensured in particular even with a relatively low-frequency second reference clock signal. Generation of low-frequency reference clock signals generally requires less power than generation of higher-frequency reference clock signals, so that the circuit arrangement according to the invention, in conjunction with a low-frequency reference clock generator, is also well suited for battery operation. The good control characteristic is a consequence of the phase correction being applied by the phase actuator to the clock signal of the oscillator. Since the clock signal of the oscillator is usually much higher frequency than the second reference clock signal, the frequency of this clock signal can be controlled very fine before phase comparison by adding or inserting individual clock phases in the clock signal of the oscillator. In particular, this causes only a very small phase and pulse trembling.

Another advantage of the circuit arrangement according to the invention is that no processor is required for its realization. Instead, the circuitry may be e.g. be realized by means of a low-cost ASIC module (Application Specific Integrated Circuit).

Advantageous embodiments and further developments of the invention are specified in the dependent claims.

The output of the first phase comparator can be connected to the frequency control input of the oscillator via a switching element, such. Example, a transistor, a logic gate or a multiplexing device to be connected. This switching element can be controlled so that it is closed in the first mode of the circuit arrangement and open in the second mode.

Before the frequency control input of the oscillator, a filter such. Example, a simple low-pass filter or a so-called P, PI or PID filter, be connected for integrating supplied from the oscillator signals for frequency control. Frequently, the frequency control input of the oscillator itself can take over such a filter function.

Furthermore, a memory may be provided in which the phase correction information formed in the first operating mode remains stored as long as the circuit arrangement is in the second operating mode. In the second mode, the insertion and removal of clock phases in the phase actuator is then controlled depending on the stored phase correction information.

In order to compare two different clock signals by means of a phase comparator, it is usually necessary that the clock signals to be compared have the same nominal frequency. For comparing clock signals of different nominal frequency, these clock signals can each be supplied via a frequency divider of the phase comparator. The divider factor of a respective frequency divider is to be dimensioned so that the voltage applied to the inputs of the phase comparator, shared target frequencies are equal.

According to an advantageous development of the invention, a detector device can be provided with which it can be detected whether the first reference clock signal is present or not. An output of the detector device may be connected to one or more switching elements for controlling and / or switching the operating mode.

According to an advantageous embodiment of the invention, the control device may comprise an up / down counter whose counting direction depends on the output signal of the second phase comparison device. The up / down counter, for example, be controlled so that its count at predetermined times, eg. B. each at the positive or negative edges of the second reference clock signal, depending on whether the detected phase difference is positive or negative, either incremented or decremented. When the phase is equal, the counter reading can remain the same.

Furthermore, a phase actuator control may be provided with a counting register to be loaded with the count of the up / Abwährtszählers as Zählvorgabe. The counting register can be z. B. in a predetermined rhythm by a clock signal, starting from the count instruction to cause on reaching a predetermined counter mark on or off a clock phase in the phase actuator.

The counting register may further be divided into a first register part for high-order bits and a second register part for low-order bits, wherein a counting frequency, with the second register part is counted, is determined by the content of the first register part. By this functional separation of the register parts, a very large control range can be achieved even with a small length of the count register or the up / Abwährtszählers. In this case, the control is the more accurate, the lower the value of the higher-order, the count frequency determining bits of the Zählvorgabe, ie, the less differ from the second phase comparator clock signals to each other.

According to a further advantageous development of the invention, another, controlled by the control device phase actuator for deriving a further frequency synchronous clock signal from the second reference clock signal may be provided. In this way, for example, a frequency synchronous clock signal can be provided for a watch application.

According to a further embodiment of the invention, an output of a detector device which indicates the presence of the second reference clock signal can be connected to an alarm transmitter for triggering an alarm signal in the absence of the second reference clock signal.

According to a further embodiment variant, an output of a detector device which indicates the presence of the clock signal of the oscillator can be connected to an alarm transmitter for triggering an alarm signal in the absence of the clock signal.

An embodiment of the invention will be explained in more detail with reference to the drawing.

FIG 1

eine erfindungsgemäße Schaltungsanordnung in schematischer Darstellung und

FIG 2

eine grafische Veranschaulichung von Phasenbeziehungen von Taktsignalen.

Show

FIG. 1

a circuit arrangement according to the invention in a schematic representation and

FIG. 2

a graphical illustration of phase relationships of clock signals.

Figure 1 shows a circuit arrangement for generating a reference clock signals to be supplied RT1 and RT2 frequency-synchronous clock signal TO in a schematic representation. The circuit arrangement has a first phase locked loop, which comprises a first phase comparator PV1, a filter F and a voltage controlled oscillator, a so-called VCXO (Voltage Controlled X-tal Oscillator). The output of the phase comparator PV1 is on Switching element S2 in a first mode of the circuit arrangement with a filter F and connected via this with a frequency control input of the oscillator VCXO, which forms the clock signal TO to be synchronized. The filter F is used for integrating frequency control signals supplied by the oscillator VCXO and can be realized, for example, as a low-pass filter or as a so-called P, PI, or PID filter.

In the first operating mode, the clock signal TO is to be synchronized with the first reference clock signal RT1. Such a first reference clock signal RT1 is often derived for synchronization of communication devices from network clock signals, from signals transmitted by the public communications network or from signals received wirelessly from a time information transmitter. The first reference clock signal RT1 is fed via a frequency divider T1 to a first input E1, the first phase comparator PV1. Likewise, the clock signal TO of the oscillator VCXO is fed via a frequency divider T2 to a second input E2 of the first phase comparator PV1. The division factors of the frequency divider T1 and T2 are dimensioned so that the respective divided desired frequencies of the clock signal TO and the first reference clock signal RT1 are the same.

As a further functional components, the circuit arrangement has a phase actuator PS for inserting and removing clock phases into the clock signal TO, a second phase comparator PV2, and a control device RE. In the first operating mode of the circuit arrangement, said function components serve to detect a deviation of the clock signal TO frequency-synchronous with the first reference clock signal RT1 to the second reference clock signal RT2. The second reference clock signal RT2 is supplied to a first input E1 of the second phase comparator PV2. The second reference clock signal RT2 can be z. Example of a temperature-compensated oscillator, a so-called TCXO (Temperature Compensated X-tal Oscillator) are generated. For the present embodiment, assume that the second reference clock signal RT2 has an application typical frequency of 32768 Hz. The use of such a relatively low frequency has the advantage that commercial TCXOs can be used to generate the second reference clock signal RT2, which have a power consumption of only a few microamps. Thus, the circuit arrangement according to the invention in conjunction with a relatively low-frequency TCXO as a second reference clock source is also well suited for battery operation.

For phase comparison with the second reference clock signal RT2, the clock signal TO of the oscillator VCXO via the phase actuator PS and a frequency divider T3 for adjusting the oscillator setpoint frequency to the frequency of the reference clock signal RT2, a second input E2 of the second phase comparator PV2 supplied. In a typical oscillator setpoint of z. B. 16.384 Mhz is to adapt to the frequency of 32768 Hz of the second reference clock signal RT2 a frequency divider T3 with divider factor 500 provided. Such a high oscillator frequency allows a particularly fine control by inserting and removing clock phases.

The output signal of the second phase comparator PV2 is fed via a switching element S1 in the first mode to an up / down counter UDC of the controller RE and determines its counting direction. The count frequency of the up / down counter UDC is given by the second reference clock signal RT2 also applied thereto. For example, at each phase edge of the second reference clock signal RT2, which leads the corresponding phase edge of the divided clock signal TO, the up / down counter UDC can be incremented and decremented accordingly when lagging. At approximately phase coincidence, the up / down counter UDC is stopped. As approximate phase equality can apply in this sense, if the respective measured phase difference lies within a predetermined interval. A respective count ZS of the up / down counter UDC represents an accumulated phase correction information which describes a deviation of the first reference clock signal RT1 frequency-synchronous clock signal TO to the second reference clock signal RT2 and thus a deviation between the first and second reference clock signal.

The controller RE also comprises a phase controller PSS having a count register which is divided into a first register part LOG for high-order bits and a second register part LIN for low-order bits. The phase control PSS further includes a frequency divider T4, the clock signal TO of the oscillator VCXO is supplied before passing through the phase actuator PS. The divider factor TF of the frequency divider T4 is determined by the content of the register part LOG of the count register. The divided output frequency of the frequency divider T4 can thus within wide limits, z. B. typically be varied between 4 Hz and 4096 Hz. The clock signal TO divided by the frequency divider T4 predetermines a count clock ZT, with which the register part LIN of the count register is further counted.

As part of the control of the phase actuator PS of the count ZS of the up / down counter UDC is transmitted as Zählvorgabe in the counting register of the phase actuator control PSS. The higher-order bits of the counter reading ZS transferred into the register section LOG thus define a current divider factor TF, while a new start value for the count is specified with the lower-order bits of the counter reading ZS transmitted to the register section LIN. After the transmission of the counter reading ZS, the register part LIN is counted up to a predetermined counter mark in the rhythm of the counting clock ZT. Upon reaching this Zählmarke a control signal SS is formed by the phase control PSS, which is supplied to the phase actuator PS and there is an addition or insertion of a clock phase in the clock signal TO of the oscillator VCXO causes. Depending on a sign bit of the counter reading ZS, a decision is made as to whether a control signal for insertion or a control signal for removing a clock phase is formed. Further, upon reaching the predetermined count, the content of the count register is renewed by reloading a current count ZS from the up / down counter UDC, thus initiating a new count run of the count register.

In a second mode of operation of the circuit arrangement according to the invention, in which e.g. is switched automatically on failure of the first reference clock signal RT1, the clock signal TO is synchronized based on the second reference clock signal RT2 including the phase correction information ZS formed in the first mode. In this case, the synchronicity with the no longer used, first reference clock signal RT1 should remain as accurate as possible.

In the second mode is switched by switching the switching elements S1 and S2. With the switching element S1 to the output of the second phase comparator PV2 is separated from the up / down counter UDC and instead connected via a direction indicated by a dotted line connection with an input of the switching element S2. This input is coupled by switching the switching element S2 via the filter F to the frequency control input of the oscillator VCXO. By switching the switching element S2, the previous connection between the output of the phase comparator PV1 and the filter F is interrupted. As a result of the described switching of the switching elements S1 and S2, a second phase locked loop is formed, which comprises the oscillator VCXO, the phase control element PS, the second phase comparator PV2 and the filter F. The clock signal TO is thus synchronized on the basis of the second reference clock signal RT2.

After separation of the second phase comparator PV2 from the up / down counter UDC this is stopped. Be last count ZS remains stored as phase correction information and is used as in the first mode for reloading the count register of the phase actuator control PSS. The insertion or removal of clock phases is thus continued by the phase actuator control PSS in accordance with the last in the second mode, last count ZS the up / down counter UDC. The phase control in the second phase-locked loop is thereby corrected by the last detected deviation of the second reference clock signal RT2 from the first reference clock signal RT1, so that the clock signal TO remains synchronized with high accuracy to the no longer present first reference clock signal RT1.

FIG. 2 illustrates the change in the time profile of the clock signal TO caused by the phase control element being removed and inserted by clock phases. While the uppermost curve represents the time profile of a clock signal which is unchanged by the phase actuator PS, the middle curve shows a clock signal with a clock phase taken out and the lower curve a clock signal with an inserted clock phase.

In the present embodiment, the phase actuator PS is realized in a particularly simple manner with the aid of a 2-bit counter. This passes through the count stages 0,1,2 and 3 during one clock period of the clock signal TO. The output signal of the phase actuator PS is derived from the state of the high order bit of the 2-bit counter, i. during counts 0 and 1, the output is zero and during counts 2 and 3 is one. The respective counting stages of the counter are each indicated below the illustrated clock signal curves.

A clock phase is now issued by skipping a count stage of the 2-bit counter, on the initiative of the control signal SS. This jumps the phase of the following bars by 90 degrees forward. Analogously, a clock phase is inserted, by suppressing a count that would otherwise cause the 2-bit counter to continue counting so that the 2-bit counter is not counted until the next count. The phase of subsequent bars shifts by 90 degrees backwards.

Claims (12)

1. Circuit arrangement for producing a clock signal (TO) whose frequency is synchronous with that of reference clock signals (RT1, RT2), having

   a) an oscillator (VCXO) which forms the synchronous-frequency clock signal (TO) and whose clock frequency can be controlled via a frequency control input,

   b) a first phase comparison device (PV1) having a first input (E1) for coupling a first reference clock signal (RT1), a second input (E2), to which the clock signal (TO) from the oscillator (VCXO) is supplied, and an output which is routed to the frequency control input of the oscillator (VCXO), and

   c) a second phase comparison device (PV2) having a first input (E1) for coupling a second reference clock signal (RT2) and an output which can be coupled to the frequency control input of the oscillator (VCXO) via a switching element (S1) on the basis of operating mode,
   characterized by

   d) a phase control element (PS) for inserting and removing clock phases which is used to supply the clock signal (TO) from the oscillator (VCXO) to a second input (E2) of the second phase comparison device (PV2), with insertion and removal of clock phases being able to be controlled via a control input of the phase control element (PS), and

   e) a regulating device (RE) which can be connected to the output of the second phase comparison device (PV2) via a switching element (S1) on the basis of operating mode in order to form phase correction information (ZS) on the basis of the second phase comparison device's output signal and which is connected to the control input of the phase control element (PS) in order to control insertion and removal of clock phases on the basis of the phase correction information (ZS) formed.
2. Circuit arrangement according to claim 1,
   characterized
   in that the output of the first phase comparison device (PV1) is routed to the frequency control input of the oscillator (VCXO) via a switching element (S2) which can connect and isolate the output of the first phase comparison device (PV1) and the frequency control input of the oscillator (VCXO) on the basis of operating mode.
3. Circuit arrangement according to claim 1 or 2,
   characterized by
   a filter (F) connected upstream of the frequency control input of the oscillator (VCXO) for the purposes of integrating frequency control signals supplied to the oscillator (VCXO).
4. Circuit arrangement according to one of the preceding claims,
   characterized by
   a memory for storing the phase correction information (ZS) on the basis of operating mode.
5. Circuit arrangement according to one of the preceding claims,
   characterized
   in that a frequency divider (T1, T2, T3) is connected upstream of at least one input (E1, E2) of at least one phase comparison device (PV1, PV2).
6. Circuit arrangement according to one of the preceding claims,
   characterized
   in that an output of a detector device which indicates when the first reference clock signal (RT1) is present is connected to a switching element (S1, S2) for controlling the operating mode.
7. Circuit arrangement according to one of the preceding claims,
   characterized
   in that an output of a detector device which indicates when the second reference clock signal (RT2) is present is connected to an alarm transmitter for triggering an alarm signal when the second reference clock signal (RT2) is not present.
8. Circuit arrangement according to one of the preceding claims,
   characterized
   in that an output of a detector device which indicates when the clock signal (TO) from the oscillator (VCXO) is present is connected to an alarm transmitter for triggering an alarm signal when the clock signal (TO) is not present.
9. Circuit arrangement according to one of the preceding claims,
   characterized
   in that the regulating device (RE) has an up/down counter (UDC) whose counting direction is dependent on the output signal from the second phase comparison device (PV2) and whose counter reading (ZS) represents the phase correction information.
10. Circuit arrangement according to claim 9,
    characterized
    in that the regulating device (RE) has a phase control element controller (PSS) having a counting register (LOG, LIN) which can be loaded with the counter reading (ZS) from the up/down counter (UDC) as a counting preset and prompts insertion or removal of a clock phase in the phase control element (PS) when a prescribed counting marker is reached.
11. Circuit arrangement according to claim 10,
    characterized
    in that the counting register is split into a first register part (LOG) for more significant bits and a second register part (LIN) for less significant bits, and
    a counting frequency used to count through the second register part (LIN) is determined by the content of the first register part (LOG).
12. Circuit arrangement according to one of the preceding claims,
    characterized by
    a further phase control element, controlled by the regulating device (RE), for deriving a further synchronous-frequency clock signal from the second reference clock signal (RT2).

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