Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/02—Containers; Seals
  • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/52—Mounting semiconductor bodies in containers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/54—Providing fillings in containers, e.g. gas fillings
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/02—Containers; Seals
  • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
  • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• This present invention relates to the wafer-scale packaging of monolithically integrated sensors and actuators and of integrated circuits in general.
• Wafer scale packaging provides significant enhancements for manufacturing and has resulted in the introduction of many micromachined sensor components more difficult or impossible to produce with other techniques.
• Wafer scale packaging using a glass frit as the bonding medium requires temperatures not typically compatible with standard microelectronics processing for the bond process, and often involves frit materials containing elemental components deleterious to active circuitry. Even with the resolution of such limitations, neither performance nor area utilization is enhanced significantly if the wafer scale packaging requires unique bond areas.
• This present invention provides a semiconductor wafer-level package in which glass frit is formed directly in contact with the devices or active circuitry in the monolithic device. This could be embodied using wafer bond or by direct application of glass frit to the devices.
• This package may be used to encapsulate a monolithically-integrated sensor structure, to protect an integrated circuit from unwanted exposure to environmental or electromagnetic interactions, or to create wafer-scale protected integrated circuits and systems for flip-chip packaging applications.
• a preferred embodiment includes a cap wafer bonded to the semiconductor substrate, which may include integrated circuits and sensors. This bond is formed using a pattern of frit glass as a pattern such that any sealed volumes formed by the cap wafer, frit glass, and semiconductor substrate are hermetically sealed.
• Integrated circuits can exist beneath the frit glass seal.
• Another preferred embodiment includes direct application of a pattern of glass frit to a semiconductor substrate such that regions of the substrate are hermetically sealed.
• Integrated circuits (devices) can exist directly beneath the frit glass.
• Figure 1 shows a perspective cross-sectional view of a device encapsulated within a semiconductor wafer level package containing a cap wafer in accordance with a first preferred embodiment of the present invention.
• Figure 2 illustrates a perspective cross-sectional view of an encapsulated device excluding a cap wafer in accordance with a second preferred embodiment of the invention.
• the figures illustrate the general invention, and descriptions and details of well-known features and techniques are omitted to avoid excessive complexity.
• the figures are not necessarily drawn to scale, and the same reference numerals in different figures denote the same elements. It is further understood that the embodiments of the invention described herein are capable of being manufactured or operated in other orientations than described or illustrated herein.
• Figure 1 shows a cross sectional view of a device 12, which is encapsulated in a wafer scale package 21 in accordance with the present invention.
• a plurality of such devices together with external structures such as test devices and scribe channels will be fabricated as part of the total semiconductor wafer level package.
• external structures such as test devices and scribe channels
• the device 12 is fabricated on a semiconductor substrate wafer 11 , which comprises a wafer of semiconductor material before the wafer has been diced into a plurality of distinct chips.
• Device 12 may be any of the devices, which are commonly fabricated using the semiconductor wafer.
• the device 12 may be located in one or any of three regions in the package 21.
• the first location of a device 12a is inside a cavity 17 formed by the protective cap 16, the frit glass layer 14, and the substrate 11.
• a second location of a device 12b may be in a position beneath the frit glass 14 in which a sealing surface or the hermetic bond is formed with device 12b.
• a device 12c may be located outside the protective cap and will be exposed to external environments, electrical contacts, etc.
• the cap wafer which can be silicon, glass, metal, polymer, or the like, is provided which can be prepared by providing a plurality of holes, which extend completely through cap wafer. These holes, which are normally drilled or etched before bonding, may also be made after bonding.
• a frit glass is then typically deposited on the cap wafer by a silk screening method, which leads to a pattern aligned with the electrical patterns on the device wafer. Other methods of deposition may also be employed such as spin coating, spraying, direct write, etc.
• the preferred embodiment is to deposit slurry comprising a mixture of organic binder, solvent, and a frit glass containing filler, deposited through the silk screen. The combination is fired by heating to a high enough temperature to volatilize organic or inorganic materials.
• frit glass deposition Selection and use of the binder as well as the subsequent firing comprise methods well known in the art of frit glass deposition. Then frit glass itself is selected to allow bonding below the temperature at which aluminum forms an alloy with silicon, approximately 570 degrees Celsius, and more importantly, at a low enough temperature not affect the functionality of the electronic devices which may contain integration on the same chip, such as an IC device and sensor.
• Suitable glasses may be available from VIOX Corporation, Nippon Electric Glass America, Inc., Ferro Corporation, or others, but the practiced embodiment employs a glass, identified as VIOX Glass No. 24925, or VIOX Glass No. 24927 from VIOX Corporation.
• the cap wafer is bonded to semiconductor substrate wafer using a frit glass layer in direct contact with the electronic device, frit glass serving as the bonding agent. Process conditions are such that the integrated circuitry,
• the IC and which can include sensing elements, are compatible so as not to degrade the performance and functionality of the integrated electronic devices.
• the range of softening temperatures for the frit glass material is less than about 500 degrees C, preferably about 300 degrees C to about 475 degrees C.
• a preferred thickness of the frit glass layer is about 5 microns to about 4 mils, preferably about 5 microns to about 25 microns.
• Other glasses with lower bonding temperatures may be available, however, in which case it is understood that the glazing and bonding temperatures may be lowered.
• Cap wafer 16 is bonded to semiconductor substrate wafer 11 using frit glass 14 as a bonding agent. This bonding comprises heating the cap wafer 16, frit glass 14, and semiconductor substrate wafer 11. In this way semiconductor wafer level package 21 is formed as part of a capped wafer structure with device 12 hermetically sealed of predetermined dimensions formed by a combination of semiconductor substrate wafer 11 , cap wafer 16, and frit glass 14.
• Cap wafer 16 is formed from a material, which will form a suitable seal with the frit glass. Typical such materials are semiconductor wafers, such as silicon, ll-VI or lll-V compound semiconductors, quartz plates, alumina plates, certain metals, polymers, or the like. The material, which comprises cap wafer 16, may be selected to provide a desired thermal expansion characteristic.
• a silicon wafer used for cap wafer 16 will inherently have virtually identical thermal properties with a similar silicon wafer, which is used for semiconductor substrate wafer 11.
• the compatibility of the frit glass material of the invention provides a means to hermetically seal the device on the semiconductor substrate by directly contacting the frit glass material to the device 12 without damage or ill effects to the device.
• the low temperature frit glass material of the invention may also be used to form frit glass walls by predetermining the pattern of the frit glass material prior to depositing it on the surface of the cap wafer 16.
• a plurality of metal traces 19 may be fabricated on semiconductor substrate wafer 11 , prior to the formation of the frit glass layer 14. Metal traces 19 form a seal with the frit glass 14 as shown in Figure 1. Metal traces 19 form a plurality of electrodes on semiconductor substrate wafer 11 , which provide electrical coupling to device 12. Prior to frit glass application, holes may be etched in cap wafer 16 in locations which provide ready access to a portion of the electrodes formed by metal traces 19. A plurality of traces 19 is bonded to a plurality of pads formed on device 12 in the opening 18. Wires (not shown) extend through the opening 18 and are themselves coupled to external leads. Wires through opening 18, and metal traces 19 provide a simple, inexpensive method to provide a plurality of desired electrical couplings to device 12 while allowing portions or all of device 12 to remain hermetically sealed under the cap wafer 16.
• Cap wafer 16 and semiconductor substrate wafer 11 may be aligned optically by means of opening 18, and an appropriate alignment target formed on semiconductor substrate wafer 11. Alternatively a plurality of bonding pads formed as part of metal traces 19 are used for visual alignment.
• the capped wafer structure is then introduced into a controlled environment, which typically comprises an inert gas at a specified pressure such as helium, argon or nitrogen. While in the inert gas, cap wafer 16 and semiconductor substrate wafer 11 are heated to bond them together to form semiconductor wafer level package 21. The bonding hermetically seals the capped wafer structure.
• the controlled environment is possible which provides a predetermined damping action for mechanical motion of device 12. The predetermined damping action is readily controlled by altering the composition and pressure of the inert gas.
• the capped wafer structure is then diced into a plurality of composite chips by sawing, a method well known in the semiconductor art.
• the composite chips may then be further encapsulated, for example, within a plastic material or underfilled as is conventionally know in flip chip technology.
• the composite chips can also exist without further encapsulation.
• a second preferred embodiment of the package 21 does not contain a cap wafer and is illustrated in Figure 2.
• the package 21 is prepared as described except the step of forming a cap wafer is omitted.
• the frit glass is applied directly on the device and an opening is provided in the frit glass layer to provide access to the substrate of the wafer.
• a whole cap wafer or cap wafer containing cavities was selected and a glass paste pattern printed on a surface of the cap wafer by screen printing. It may be appreciated that any conventional patterning technique may be used, such as screen printing, spin coating, direct dispense writing, or photolithographic techniques.
• the frit glass paste was dried on the cap wafer in an oven set at 80 degrees C for 1 hour and for a second hour at 120 degrees C.
• the glass patterned wafers were removed from the drying oven and loaded into furnace boats.
• the wafers were glazed in a specified temperature program, i.e. 450 degree C temperature for at least 30 minutes. Temperature range example: min. 420 degrees C and max. 505 degrees C.
• the cap wafer was aligned to the device wafer in an Electronic Vision Model EV 450 Wafer Aligner in preparation for bonding of cap wafer to device wafer.
• the wafer was bonded in an Electronic Vision Model EV AB1 PV Wafer Bonder Single Chamber at 430 degrees C for 10 minutes. Wafers are typically bonded 20 to 30 degrees below the glazed wafer temperature.
• a whole device wafer or device wafer containing cavities or recesses was selected and a glass paste pattern printed on a surface of the wafer by screen printing. Any conventional patterning technique may be used, such as screen printing, spin coating, direct dispense writing, or photolithographic techniques.
• the frit glass paste was dried on the wafer in an oven set at 80 degrees C for 1 hour and for a second hour at 120 degrees C.
• the glass patterned wafers were removed from the drying oven and loaded into furnace boats.
• the wafers were glazed in a specified temperature program, i.e. 450 degree C temperature for at least 30 minutes to volatilize the organic binder. Temperature range example: about 420 degrees C and to 505 degrees C.
• the present invention provides packaging devices which are fabricated on a semiconductor wafer before that wafer is diced into individual chips.
• the packages contain a hermetic seal by means of frit glass on electronics having thermal characteristics which closely match those of the device.
• the package is inexpensive to manufacture and provides for electrical connections to the device without compromising the other characteristics of the package.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Chemical & Material Sciences (AREA)
• Ceramic Engineering (AREA)
• Micromachines (AREA)

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• 2000
  • 2000-09-15 EP EP00961925A patent/EP1216487A1/de not_active Ceased
  • 2000-09-15 AU AU73812/00A patent/AU7381200A/en not_active Abandoned
  • 2000-09-15 WO PCT/US2000/025315 patent/WO2001020671A1/en not_active Application Discontinuation

Non-Patent Citations (1)

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