EP1214738A1 - Method to fabricate a mosfet - Google Patents

Method to fabricate a mosfet

Info

Publication number
EP1214738A1
EP1214738A1 EP00957193A EP00957193A EP1214738A1 EP 1214738 A1 EP1214738 A1 EP 1214738A1 EP 00957193 A EP00957193 A EP 00957193A EP 00957193 A EP00957193 A EP 00957193A EP 1214738 A1 EP1214738 A1 EP 1214738A1
Authority
EP
European Patent Office
Prior art keywords
polysilicon
area
areas
well
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00957193A
Other languages
German (de)
French (fr)
Inventor
Ted Johansson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, Telefonaktiebolaget LM Ericsson AB filed Critical Infineon Technologies AG
Publication of EP1214738A1 publication Critical patent/EP1214738A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to silicon metal oxide field effect transistors and more exactly to a method using a minimum of mask steps for fabrication thereof.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • CMOS is the most common circuit type today, and consists of n-type devices (NMOS) and p-type devices (PMOS) integrated on a single die. Using these two device types, digital building blocks can be designed that will only draw current during the transition from one state to another and draw very little current between transitions. CMOS logic will therefore have lower power consumption that corresponding logic built in NMOS or PMOS only, and, although more complex to fabricate, has therefore become the preferred choice for large integrated circuits.
  • a generic MOS process flow consists of (at least) the following fabrication steps (from any advanced textbook on silicon process integration, also for example see S. M. Sze, Ed., VLSI Technology, McGraw-Hill, 1983, and S. Wolf, R. N. Tauber, Silicon Processing for the VLSI ERA, Lattice Press, Sunset Beach, 1986): 1. Start: Initial material is ⁇ 100> 10-20 ⁇ cm p-type silicon for NMOS.
  • LOCOS isolation is the most common, and consists of the following steps: pad oxide growth, silicon nitride deposition, LOCOS mask (# 1), LOCOS nitride etch, LOCOS oxidation, nitride etch, pad oxide etch, Kooi oxide growth, Kooi oxide etch.
  • Threshold voltage adjustment (ion implantation).
  • step 8 Polysilicon doping. Can be combined with step 8. 7. Gate mask (#2), gate etching.
  • Source/drain anneal
  • Metal mask (#4) metal etching.
  • a document U.S. Patent No. 5,899,719 discloses a narrow gate FET formed on a substrate by providing a first layer of polysilicon on the active device.
  • the method allows for gate electrodes to be formed that are narrower than the design rule characteristics of a particular lithography process by two times the width of the spacers formed within the openings in the first polysilicon layer. Since the width of the spacers is essentially determined by the thickness of the insulating layer from which the spacers are formed, the width of the gate electrode is controllable.
  • the document gives no hints of any method for further decreasing the number of masking steps in the process but relies on a standard method for instance as visualised above.
  • EP-A2-0 851 478 describes a CMOS process using grown field oxide for active area isolation taking advantage of process steps used in LDD (Lightly-Doped Drain) transistor fabrication to reduce the chip space occupied by the field oxide.
  • the fabrication thereby uses only a single critical mask to define a spacer oxide pattern conforming to the narrow field oxide pattern in both conductivity type wells of the device.
  • the process is said to enable use of a field oxide having a width being less than 2.5 times the gate width.
  • MOSFET transistors An extremely simple method to fabricate MOSFET transistors is described including enhancements of the basic concept.
  • a key idea is that two areas of polysilicon can be isolated from each other and used to isolate a third silicon area, if the areas of polysilicon are placed from each other at a distance corresponding to a width of two side wall spacers, and then in a common way an oxide or nitride spacer is formed.
  • CMOS inverter By means of the method described, a device can be manufactured for characterisation purposes with limited metallizing using only one mask layer. Using one additional mask, the method is extended for simple CMOS building blocks. To illustrate this, the layout of the simplest CMOS building block, the CMOS inverter, will be demonstrated.
  • a method according to the present invention is set forth by the independent claim 1 and the dependent claims 2 - 6. Further a MOSFET inverter device according to the present invention is set forth by the independent claim 7 and further embodiments are set forth by the dependent claims 8 to 10.
  • FIG. 1 shows an initial geometric form used in an embodiment of the method according to the present invention indicating two cross sections discussed
  • FIG. 2 shows a geometric form according to a second embodiment of the present method
  • FIG. 3a illustrates an inverter circuitry easily obtained by the present method
  • FIG. 3b illustrates the geometric form of an embodiment resulting in the inverter circuitry of FIG. 3a
  • FIG. 4 illustrates the geometric form of another embodiment resulting in the inverter circuitry of FIG. 3a;
  • FIG. 5 illustrates an initial step of implanting a p-type material
  • FIG. 6 illustrates a next step of forming a gate oxide on top of the doped p- type material
  • FIG. 7 illustrates the step depositing a polysilicon layer
  • FIG. 8 illustrates the result at cross section (a) of FIG. 1 after the step of etching the polysilicon using a photolithographic mask
  • FIG. 9 illustrates the result at cross section (b) of FIG. 1 after the step of etching the polysilicon using a photolithographic mask
  • FIG. 10 illustrates the result at cross section (a) after the steps of removal of gate oxide and adding spacers
  • FIG. 11 illustrates the result at cross section (b) after the steps of removal of gate oxide and adding spacers
  • FIG. 12 illustrates the result at cross section (a) after a standard SALICIDE process step using TiSte
  • FIG. 13 illustrates the result at cross section (b) after a standard SALICIDE process step using TiSb
  • FIG. 14 illustrates a flow chart of the present basic method utilising only one masking step.
  • Figure 1 illustrates an initial embodiment for disclosing the method according to the present invention.
  • the hatched areas indicate polysilicon areas applied by means of a first mask (#1) on top of a thin thermally grown oxide layer on a semiconductor substrate.
  • the substrate will be of a p-type material for N-type devices and n-type for a P-type device.
  • Two U-shaped opposite facing polysilicon areas 1, 2 enclose the n-well or p-well previously created in the semiconductor substrate. Between the two U-shaped opposite directed polysilicon areas 1 and 2 is inserted a third polysilicon area 5 forming a gate terminal.
  • Figure 1 is found two lines (a) and (b) defining two cross-sections which will be further discussed in Figures 8 - 13.
  • the cross-section (b) illustrates the narrow distances equal to the width of two side wall spacers between the two U-formed polysilicon areas 1, 2 and the third polysilicon area 5.
  • Figure 2 illustrates a second embodiment in accordance with Figure 1 demonstrating metallizing connections 8 for the source/ drain /gate areas forming terminals for a MOSFET transistor.
  • Figure 3(a) illustrates a simple inverter circuitry which can be very simple realised by means of the present method for creating MOS transistors.
  • Figure 3(b) illustrates a layout of the polysilicon areas in connection with a p-well and an n-well created in the substrate before depositing the thin oxide layer. In this case an extra initial mask step will be needed for creating the two types of wells.
  • Figure 4 illustrates a second embodiment of the inverter structure according to Figure 3(b).
  • the upper polysilicon area 3 in Figure 3(b) here has been divided into two portions 4 on each side of the third polysilicon area 5 intended for the common input gate terminal connection. Consequently an inverter stage can be manufactured using on two masking steps when utilising the method of the present invention.
  • Starting material is ⁇ 100> silicon.
  • N-type devices will be built in a p-type material, p-type in an n-type material. If only one type of devices will be needed, a single material can be used.
  • the resistivity of the material is selected to be in the range of 15-20 ⁇ C m.
  • an epi material is commonly used with a highly doped substrate and the medium doped layer on top of it.
  • Gate-oxidation ( Figure 6). A thin uniform oxide 9 is formed on the surface by thermal oxidation, which will be the gate oxide of the device. The thickness usually relates to the gate length and the supply voltage of the device and is for modern MOSFET devices (Leff ⁇ 0.2-0.5 ⁇ m and VDD-2-3 V) in the range of 50- 100 A.
  • MOSFET devices Leff ⁇ 0.2-0.5 ⁇ m and VDD-2-3 V
  • Polysilicon deposition (Figure 7). Typical thickness is 2000-4000 A using ⁇ 600°C which creates a uniform undoped polysilicon layer 10 which will serve as a gate material.
  • LDD Lightly-Doped Drain
  • the LDD reduces the maximum electrical field, which improves the breakdown voltage and reduces long-term degradation.
  • the LDD implant is typically a light-to- medium dose phosphorous implant, made prior to the spacer formation.
  • Spacer deposition Depositions of silicon nitride or silicon dioxide for use as side wall spacers 12. The thickness will be typically 3000-4000 A to leave a 2000 A spacer 12 on each side of the polysilicon.
  • nitride/ oxide and silicon The selectivity between nitride/ oxide and silicon is high and will etch away these materials on the silicon /polysilicon areas without removing more than -50 A of silicon.
  • Source /drain /gate implantation The gate, source and drains are doped using a P or an As (preferred) high-dose implant (5" 10 15 -2 10 16 cm -2 ) if fabricating n-devices or B or BF2 high-dose implant if fabricating p-devices.
  • a P or an As (preferred) high-dose implant 5" 10 15 -2 10 16 cm -2
  • the implanted dopants are diffused and electrically activated using a short temperature anneal using furnace anneal at 950°C for 30 minutes, or RTA, typically 1050°C for 30 seconds.
  • the obtained device is a MOSFET structure, fabricated only using ONE mask layer, and with silicide 14 as contacts.
  • a flow diagram of the basic method is demonstrated in Figure 14 defining the main steps performed on a standard p-well or n-well silicon material with a uniform layer of oxide applied according to the state of the art.
  • the present disclosed method provides the advantages to be extremely simple and fast to fabricate and compatible with standard CMOS technology, but saves valuable time and money for evaluation of new device concepts.
  • Metallizing and final passivation can be carried out using standard IC fabrication steps. One mask is required for first contact hole, one for the metal and one for the final passivation, in total three masks for the first metallizing layer. For each additional layer of metal + via hole required for connect, two more masks are needed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

An extremely simple method to fabricate MOSFET transistors is described including enhancements of the basic concept. A key idea is that two areas of polysilicon (1, 3) can be isolated from each other and used to isolate a third silicon area (5), if the areas of polysilicon are placed from each other at a distance corresponding to the width of two side wall spacers, and then in a common way oxide or nitride spacers are formed. By means of the method described, a device with limited metallizing is manufactured using only one mask layer. Using one additional mask, the method is extended for producing simple CMOS building blocks. As an illustration the layout of the most common CMOS building block, a CMOS inverter, is demonstrated.

Description

METHOD TO FABRICATE A MOSFET
TECHNICAL FIELD The present invention relates to silicon metal oxide field effect transistors and more exactly to a method using a minimum of mask steps for fabrication thereof.
BACKGROUND
The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the most common transistor type today. Virtually all large integrated circuits (microprocessors, memories, digital electronics etc.) are built by utilising silicon MOS technology.
When developing new processes and devices for ICs, most of the time is spent on fabrication, characterisation and modelling of single active devices of a few geometrical sizes, which devices later are connected together in millions to form any set of complex circuit functions.
CMOS is the most common circuit type today, and consists of n-type devices (NMOS) and p-type devices (PMOS) integrated on a single die. Using these two device types, digital building blocks can be designed that will only draw current during the transition from one state to another and draw very little current between transitions. CMOS logic will therefore have lower power consumption that corresponding logic built in NMOS or PMOS only, and, although more complex to fabricate, has therefore become the preferred choice for large integrated circuits.
A generic MOS process flow consists of (at least) the following fabrication steps (from any advanced textbook on silicon process integration, also for example see S. M. Sze, Ed., VLSI Technology, McGraw-Hill, 1983, and S. Wolf, R. N. Tauber, Silicon Processing for the VLSI ERA, Lattice Press, Sunset Beach, 1986): 1. Start: Initial material is < 100> 10-20 Ωcm p-type silicon for NMOS.
2. Device isolation. LOCOS isolation is the most common, and consists of the following steps: pad oxide growth, silicon nitride deposition, LOCOS mask (# 1), LOCOS nitride etch, LOCOS oxidation, nitride etch, pad oxide etch, Kooi oxide growth, Kooi oxide etch.
3. Threshold voltage adjustment (ion implantation).
4. Gate oxidation.
5. Polysilicon (gate material) deposition.
6. Polysilicon doping. Can be combined with step 8. 7. Gate mask (#2), gate etching.
8. Source/ drain implant.
9. Source/drain anneal.
10. Oxide deposition.
11. Contact hole mask (#3), etching of contact hole. 12. Metal deposition (Al) .
13. Metal mask (#4), metal etching.
14. Alloying of contacts, forming gas anneal.
Thus these 14 steps will include at least four different masks. Final passivation and bond pad etches still not being included in the process flow (at least another additional mask) .
A document U.S. Patent No. 5,899,719 discloses a narrow gate FET formed on a substrate by providing a first layer of polysilicon on the active device. The method allows for gate electrodes to be formed that are narrower than the design rule characteristics of a particular lithography process by two times the width of the spacers formed within the openings in the first polysilicon layer. Since the width of the spacers is essentially determined by the thickness of the insulating layer from which the spacers are formed, the width of the gate electrode is controllable. However the document gives no hints of any method for further decreasing the number of masking steps in the process but relies on a standard method for instance as visualised above. Another document EP-A2-0 851 478 describes a CMOS process using grown field oxide for active area isolation taking advantage of process steps used in LDD (Lightly-Doped Drain) transistor fabrication to reduce the chip space occupied by the field oxide. The fabrication thereby uses only a single critical mask to define a spacer oxide pattern conforming to the narrow field oxide pattern in both conductivity type wells of the device. The process is said to enable use of a field oxide having a width being less than 2.5 times the gate width.
Finally may be mentioned a document JP 61-032578 disclosing a procedure to prevent leakage by a parasitic transistor by forming a dummy gate pattern as a gate pattern not used as a wiring onto an isolation region. A space between the dummy gate pattern and the gate electrode is brought to approximately twice as long as the width of a side wall. This structure is however not used for manufacturing an active component.
In experimental environments, there is a need to fabricate simple MOS structures with few photo masks and a simplified process sequence, to evaluate new device ideas in a very short time and with reduced efforts. As demonstrated above a process flow for a single MOS transistor requires at least four mask layers including the metallizing: two for the device definition ("front-end") and two for connecting the device ("back end").
If, at least for evaluation purposes, a simplified fabrication flow could be used, much time and efforts during early process/ device development phases could be saved.
SUMMARY
An extremely simple method to fabricate MOSFET transistors is described including enhancements of the basic concept. A key idea is that two areas of polysilicon can be isolated from each other and used to isolate a third silicon area, if the areas of polysilicon are placed from each other at a distance corresponding to a width of two side wall spacers, and then in a common way an oxide or nitride spacer is formed.
By means of the method described, a device can be manufactured for characterisation purposes with limited metallizing using only one mask layer. Using one additional mask, the method is extended for simple CMOS building blocks. To illustrate this, the layout of the simplest CMOS building block, the CMOS inverter, will be demonstrated.
A method according to the present invention is set forth by the independent claim 1 and the dependent claims 2 - 6. Further a MOSFET inverter device according to the present invention is set forth by the independent claim 7 and further embodiments are set forth by the dependent claims 8 to 10.
BRIEF DESCRIPTION OF THE DRAWINGS The invention, together with further objects and advantages thereof, may best be understood by making reference to the following description taken together with the accompanying drawings, in which:
FIG. 1 shows an initial geometric form used in an embodiment of the method according to the present invention indicating two cross sections discussed;
FIG. 2 shows a geometric form according to a second embodiment of the present method;
FIG. 3a illustrates an inverter circuitry easily obtained by the present method;
FIG. 3b illustrates the geometric form of an embodiment resulting in the inverter circuitry of FIG. 3a; FIG. 4 illustrates the geometric form of another embodiment resulting in the inverter circuitry of FIG. 3a;
FIG. 5 illustrates an initial step of implanting a p-type material;
FIG. 6 illustrates a next step of forming a gate oxide on top of the doped p- type material;
FIG. 7 illustrates the step depositing a polysilicon layer;
FIG. 8 illustrates the result at cross section (a) of FIG. 1 after the step of etching the polysilicon using a photolithographic mask;
FIG. 9 illustrates the result at cross section (b) of FIG. 1 after the step of etching the polysilicon using a photolithographic mask;
FIG. 10 illustrates the result at cross section (a) after the steps of removal of gate oxide and adding spacers;
FIG. 11 illustrates the result at cross section (b) after the steps of removal of gate oxide and adding spacers;
FIG. 12 illustrates the result at cross section (a) after a standard SALICIDE process step using TiSte;
FIG. 13 illustrates the result at cross section (b) after a standard SALICIDE process step using TiSb; and
FIG. 14 illustrates a flow chart of the present basic method utilising only one masking step. DETAILED DESCRIPTION
An extremely simple method to fabricate MOSFET transistors is described including enhancements of the basic concept. The fabrication process of the structure is outlined in the flow process description below.
Figure 1 illustrates an initial embodiment for disclosing the method according to the present invention. The hatched areas indicate polysilicon areas applied by means of a first mask (#1) on top of a thin thermally grown oxide layer on a semiconductor substrate. The substrate will be of a p-type material for N-type devices and n-type for a P-type device. Two U-shaped opposite facing polysilicon areas 1, 2 enclose the n-well or p-well previously created in the semiconductor substrate. Between the two U-shaped opposite directed polysilicon areas 1 and 2 is inserted a third polysilicon area 5 forming a gate terminal. In Figure 1 is found two lines (a) and (b) defining two cross-sections which will be further discussed in Figures 8 - 13. The cross-section (b) illustrates the narrow distances equal to the width of two side wall spacers between the two U-formed polysilicon areas 1, 2 and the third polysilicon area 5. By means the utilising of the spacers the necessary following processing steps will be performed without the need of any further masking steps, which will be obvious from the description below.
Figure 2 illustrates a second embodiment in accordance with Figure 1 demonstrating metallizing connections 8 for the source/ drain /gate areas forming terminals for a MOSFET transistor.
Figure 3(a) illustrates a simple inverter circuitry which can be very simple realised by means of the present method for creating MOS transistors. Figure 3(b) illustrates a layout of the polysilicon areas in connection with a p-well and an n-well created in the substrate before depositing the thin oxide layer. In this case an extra initial mask step will be needed for creating the two types of wells. Figure 4 illustrates a second embodiment of the inverter structure according to Figure 3(b). The upper polysilicon area 3 in Figure 3(b) here has been divided into two portions 4 on each side of the third polysilicon area 5 intended for the common input gate terminal connection. Consequently an inverter stage can be manufactured using on two masking steps when utilising the method of the present invention.
A process flow will now be describes by means of the cross-section sketches illustrated in Figures 5 - 13. All manufacturing steps can use commonly known fabrication methods.
1. Start (Figure 5). Starting material is < 100> silicon. N-type devices will be built in a p-type material, p-type in an n-type material. If only one type of devices will be needed, a single material can be used. The resistivity of the material is selected to be in the range of 15-20 ΩCm. In this case, an epi material is commonly used with a highly doped substrate and the medium doped layer on top of it.
If both types of devices will be build on a single silicon die, standard well technology (p-well/ n-well/ twin-well etc.) is used to create separate p- and n- well regions. Depending on the selection of the starting material and the requirements on the device, one or two implantations to adjust the threshold voltage and to increase the punch-through resistance can be performed before executing the next step.
2. Gate-oxidation (Figure 6). A thin uniform oxide 9 is formed on the surface by thermal oxidation, which will be the gate oxide of the device. The thickness usually relates to the gate length and the supply voltage of the device and is for modern MOSFET devices (Leff~0.2-0.5 μm and VDD-2-3 V) in the range of 50- 100 A. WO 01/17009 PCT/SEOO/01607
3. Polysilicon deposition (Figure 7). Typical thickness is 2000-4000 A using ~600°C which creates a uniform undoped polysilicon layer 10 which will serve as a gate material.
4. Poly mask (Figures 8 and 9). Before etching the polysilicon pattern, a photolithographical step is performed. Photo resist is spun on the wafer, exposed and unexposed areas are washed away, leaving a pattern 11 shown in Figures 8 and 9 for a typical single device. The distance between two polysilicon islands ( 1 and 5 or 5 and 2) in Figure 9 must be selected equal to TWO spacer widths, as defined in step 6. The polysilicon layer will serve both as gate of the MOS transistors and isolating the source/ drains areas from the field regions of the semiconductor die.
5. Gate etch. Dry etching of the polysilicon is performed using reactive ion- etching (RIE). For the spacer formation/ etch, it is important that the etch profile is a vertical as possible. The etch has good selectivity to oxide and only a minor part of the gate oxide will be removed. The resist is stripped using dry and/ or wet methods.
6. LDD implantation. For a short channel transistor it is common to use Lightly-Doped Drain (LDD) technology, which grades the source/ drain junction close to the channel of the transistor. The LDD reduces the maximum electrical field, which improves the breakdown voltage and reduces long-term degradation. The LDD implant is typically a light-to- medium dose phosphorous implant, made prior to the spacer formation.
7. Spacer deposition. Depositions of silicon nitride or silicon dioxide for use as side wall spacers 12. The thickness will be typically 3000-4000 A to leave a 2000 A spacer 12 on each side of the polysilicon.
8. Spacer etch (Figures 10 and 11). In the next etch, the material for the spacer is dry etched using RIE. The etch is non-isotropic (mainly vertical) and leaves nitride/ oxide at the polysilicon edges with a characteristic form. WO 01/17009 " PCT/SEOO/01607
The selectivity between nitride/ oxide and silicon is high and will etch away these materials on the silicon /polysilicon areas without removing more than -50 A of silicon.
9. Source /drain /gate implantation. The gate, source and drains are doped using a P or an As (preferred) high-dose implant (5" 1015-2 1016 cm-2) if fabricating n-devices or B or BF2 high-dose implant if fabricating p-devices.
10. Activation. The implanted dopants are diffused and electrically activated using a short temperature anneal using furnace anneal at 950°C for 30 minutes, or RTA, typically 1050°C for 30 seconds.
1 1 - SALICIDE (Figures 12 and 13). To lower the sheet resistivity of the gate, source and drain areas, to contact the device in the case of no additional metallizing etc., the standard SALICIDE (self-aligned silicide) process sequence using e.g. TiSi2 in a two-step formation is then applied.
The obtained device is a MOSFET structure, fabricated only using ONE mask layer, and with silicide 14 as contacts. A flow diagram of the basic method is demonstrated in Figure 14 defining the main steps performed on a standard p-well or n-well silicon material with a uniform layer of oxide applied according to the state of the art.
It can, using only one additional mask, be enhanced to CMOS and is compatible with multi-layer metallizing schemes.
The present disclosed method provides the advantages to be extremely simple and fast to fabricate and compatible with standard CMOS technology, but saves valuable time and money for evaluation of new device concepts.
Since only one mask layer, does not require any alignment of photo masks. Can therefore be used with new photolithographical methods before alignment procedures have been developed. The present method can simply be extended to CMOS IC-technology. In order to obtain integrated CMOS circuits, one additional mask layer must be used. This mask defines the n-well/ p-well regions using twin-well technology. The same mask is also used if threshold voltage adjustments are needed, (see Step 1 of the description on page 7), and for the n+/p+ source/ drain/ gate implant if p+ blanket implantation can be accepted (also for example see L. C. Parillo et al, "Twin-tub CMOS - A Technology for VLSI Circuits", IEDM Tech. Dig. 1980, p. 752), otherwise two masks will be used.
In Figures 2 - 4 are indicated how a typical CMOS inverter can be made using one additional mask only. In order to connect the n+/p+ regions at the invert output on this level, a SALICIDE (Step 10) or metal interconnect layer must be used.
Metallizing and final passivation can be carried out using standard IC fabrication steps. One mask is required for first contact hole, one for the metal and one for the final passivation, in total three masks for the first metallizing layer. For each additional layer of metal + via hole required for connect, two more masks are needed.
It will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departure from the scope thereof, which is defined by the appended claims.

Claims

1. Method for a simplified fabrication of a metal oxide semiconductor device using a silicon material, characterised by the steps of growth of a uniform oxide layer (9); depositing polysilicon (10) on top of the uniform layer of oxide (9); forming by means of a first mask (11) first (1) and second (2) areas of polysilicon creating separate polysilicon areas on top of the oxide and forming a third area (5) of polysilicon on top of the oxide in relation to the first and second areas of polysilicon, thereby placing the first (1) and third (5) areas of polysilicon as well as the second (2) and third (5) areas of polysilicon at a distance from each other corresponding to a width of two side wall spacers (12), utilising the first, second and third areas of polysilicon in a first dry etching process of the silicon material thereby performing a gate etch; forming standard oxide or nitride spacers (12) at the steep sides of the first (1), second (2) and third (5) areas of polysilicon by deposition of silicon dioxide or silicon nitride and anisotropical etching in a second dry etching process thereby preparing for a source /drain /gate standard implantation and activation process; application of a standard SALICIDE process sequence thereby producing a metal oxide semiconductor structure with silicide (14) as contacts and using only one mask step.
2. The method according to claim 1, characterised by the further step of including as an initialising step for said silicon material an extra mask for defining n-well/ p-well regions to thereby fabricate a CMOS device.
3. The method according to claim 1 or 2, characterised by the further step of applying reactive ion etching for said first and second dry etching process.
4. The method according to claim 1 or 2, characterised by the further step of utilising P or As high dose implant when fabricating n-devices, or B alternatively BF2 high dose implant when fabricating p-devices.
5. The method according to claim 1 or 2, characterised by the further step of electrically activating the implanted dopants by using a short temperature anneal using furnace anneal at about 950°C for 30 minutes or RTA, typically at 1050°C for 30 seconds.
6. The method according to claim 1 or 2, characterised by the further step of using TiSi2 in a two-step formation in the standard SALICIDE process.
7. A metal oxide semiconductor device forming an inverter fabricated by using only two mask steps characterised in a first n-well area and a second p-well area, respectively formed by means a first mask, a first (1) and a second (2) and a third area (5) of polysilicon (10) on top of an oxide layer (9) by means of a second mask, whereby the first area (1) and the third area (5) of polysilicon as well as the second area (2) and the third (5) area of polysilicon are at a distance from each other corresponding to a width of two side wall spacers of silicon dioxide or silicon nitride; the device forming n-type channel and p-type channel CMOS devices in series having a common gate input electrode and a common output terminal representing series connected drain and source electrodes of the n-type and p-type channel CMOS devices.
8. The device according to claim 7, characterised in that the third area (5) of polysilicon forms the common gate input electrode terminal.
9. The device according to claim 8, characterised in that a second area
(3) of polysilicon has the shape of an E separating the n-well area from the p- well area thereby separating source and drain regions in the CMOS device.
10. The device according to claim 8, characterised in that the second area of polysilicon further is divided into two portions (4) one of for each one of the n-well and the p-well areas for forming direct contacts for separate source and drain regions in the CMOS device, whereby the third area (5) of polysilicon forming said common gate input terminal also separates the n- well and the p-well areas into separate areas for ground and supply voltage connections, respectively.
EP00957193A 1999-09-01 2000-08-23 Method to fabricate a mosfet Withdrawn EP1214738A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9903081 1999-09-01
SE9903081A SE517452C2 (en) 1999-09-01 1999-09-01 Metal oxide semiconductor device and method for its manufacture
PCT/SE2000/001607 WO2001017009A1 (en) 1999-09-01 2000-08-23 Method to fabricate a mosfet

Publications (1)

Publication Number Publication Date
EP1214738A1 true EP1214738A1 (en) 2002-06-19

Family

ID=20416816

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00957193A Withdrawn EP1214738A1 (en) 1999-09-01 2000-08-23 Method to fabricate a mosfet

Country Status (10)

Country Link
EP (1) EP1214738A1 (en)
JP (1) JP2003508910A (en)
KR (1) KR20020027615A (en)
CN (1) CN1206710C (en)
AU (1) AU6884600A (en)
CA (1) CA2384004A1 (en)
HK (1) HK1052253B (en)
SE (1) SE517452C2 (en)
TW (1) TW447132B (en)
WO (1) WO2001017009A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101456454B1 (en) 2008-06-25 2014-11-03 주성엔지니어링(주) Semiconductor device and method of manufacturing the same
CN101789401B (en) * 2009-01-23 2011-10-05 中芯国际集成电路制造(上海)有限公司 CMOS (Complementary Metal-Oxide-Semiconductor Transistor) and manufacture method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5911114A (en) * 1997-03-21 1999-06-08 National Semiconductor Corporation Method of simultaneous formation of salicide and local interconnects in an integrated circuit structure
US5897348A (en) * 1998-03-13 1999-04-27 Texas Instruments - Acer Incorporated Low mask count self-aligned silicided CMOS transistors with a high electrostatic discharge resistance

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KOKUBUN K ET AL: "NEW EMBEDDED DRAM TECHNOLOGY USING SELF-ALIGNED SALICIDE BLOCK (SSB) PROCESS FOR 0.18UM SOC (SYSTEM ON A CHIP)", SYMPOSIUM ON VLSI TECHNOLOGY. DIGEST OF TECHNICAL PAPERS. KYOTO, JAPAN, JUNE 14 - 16, 1999, June 1999 (1999-06-01), NEW YORK, NY : IEEE, US, pages 155 - 156, XP000894556 *

Also Published As

Publication number Publication date
KR20020027615A (en) 2002-04-13
CN1387677A (en) 2002-12-25
SE9903081L (en) 2001-03-02
CA2384004A1 (en) 2001-03-08
SE517452C2 (en) 2002-06-04
SE9903081D0 (en) 1999-09-01
AU6884600A (en) 2001-03-26
WO2001017009A1 (en) 2001-03-08
HK1052253A1 (en) 2003-09-05
CN1206710C (en) 2005-06-15
JP2003508910A (en) 2003-03-04
HK1052253B (en) 2006-01-27
TW447132B (en) 2001-07-21

Similar Documents

Publication Publication Date Title
US4701423A (en) Totally self-aligned CMOS process
US4319395A (en) Method of making self-aligned device
US5573963A (en) Method of forming self-aligned twin tub CMOS devices
US5665993A (en) Integrated circuit including a FET device and Schottky diode
US7053465B2 (en) Semiconductor varactor with reduced parasitic resistance
US6083780A (en) Semiconductor device and method of fabrication thereof
US5294822A (en) Polycide local interconnect method and structure
EP0450375B1 (en) Interconnect and method of manufacture for semiconductor devices
EP0135243B1 (en) A method of producing a semiconductor structure on a substrate and a semiconductor device manufactured thereby
US20010000245A1 (en) Structure and method for gated lateral bipolar transistors
US5332913A (en) Buried interconnect structure for semiconductor devices
EP1479101A2 (en) Integrated circuit having interconnect to a substrate and method therefor
US5045493A (en) Semiconductor device and method of manufacturing the same
US6372590B1 (en) Method for making transistor having reduced series resistance
KR100271265B1 (en) Self-aligned pocl3 process flow for submicron microelectronics applications using amorphized polysilicon
US6657263B2 (en) MOS transistors having dual gates and self-aligned interconnect contact windows
KR100234549B1 (en) Low resistance silicided substrate contact
US5759881A (en) Low cost well process
EP1214738A1 (en) Method to fabricate a mosfet
JP2718257B2 (en) Reduction of buried layer capacitance in integrated circuits.
US20020076885A1 (en) Low resistance complementary metal oxide (CMOS) transistor and method
JPH1098186A (en) Semiconductor device and manufacturing method thereof
JPH11238807A (en) Semiconductor integrated circuit device
US6093595A (en) Method of forming source and drain regions in complementary MOS transistors
JPH07254645A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20020402

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

17Q First examination report despatched

Effective date: 20061211

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20090303