EP1212691A2 - Rechnergestütztes verfahren zur parallelen berechnung des arbeitspunktes elektrischer schaltungen - Google Patents
Rechnergestütztes verfahren zur parallelen berechnung des arbeitspunktes elektrischer schaltungenInfo
- Publication number
- EP1212691A2 EP1212691A2 EP00943652A EP00943652A EP1212691A2 EP 1212691 A2 EP1212691 A2 EP 1212691A2 EP 00943652 A EP00943652 A EP 00943652A EP 00943652 A EP00943652 A EP 00943652A EP 1212691 A2 EP1212691 A2 EP 1212691A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- computer
- circuit
- node
- operating point
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Definitions
- WO 98/24039 therefore proposes a large one
- Partition circuit and have the partitions processed by different computers.
- the working point ie the potentials of all nodes, is determined as the basis for further analyzes, such as transient or alternating current analyzes.
- the charging process such as m H. Spiro: “Simulation of integrated circuits” (2nd edition, R. Oldenbourg Verlag Kunststoff, Vienna 1990), describes the dynamic elements present in an electrical circuit, such as capacitances and / or inductances used to calculate the operating point using a pseudo-transient analysis.
- the dynamic elements are gradually increased, starting from a value of zero, to a value that is in principle arbitrarily high, in particular to the value “1”.
- dynamic elements such as capacitors or inductors
- predetermined known values can additionally be installed at suitable points, for example at or between a plurality of nodes. In this way, difficulties in the calculation due to an insufficient number of dynamic elements can be avoided.
- the additional dynamic elements introduced into the circuit can be gradually reduced to zero from an initial value, for example towards infinity, for which the operating point calculation is trivial, so that the original circuit is again simulated.
- at least one node, ie a connection point of at least two current paths, of the circuit is connected by means of a capacitance with a predetermined value with a predetermined potential.
- a capacitance can also be connected to each node via all partitions, the second connection of which is in each case connected to a predetermined potential, for example to ground.
- This procedure has the advantage that the operating point, that is, the respective potentials of the individual nodes, for an initial value for the capacities going towards infinity, can be trivially calculated for the circuit, based on a solution of the then explicit equation.
- the circuit simulation can be changed by suitably selecting the value for the capacities until a calculation of the operating point of the circuit for a value of the capacities towards zero or almost towards zero results.
- This implementation of the charging method also for parallel calculation of an electrical circuit, advantageously allows a very large circuit with a large number of transistors to be calculated quickly and easily, even with a smaller number of dynamic elements.
- Various approaches are conceivable for the respective redefinition of the value for the capacity with the aim of letting it go to zero, the decision criterion being the degree of difficulty in calculating the operating point of the respective previous step.
- the operating point which is obtained by solving a non-linear equation for a specific value of the capacities, can be solved iteratively using the Newton method, for example. For the selection of the next value for "C” Then the number of iteration steps necessary for the solution can be used until a predetermined value for "C" is undershot.
- starting point 1 is a simulation of an electrical circuit, for example in the circuit description language SPICE. This is partitioned in a first processing 2, as described, for example, in WO 98/24039 as the "clustering method", so that individual partitions or parts of the circuits, which are as calculable as possible with the same degree of difficulty, result.
- an earthed capacitance is now added to each node of the circuit, that is to say a connection point of at least two conductors or current paths.
- a capacitance the second connection of which is at a predetermined potential, both potentials and the values for the capacities of each node being different. can differentiate.
- the capacitance of the second connection is at the same potential, for example mass, and an identical high value CO is selected for all capacities in step 4 in step 4.
- the operating point is now calculated in a further step 6 for each partition or subcircuit, the required coupling values, i.e. the values for the coupling points or interfaces of adjacent partitions, being exchanged and included in the calculation of the operating points of adjacent partitions.
- Partition which is referred to below as "master", take control of the charging process.
- the master determines the initial value CO for the capacities, it also being conceivable to specify the initial value externally, for example by the user.
- This value CO is then transferred to all other partitions, hereinafter referred to as slaves.
- the operating point is subsequently calculated both in the master partition and in all slave partitions, the full source vector, which represents the energy sources present in the circuit, of course being present on the circuit.
- D day (C, ... C, 0, ..., 0) and t denotes the time.
- the corrected values s * +1 are calculated by the slaves or slave partitions in each iteration step of the master and communicated to the master.
- the non-linear system of equations must be used by the slaves
- the results of the slaves are then used in the master's equation system, whereupon the master can calculate the expression m n + x .
- a new value "C ne j" for "C” is determined by the master, whereby the slaves can also make suggestions.
- the choice of the new value "C re “ for "C” depends on the Difficulty in calculating the previous step with the value "C a ⁇ -" for "C".
- N is the number of iterations of the master and "n”, "n_" are parameters specified by the user. Instead of halving or doubling of "C a -" other strategies for reduction or enlargement of "C a ⁇ -" are self-evident ⁇ possible. In addition, the number of iteration steps required by the slaves or slave partitions to solve their non-narean equation system can also be taken into account, for example by selecting
- n_ siave denotes the number of iteration steps of the slave j, during the lth iteration of the master. It should be noted here that the choice of a value for "C” only influences the efficiency of the process and not the operating point itself.
- the calculation at branch 5 is terminated, with the value for C being able to be set to "0" in a last step.
- the result 8 is the working point of the original circuit and can be output via output units, such as a screen, printer or the like, and / or can be buffered in a memory as the basis for further analysis of the circuit.
- an operating point of a very large electrical circuit can advantageously be calculated in parallel by a large number of computers or processors, the disadvantage of known parallel calculation types, namely the lack of convergence in the case of unfavorable initial values, being avoided.
- the effort for the calculation in terms of iteration steps and step by step Setting a value for "C" is kept in a reasonable frame by the parallel calculation due to the distribution over several processors.
- the working point calculated in this way then serves as the basis for further analyzes, for example the AC analysis of a circuit.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
- Complex Calculations (AREA)
- Supply And Distribution Of Alternating Current (AREA)
- Multi Processors (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19927301 | 1999-06-15 | ||
| DE19927301 | 1999-06-15 | ||
| PCT/DE2000/001754 WO2000077658A2 (de) | 1999-06-15 | 2000-05-30 | Rechnergestütztes verfahren zur parallelen berechnung des arbeitspunktes elektrischer schaltungen |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP1212691A2 true EP1212691A2 (de) | 2002-06-12 |
| EP1212691B1 EP1212691B1 (de) | 2003-08-06 |
Family
ID=7911328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP00943652A Expired - Lifetime EP1212691B1 (de) | 1999-06-15 | 2000-05-30 | Rechnergestütztes verfahren zur parallelen berechnung des arbeitspunktes elektrischer schaltungen |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7024648B1 (de) |
| EP (1) | EP1212691B1 (de) |
| DE (1) | DE50003214D1 (de) |
| WO (1) | WO2000077658A2 (de) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI476616B (zh) * | 2010-02-12 | 2015-03-11 | Synopsys Shanghai Co Ltd | Estimation Method and Device of Initial Value for Simulation of DC Working Point |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5181179A (en) * | 1990-07-25 | 1993-01-19 | At&T Bell Laboratories | Artificial parameter homotopy methods for the dc operating point problem |
| US5467291A (en) * | 1991-09-09 | 1995-11-14 | Hewlett-Packard Company | Measurement-based system for modeling and simulation of active semiconductor devices over an extended operating frequency range |
| US7047162B1 (en) | 1996-11-18 | 2006-05-16 | Siemens Aktiengesellschaft | Computer assisted method for partitioning an electric circuit |
| US5930153A (en) * | 1997-04-30 | 1999-07-27 | Lucent Technologies, Inc. | Systems and methods for testing and manufacturing large-scale, transistor-based, nonlinear circuits |
| EP0986015B1 (de) * | 1998-09-09 | 2003-11-26 | STMicroelectronics S.r.l. | Verfahren zur Dynamischen Elektrischen Simulation von VLSI Schaltungen |
| US6490546B1 (en) * | 1999-05-04 | 2002-12-03 | International Business Machines Corporation | Method for obtaining DC convergence for SOI FET models in a circuit simulation program |
| US6530065B1 (en) * | 2000-03-14 | 2003-03-04 | Transim Technology Corporation | Client-server simulator, such as an electrical circuit simulator provided by a web server over the internet |
-
2000
- 2000-05-30 WO PCT/DE2000/001754 patent/WO2000077658A2/de not_active Ceased
- 2000-05-30 US US10/009,979 patent/US7024648B1/en not_active Expired - Fee Related
- 2000-05-30 EP EP00943652A patent/EP1212691B1/de not_active Expired - Lifetime
- 2000-05-30 DE DE50003214T patent/DE50003214D1/de not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| See references of WO0077658A2 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US7024648B1 (en) | 2006-04-04 |
| WO2000077658A2 (de) | 2000-12-21 |
| DE50003214D1 (de) | 2003-09-11 |
| WO2000077658A3 (de) | 2002-02-28 |
| EP1212691B1 (de) | 2003-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE3689538T2 (de) | Integrierte Schaltung und Optimierungsverfahren dafür. | |
| DE69225527T2 (de) | Verfahren und System zur automatischen Bestimmung der logischen Funktion einer Schaltung | |
| DE69324534T2 (de) | Gerät zur Berechnung der Leistungsaufnahme eines aus MOS-Transistoren zusammengesetzten Logik-Funktionsblocks | |
| DE102017113594A1 (de) | Computerimplementiertes Verfahren zur Simulation einer elektrischen Gesamtschaltung | |
| EP4068138B1 (de) | Verfahren zur aufteilung von simulationsmodellen zwischen einem prozessor und einem fpga | |
| DE102014118932A1 (de) | Charakterisierung einer Zelle unter Verwendung einer Eingangswellenerzeugung unter Berücksichtigung verschiedener Schaltungstopologien | |
| EP2145372B1 (de) | Verfahren und vorrichtung zur bestimmung des lastflusses in einem elektrischen versorgungsnetz | |
| DE102019130971A1 (de) | Computerimplementiertes Verfahren zur Simulation einer elektrischen Schaltung | |
| EP1062604B1 (de) | Verfahren und vorrichtung zur ermittlung einer störung eines technischen systems | |
| DE3854636T2 (de) | Automatischer Prüfprozess für logische Geräte. | |
| DE102012016610B4 (de) | Echtzeit-Schaltungssimulation | |
| DE19626984C1 (de) | Verfahren zur rechnergestützten Ermittlung einer Systemzusammenhangsfunktion | |
| EP1212691B1 (de) | Rechnergestütztes verfahren zur parallelen berechnung des arbeitspunktes elektrischer schaltungen | |
| EP0938716B1 (de) | Rechnergestütztes verfahren zur partitionierung einer elektrischen schaltung | |
| EP1257904B1 (de) | Verfahren zum erzeugen einer folge von zufallszahlen eines 1/f-rauschens | |
| EP1008075B1 (de) | Rechnergestütztes verfahren zur partitionierung einer elektrischen schaltung | |
| DE112023001319T5 (de) | Rauschanalysevorrichtung, Rauschanalyseverfahren und Programm | |
| DE19710463C2 (de) | Verfahren zur automatischen Differentiation auf einem Rechner insbesondere zur Simulation elektronischer Schaltungen | |
| WO2021185762A1 (de) | VERFAHREN UND VORRICHTUNG ZUR BESTIMMUNG EINER SENSITIVITÄT EINER KENNGRÖßE EINER ELEKTRONISCHEN SCHALTUNG | |
| DE69120522T2 (de) | LOGIK-SYNTHESE mit Analyse des kritischen Pfads | |
| DE10231304A1 (de) | Verfahren und Vorrichtung zur Berechnung der elektromagnetischen Feldintensität | |
| EP4478239A1 (de) | Emulation einer analogen schaltung mittels programmierbarer digitaler logik | |
| DE102024118150A1 (de) | Computerimplementiertes Verfahren zum Test eines elektronischen Steuergerätes mit einem Simulator und entsprechender Simulator | |
| DE112022005581T5 (de) | Definition einer analogen informationsmodell-objektklasse | |
| EP4506867A1 (de) | Verfahren und vorrichtung zum computerimplementierten verarbeiten einer quantenschaltung auf einer quantenverarbeitungseinheit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| 17P | Request for examination filed |
Effective date: 20011205 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB |
|
| AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
| RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: INFINEON TECHNOLOGIES AG |
|
| R17D | Deferred search report published (corrected) |
Effective date: 20020228 |
|
| 17Q | First examination report despatched |
Effective date: 20020724 |
|
| GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
| RIC1 | Information provided on ipc code assigned before grant |
Free format text: 7G 06F 17/50 A |
|
| GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
| GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
| AK | Designated contracting states |
Designated state(s): DE FR GB |
|
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
| REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: GERMAN |
|
| REF | Corresponds to: |
Ref document number: 50003214 Country of ref document: DE Date of ref document: 20030911 Kind code of ref document: P |
|
| GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20031117 |
|
| LTIE | Lt: invalidation of european patent or patent extension |
Effective date: 20030806 |
|
| REG | Reference to a national code |
Ref country code: IE Ref legal event code: FD4D |
|
| ET | Fr: translation filed | ||
| PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
| 26N | No opposition filed |
Effective date: 20040507 |
|
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20100916 AND 20100922 |
|
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20110804 AND 20110810 |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: TP Owner name: QIMONDA AG,, DE Effective date: 20120123 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20140619 Year of fee payment: 15 |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 16 |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R081 Ref document number: 50003214 Country of ref document: DE Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE Ref country code: DE Ref legal event code: R081 Ref document number: 50003214 Country of ref document: DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20150521 Year of fee payment: 16 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20150521 Year of fee payment: 16 |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R081 Ref document number: 50003214 Country of ref document: DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE |
|
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20151015 AND 20151021 |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 50003214 Country of ref document: DE |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: TP Owner name: INFINEON TECHNOLOGIES AG, DE Effective date: 20160212 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20151201 |
|
| GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20160530 |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST Effective date: 20170131 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20160531 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20160530 |