Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/01—Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
  • G01R31/2836—Fault-finding or characterising
  • G01R31/2846—Fault-finding or characterising using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/316—Testing of analog circuits
  • G01R31/3163—Functional testing

Definitions

• the present disclosure relates to a method for testing circuits. More particularly, the disclosure relates to a method of testing circuits having analog components, and a method of developing the tests applied to them.
• Test methodologies for mixed-signal systems are based primarily on the paradigm of measuring the circuit's specifications to determine if they are "good” or “bad”. This method is known as specification based testing. With this method of testing, each specification is measured for each circuit, e.g., an integrated circuit (IC), to ensure that the circuit satisfies all specified parameters. Specification based testing has many drawbacks. Foremost perhaps is the cost associated with such testing. Testing costs include both the cost of test development as well as the costs associated with conducting the actual manufacturing tests. The cost factor becomes critical in high volume production of analog and mixed-signal ICs.
• the present disclosure relates to a method for testing a circuit having analog components.
• the method comprises performing a low-cost optimized test on the circuit by applying an optimized input stimulus to the circuit, capturing the circuit response to the input stimulus applied to the circuit, evaluating the circuit response to predict whether the performance parameters of the circuit satisfies predetermined specifications for the circuit, and making a pass/fail determination for the circuit based upon the evaluation of the circuit response.
• the method deriving synthesizing functions which map measurement responses of the circuit to circuit performance parameters, applying an optimized input stimulus to the circuit, capturing the circuit response to the input stimulus applied to the circuit, evaluating the circuit response with respect to the derived synthesizing functions to predict whether a predeterrnined number of performance parameters of the circuit satisfies predetermined specifications for the circuit, making a pass/fail determination for the circuit based upon the evaluation of the circuit response, and for circuits for which a clear pass/fail determination cannot be made, perfo ⁇ r-ing specification based tests with respect to particular predetermined circuit specifications to make a final pass/fail determination for the circuit.
• FIG. 1 is a high level flow diagram of a testing methodology in accordance with the present invention.
• FIG. 2 is a flow diagram detailing a first portion of the testing methodology shown in FIG. 1.
• FIG. 3 is a schematic representation of various parameter spaces.
• FIG. 4 is a flow diagram detailing the first portion of the testing methodology shown in FIG. 2.
• FIG. 5 is a schematic view of mapping between parameter spaces.
• FIG. 6 is a flow diagram of an example test flow.
• FIG. 7 is a flow diagram of generation of critical circuit instances.
• FIG. 8 is a is a schematic of a routine showing steps involved in synthesizing mapping functions.
• FIG. 9 is a graphical representation of standard deviation of measurements.
• FIG. 10 is a schematic representation of string encoding.
• FIG. 11 is a schematic representation of use of uniform crossover to create child strings.
• FIG. 1 illustrates a high level view of a testing methodology in accordance with the present invention.
• the final test procedure can be divided into two stages. As shown in FIG. 1, the circuit under test
• CUT CUT is first subjected to a set of low-cost optimized tests derived from the CUT's specifications, as indicated in block 10. These tests can be conducted by applying an input stimulus (described below) to the circuit and observing the response, e.g. in the form of a waveform, to determine whether the circuit operates in compliance with a majority of the specifications established for the circuit. Once these tests have been performed, the test results are evaluated, as shown in block 12, to determine whether the CUT passes with respect to the various predetermined specifications. At this point, it can be determined, at least with respect to some circuits, whether the circuit passes (is good) or fails (is bad).
• the low-cost optimized tests which are the subject of the present disclosure may reject circuits that actually pass each designated specification or accept circuits which do not pass each designated specification. Therefore, at 14, some circuits may fall into a third category in which it is not clear from the optimized tests whether the circuit passes or fails.
• critical specification based tests can be applied in a second stage with respect to particular predete ⁇ nined specifications in the conventional manner, as indicated in block 16, to ensure that each approved circuit complies with each specification. Determination of which specifications for a given circuit will be specification based tested can be made by, for instance, initially comparing the test results obtained for each specification with the low-cost optimized tests with conventional test results for each specification. In this manner, the accuracy of the low-cost optimized tests can be assessed on a specification-
• the overall test process can comprise first applying the low-cost optimized tests to the CUTs, and then applying critical specification based tests to circuits which do not clearly pass or fail with respect to certain predete ⁇ riined circuit specifications to make a final "good” or "bad” determination.
• the overall test cost is significantly smaller as compared to what would be incurred by applying specification based tests to every circuit with respect to each circuit specification.
• FIG. 2 illustrates the first portion of the test method in greater detail. More particularly, this figure shows various steps involved in blocks 10 and 12 of FIG. 1. As shown in FIG. 2, the input stimulus is first applied to the circuit as indicated in block 20.
• the output response of the circuit can be captured (block 22) and, if desired, stored. From this response, the circuit specifications can be predicted, as indicated in block 24, so that pass/fail determinations can be made with regard to the predetermined specifications, as indicated in block 26.
• the performance of a circuit is determined by a set of associated process parameters, i.e., the parameters under which the circuit is constructed.
• process parameters i.e., the parameters under which the circuit is constructed.
• such parameters can include the temperatures used during fabrication, the chemical compositions used, etc.
• n p is the total number of process parameters which affect the circuit performance.
• a circuit fabricated in this process can be represented by a point in the n p dimensional process parameter space.
• the design of an analog circuit is evaluated using various performance parameters which reflect the circuit's transient, frequency, and DC performance metrices.
• these performance parameters correspond to the specifications to which the circuit operates.
• a circuit can also be represented by a point in the n s dimensional performance parameter space.
• the performance parameters of the circuit are to satisfy certain specifications which arc given by lower and/or upper bounds on the performance parameters.
• the specifications with a single bound can be designated as single ended specifications and those with both upper as well as lower bounds can be designated as double ended specifications.
• all the double ended specifications on the CUT can be decomposed into two single ended specifications, giving a total of /./, single ended specifications (the subscript b standing for bound).
• the lower or upper bound of the /' ' single ended specification can be denoted as b,.
• the " single ended specification (on the performance parameter sj) defines a region . . ,,, in the n s dimensional performance parameter space containing all performance parameter values satisfying
• Performance parameter sets satisfying all the ⁇ % single ended specifications fo ⁇ n the acceptance region in the performance parameter space (As) are defined by
• circuits with perfonuance parameters lying in this region are classified as fault free or good circuits while circuits with perfonnance parameters outside this acceptance region are faulty or bad circuits. Since the performance parameter space and the process parameter space are related by the mappings given in equation [l], the acceptance region in the performance parameter space is implicitly related to the acceptance region in the process parameter space (A p ) as defined by equations [4] and [5].
• Every circuit instance within the acceptance region in the process parameter space can be mapped into the measurement space using the mappings of equation [6] to give an acceptance region in the measurement space (A, tone) defined by equations [7] and [8].
• the functional mappings ⁇ andf r , lie are, in general, not available in closed form and these mappings are evaluated for a given p via numerical circuit simulation. According to rigorous mathematical definitions, the dimensions of the above mentioned spaces are equal to n p , n s , and /.,,- conditional on the linear independence of the process parameters, performance parameters, and measurements respectively. From the above discussion, it can be appreciated that the manufacturing parameters, performance parameters, and testing responses of a given circuit can be defined in terms of process parameter space, performance parameter space, and measurement space, and further that each of these spaces are related to each other.
• an input stimulus can be created which, when applied to a CUT manufactured with an incorrect process parameter, will yield a change in the measurement space which can be observed so that the defective nature of the circuit can be readily identified.
• one goal of the present method is to design tests which maximize the change in the measured response of the circuit so that defective circuits can more readily be identified.
• the response can be used to predict compliance with the specifications.
• determining the test criteria involves finding the boundaries of the acceptance region in the measurement space.
• the relationship between the measured response and the various circuit specifications can be defined as a plurality of functions which map the measured response to each individual circuit specification.
• the input stimulus is applied to the CUT at block 40.
• the response resulting from the application of the input stimulus is then measured, as indicated at block 42, and stored if desired. Once this measured response has been received, it can be input into the various mapping or synthesizing functions for the various circuit performance parameters (i.e., specifications) as indicated in block 44.
• the mapping functions can then be evaluated to determine whether the circuit satisfies each individual specification, as indicated in block 46, so that a pass/fail determination can be made,
• SUBSTTTUTE SHEET (RULE 26) as indicated in block 48. At this point, flow can continue to specification based testing, if needed, as indicated in FIG. 2.
• the measurements obtained from applying the test stimulus are post-processed to define the test thresholds on the post-processed data rather than the measurements themselves.
• This process can be designated measurement synthesis.
• Measurement synthesis involves deriving n b synthesized measurements from the n m original measurements using the b synthesizing functions. All the information about the performance parameters of the circuit can be extracted using the synthesizing functions. As will be appreciated by persons having ordinary skill in the art, the synthesizing functions are preferably derived near the boundary of the acceptance region within performance parameter space to increase the accuracy of the functions in predicting a passing or failing performance parameter.
• the/ performance parameter is very near to the specification bound b route i.e.,p is a critical circuit instance.
• Equation [10] requires that the f h synthesized measurement fm s m) be equal to the f h performance parameter s Notice that two different subscripts / ' and j are used since, as described above, a performance parameter can have a double ended specification on it. In that
• the synthesized measurements track the performance parameters, physically interpretable test criteria are obtained. Synthesized measurements contain much more information about the performance parameters than the measurements themselves, which is helpful for diagnostics. Second, there are robust nonlinear function approximation techniques which can be used to derive the synthesizing functions. Thus, the synthesizing functions can capture highly non-linear relations between measurements and performance parameters. For instance, as discussed below, a multivariate regression technique can be used to derive the synthesizing functions. Third, the misclassified circuits can be identified and handled systematically with this approach. For instance, as discussed below, various errors associated with the measurement synthesis can be incorporated to identify the circuits which are likely to be misclassified due to these errors.
• SUBSTTTUTE SHEET (RULE 26) neural networks or any other regression strategy to approximate the function f ms .
• the model produced by MARS can be of the form
• Each basis function is a truncated power spline basis function of desired order q.X k,m is one of the variables in x and t ⁇ , chorus is the knot location for the basis function.
• MARS modeling strategy is to progressively add basis functions based on the maximum reduction in the squared error of the model, until an over-fitted model is obtained. This basis set is then subjected to a backward stepwise deletion to produce the final model. While using measurement synthesis to determine test criteria, the chief source of misclassification of circuits are the inherent errors associated with regression and the non-idealities of the tester. As is discussed below, these non-idealities effect our test decision and how to identify circuits which needs to be tested further with the specification tests for fault detection.
• the residuals do not contain any information about the function that we are trying to approximate and they are usually modeled as normally distributed random variables with zero mean (e n - N(0, ⁇ ] n )) .
• the variance ⁇ e 2 n can be easily calculated from the training data without performing any additional circuit simulation.
• the independent variables m in msi(m) can be replaced with (m+e m *).
• the errors in measurement (ejon,*) can be modeled as normally distributed random variables with zero mean and known covariance matrix ⁇ em (17).
• the random error in the synthesized measurement can be modeled as normally distributed with zero mean and variance ⁇ e 2 m which can be evaluated by simulation. It is to be noted that the variance can be estimated by evaluating the synthesizing function using a set of measurements with errors injected according to the measurement error statistics. This can be done without performing any additional circuit simulation. Thus, the following can be obtained
• m is the actual measurements that we are making on the CUT for fault detection
• the random error, e is the deviation of the synthesized measurement from the actual performance parameter S j .
• FIG. 6 shows an example test flow diagram for production testing of analog ICs using measurement synthesis.
• block 60 Given the acceptable ranges of all specifications, the measurement uncertainty due to inaccuracies in measurement instrumentation and modeling errors, and the mathematical prediction functions for predicting the circuit specifications form test response measurements, flow continues to block 61 in which it is determined whether the circuit needs further testing. If further testing is needed, specification tests can be conducted in block 64. If not all of the specifications have been computed, flow continues from 62 to block 65 in which, for a selected specification, the specification value is predicted from the response measurement. Next, at 66, it is determined whether
• SUBSTTTUTE SHEET (RULE 26) the predicted value is such that it is certain that the circuits is good despite uncertainties. If not, flow continues back to block 61. If so, however, flow continues to 67 in which it is determined whether the predicted specification value is such that it is certain that the circuit is bad despite the uncertainty of ⁇ ,. If not, flow continues to block 68, and the specification value is very close to the boundary of acceptance for the specification.
• An objective during the test design and while deriving the synthesizing functions is to minimize the number of circuits which need further specification testing. This in turn can be achieved by minimizing the variance ⁇ e 2 ⁇ . To minimize this variance, the individual variances of the two errors e m ⁇ and e n can be minimized. The variance of the error due to regression can be minimized by appropriately selecting the training circuit instances for the MARS.
• measurements are the independent variables and the performance parameters are the dependent variables.
• a set of appropriate circuit instances in the process parameter space can therefore be selected and mapped to the performance parameter space and measurement space by circuit simulation.
• the accuracy of the generated MARS model depends heavily upon the circuit instances used for building the model. From equations [9] and [10] it can be understood that the synthesized measurements must track the corresponding performance parameters very well near the specification bound. Hence, to obtain a very accurate synthesizing function
• the framing set typically must contain a large number of circuit instances which lie close to these bounds (critical circuit instances).
• SUBSTTTUTE SHEET (RULE 26) in Figure 7 can be used to dynamically generate the critical circuit instances required for training.
• the process statistics and specifications can be input, as indicated in block 70. If all of the specifications have been considered (71), flow continues to block 72 where descriptions of circuits having specification values very close to the specification boundaries are generated. If, on the other hand, not all of the specifications have been considered, flow continues to block 73 in which sets of current descriptions with different process parameter values are randomly generated using the supplied process statistics.
• a mathematical function of is built which maps the random process parameter values to their respective specification values. This function can then be used to determine what the process parameters should be so that the circuit specifications will be close to or at the respective specification boundaries.
• Each set of process parameters thereby determine, by simulation, the corresponding specification values. If these values differ from the predicted values ( ) by less than a specified error (ErroMax) at 75, then flow continues to block 77 and the process is repeated. If not, however, flow continues to block 76 where, for newly generated circuits whose specifications do not lie close to the specification boundary, flow will continue back to block 74.
• ErroMax a specified error
• This procedure takes this MARS model and finds a set critical circuits instances.
• This procedure uses binary search algorithm with the nominal circuit instance and a randomly selected circuit instance as the initial guesses to search for a critical circuit instance. Using these newly generated circuit instances, the average squared error between the performance parameters predicted and those obtained through simulation can be calculated. If this error is less than a predefined value, the existing MARS model is accurate near the specification bound, else more circuits are added to the training set to improve the model accuracy.
• the outputs of this routine are the MARS model relating the circuit performance parameters to the process parameters and a set of critical circuit instances.
• PCA principal component analysis
• PCA cannot be used directly for measurement selection. Therefore, a heuristic based on measurement ordering to select a set of measurements is used which will give a minimum variance ⁇ e 2 ⁇ .
• the procedure OrderMeasurements removes one measurement at a time from the list of measurements and calculates the variance ⁇ e 2 ⁇ of the synthesizing function derived using the remaining measurements. The measurements are then ordered in the ascending order of the variance ⁇ e 2 ⁇ .
• the procedure OrderMeasurements shown in FIG. 8, removes one measurement at a time from the list of measurements and calculates the variance ⁇ e 2 ⁇ of the synthesizing function derived using the remaining measurements. The measurements are then ordered in the ascending order of the variance ⁇ e 2 ⁇ .
• genetic algorithms can be used to search for the optimum PWL transient stimulus and sampling points.
• An objective during test design is to increase the standard deviation ⁇ p by appropriately choosing the measurements. This, in turn, can be achieved by selecting those measurements which are sensitive to the process parameter deviations of the circuit.
• the search space typically must be encoded into genetic strings or chromosomes a set of rules must be provided for selection, crossover, mutation and fitness evaluation for these genetic strings. For example, the following rules could be established:
• the i* gene of the genetic string is an integer representing the voltage at time point t, (equation [22]).
• the f gene has a value j
• the corresponding voltage of the PWL transient waveform is given by equation [23].
• the string length of the population is equal to the total number of time divisions n,.
• FIG. 10 shows the encoding in detail. In the figure, maximum voltage was assumed to be 5N and there are 5 voltage divisions and 5 time divisions.
• Tournament selection involves picking two strings from the population and selecting the better for reproduction.
• Crossover The crossover operator takes genes from each of the parent string and combines them to create child strings. A uniform crossover scheme can then be used for creating child strings. FIG. 11 shows how uniform crossover is performed to produce the child strings. Each gene of the parent strings is chosen with certain probability and are swapped to yield the two child strings.
• Mutation After the child strings are created, the genes of the child strings can undergo mutation. For mutation, a gene is selected with a certain probability (mutation probability) and is replaced with a random number within the allowed range.
• EXAMPLE 1 provides the performance specifications of an operational amplifier. In the absence of real data from the silicon foundry, it is assumed that the specification failure in this operational amplifier is caused by variations in seven parameters namely, the threshold voltages (N ton V top ), gate oxide thickness (T ox ), aspect ratios ((W/L) n , (W/L) p ), bias resistance ( R i as ) and compensating capacitor (CC). For the purpose of this example, it is assumed that the test measurement hardware has the capability of measuring small signal voltage gain of the operational amplifier for fault detection with 0.1 % accuracy.
• the training set for building the synthesizing function for each of the specification was generated using the algorithm FindTrainSet().
• transient tests were generated using the methods described herein.
• the two double-ended specifications were decomposed to single-ended specifications to give a total of five single-ended specifications.
• Circuit instances were generated for each of the five single- ended specifications using GenerateTrainSet(), and five circuits (one corresponding to each of the single-ended specification) with minimum distance (/ 2 , norm) from the nominal circuit were selected for generating the optimum PWL input stimulus.
• a maximum testing time of 5ms was assumed.
• For encoding the PWL input into the genetic string a string of 20 genes (giving 20 PWL segments) was assumed and the voltage at the comer points of the PWL segments was quantized to 20 levels between -5V and 5V.
• the output of the CUT was sampled at 20 equally spaced time points for fault detection. For each of the five single-ended specifications, these 20 measurements were ordered and a subset of measurements were chosen to derive the synthesizing functions. For measurement ordering and selection, a measurement error of 1% was assumed. The number of measurements required for each of the synthesizing functions is given in Table 3 along with the corresponding specifications.

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