EP1194863A1 - Appareil de traitement des donnees - Google Patents

Appareil de traitement des donnees

Info

Publication number
EP1194863A1
EP1194863A1 EP00942235A EP00942235A EP1194863A1 EP 1194863 A1 EP1194863 A1 EP 1194863A1 EP 00942235 A EP00942235 A EP 00942235A EP 00942235 A EP00942235 A EP 00942235A EP 1194863 A1 EP1194863 A1 EP 1194863A1
Authority
EP
European Patent Office
Prior art keywords
signals
data
formats
backplane
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00942235A
Other languages
German (de)
English (en)
Inventor
John Cameron Mackichan
Christopher Simon Winter
Michael Robson
David John Taylor Heatley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
British Telecommunications PLC
Original Assignee
British Telecommunications PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Telecommunications PLC filed Critical British Telecommunications PLC
Priority to EP00942235A priority Critical patent/EP1194863A1/fr
Publication of EP1194863A1 publication Critical patent/EP1194863A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections

Definitions

  • Neural nets have been proposed for pattern recognition and other purposes but they are not able to adapt rapidly to changes in the system parameters and require extensive training.
  • the apparatus according to the invention is not limited to any particular technology, medium or transport mechanism for the signals of different formats, which for example, can be optical, electrical, chemical or any other suitable form.
  • the use of signals in different formats allows data to be analysed from different perspectives so that a processor operable with signals in a first format may be configured to perform efficient processing on the basis of an analysis of the signals in a second different format.
  • a feedback path may be provided to adjust filtering characteristics of at least one of the adaptive filters as a function of the outcome of the processing performed by at least one of the processors.
  • At least one of the processors may be operable to carry out processing according to a plurality of different algorithmic processes and to select one of them according to the outcome of the processing performed by another of the processors.
  • the processing of data in one of the formats can be used to optimise processing of the data in another of the formats so as to provide more efficient algorithmic processing of the data.
  • Figure 1 is a schematic block diagram of an architecture for a data processing apparatus according to the invention
  • Figure 3 is a schematic illustration of the relationship between an entity and its attributes
  • Figure 4 is a schematic diagram of how entities are related through their attributes.
  • FIG. 5 is a schematic block diagram of a code breaking machine in accordance with the invention. Detailed description
  • Each of the adaptive filters 4 has an associated processor 5 capable of processing signals in the individual formats handled by the filters.
  • the result of the filtering and processing is fed back on path 6 to the backplane 2 so that the processed signals can be then pass to another filter-processor combination 4, 5 for further processing.
  • processor 5a produces an output 6a which passes out of the apparatus.
  • an array of transducers/effectors 7 can be provided, responsive to the outputs of the processors 5 to provide an output 6 which can be used to control other processor/filter combinations or communicate with external apparatus.
  • inputs I are present in the environment, are detected by the sensor array 1 so as to place signals on the universal backplane 2.
  • the signals may be of any suitable form in different formats, as previously described, and the role of the backplane 2 is to ensure that all of the processor/ filter components can receive signals in corresponding appropriate formats from the backplane.
  • the formats may include optical, photonic, liquid or gaseous movement, changes of state and the connections may be achieved in free space or constrained for example in a fibre or tube.
  • Modes of communication may be analog or digital in the backplane 2.
  • the modes of communication in the backplane are inherently multi- modal.
  • an optical fibre can transmit both on many wavelengths and either analog or digital signals.
  • the backplane 2 may perform differential attenuation of signals and may exhibit different temporal characteristics to different signals.
  • the adaptive filters 4 connected to the backplane 2 select from the signals of different formats those that they can recognise. This will depend on the physical properties and the algorithmic nature of the signal. For example, an optical filter 4 can be set to a particular wavelength, signal threshold and window time, thus acting as a filter element tuned to particular signals. The filter can also act as a buffer by looking only for signals that exhibit a particular short term periodicity. The filter would respond purely to analog signals at the same wavelength and thus some signals from the backplane can strongly stimulate certain filters and weakly or differentially be detected by other ones of the filters.
  • the filters 4 are adaptive and thus change their filtering properties according to the signals that are acted upon by them.
  • the filtered signals 6 are used to adjust the characteristics of the filters 4 adaptively.
  • the filter 4 can be considered as accepting signals inside certain bounds which the overall apparatus can alter. For example, bounding of the filtered signals in terms of wavelength, threshold and window duration can be carried out.
  • bounding of the filtered signals in terms of wavelength, threshold and window duration can be carried out.
  • the effect of the feedback to the adaptive filters 4 is either to increase or decrease bounding of the filter. The exact mechanism will depend on the processor 5 and the filter 4. The goal is to reinforce desirable behaviours. The bounding could even initially increase response strength and then decrease so that the filter 4 self-tunes to an optical response level.
  • the processors 5 are configured to receive filtered inputs from the filters 4 and to carry out an algorithmic process to provide an output.
  • the processors 5 may take many different forms.
  • the processors 5 may comprise conventional digital processors or can operate according to an analog computation, involve interaction with humans, be a wet chemical, electronic or other action.
  • the processors 5 may include individual memories to store precise, imprecise or temporally failing data. Unlike a conventional Von Neumann processor, there may not be a requirement for a dedicated conventional memory store, but instead, memory elements may be distributed throughout the processor architecture, for example in the backplane 2 or the filters 4.
  • Figure 2 provides an insight into how the architecture will operate to produce an effective output 6, having been stimulated at its input la.
  • the apparatus in basic terms produces a solution, or a manipulation of an effector, by operating a transform from the problem space P which acts with the knowledge space K to create a solution or a number of solutions in the solution space S.
  • the bounding vector B is used to bound the solution.
  • the error function erf I is used to stimulate the machine randomly and/or synchronously in order to prevent it from falsely locking into a limited solution space.
  • the process is presented in two dimensions for each of explanation, it will be understood that the architecture of Figure 1 has the capability to operate in N dimensions.
  • Each element of the P, K, and S_ vectors consist of a single entity which has a number of attributes associated with it, as indicated in Figure 3.
  • the machine builds its knowledge space K by creating entities and associate attributes with each entity.
  • the machine links the attributes, which are not permanent in time, and the links are continually reviewed and reinforced as appropriate. If the links are used often, then they are reinforced because it indicates a strong association between the entity and the attribute. If the link is used less often, it is weak and is removed relatively quickly.
  • Figure 4 illustrates schematically how entities are related through their attributes.
  • Figure 4 illustrates entity groups El, E2, E3, and E4 and E5.
  • Knowledge K is associated with an entity E, where: El represents a dog E2 represents a cat E3 represents a mink E4 represents a car E5 represents a locomotive
  • An attribute that could link groups El, E2 and E3 is fur.
  • An attribute that could link group E4 and E5 is steel.
  • this inefficiency is improved by using additional processing techniques on the signals in different formats in order to provide the computer with an indication of where to start looking for a solution.
  • Conventional code breaking algorithms are run on processor/filter combinations 4a/5a, and additional processing is carried out by processors and filters 4b, 5b and 4c, 5c.
  • a processor 5b in the form of a spectral analyser is responsive to the characteristics of the electrical signals in the backplane 2.
  • the analyser 5b is capable of making measurements e.g. from 0-10 GHz with integral filtering functionality thereby providing an inherent adaptive filter 4b.
  • the element 5b initially senses the electrical coded signal I on the conduit 2a, its filter 4b is set to maximum bandwidth namely 0 - lOGHx.
  • the analyser then takes measurements in relation to the signal frequency, amplitude and power of the signals and upon analysing the measurements, modifies the bandwidth of the filter in order to band limit the spectrum of measurement.
  • This modification of the filter from its maximum bandwidth to a band limited value constitutes learning and homeostasis, as the filtering is adapted in response to an analysis of the incoming electrical signal. As long as there is no or little change in the input coded signal from conduit 2a, the filtering will stay in a relatively constant state, but will change in response to changes in the input signal characteristics. Additionally, data from the filter 4a/processor 5a can provide feedback through the electrical wiring to the filter 4b to allow its characteristics to be adaptively changed. Examples of suitable spectrum analysers are HP4395-500MHz, HP4936-1.8GHz, HP8757-40GHz.
  • the optical signals produced on the conduit 2b are detected by a processor/filter arrangement 5c, 4c capable of performing an optical Fourier transform.
  • the device may comprise a dispersive optical element which has an array of optical receivers which form the output of the filter 4c.
  • the optical signal When the optical signal is presented to the Fourier transformer, it produces a corresponding pattern in the focal plane of the device which is detected and hence characterised by the optical receiver array 4c.
  • the coded signal applied to the transformer is modified, the output from the array is consequently changed.
  • the element 4c/5c includes a memory and a simple processing capability to enable particular output patterns for the sensor array 4c to be stored and correlated with particular forms of input code from the optical fibre 2b.
  • the output from the sensor array 4 comprises an electrical signal 3a which is applied to the electrical conduit 2a.
  • a conventional digital processor 5a such as a Pentium TM or similar digital processor with an associated input filter functionality 4a is coupled to the electrical conduit 2a.
  • the filter functionality may provided by software running on the processor or by the provision of an individual processor dedicated to the filtering function.
  • the processor 5a includes a conventional memory and holds a number of different algorithms/programs that can be used to decipher the encrypted code on the conduit 2a. In use, the processor 5a uses the algorithms to attempt to break the code. The processor 5a tries all of the individual programs in a sequence.
  • one of the algorithms may be configured as described in "Breaking DES", Paul C Kocher, published by RASA Laboratories in CryptoBytes, the Technical newsletter of RSA Laboratories, a Division of RSA Data Security Inc, Volume 4, Number 2, Winter 1999.
  • Another algorithm may be as described in "Attacking Elliptic Curve Cryptosystems Using Parallel Pollard rho Method” by Adrian E Escott, Alexander P L Selkirk & Dimitrios Tsapakidis, in the same publication.
  • the incoming data from the conduit 2a is provided with an identification label by the processor 5a.
  • This label is communicated through the backplane 2 to the other processors 5b, 5c where it is stored and associated with the filtered outputs produced by the filters 4b and 4c.
  • This common label is used to associate the coded signal with the most efficient method employed to crack the code.
  • the processor 5a Once the processor 5a has identified a solution for the encrypted data, it carries out a sanity check on the solution and possibly refers the solution to a human operator for final checking, on output 6a. Then, assuming that the solution satisfies the criteria, the previously mentioned code label associated with the encrypted signals is associated with the solution itself. This association performs two functions. The first is to allow the machine to learn, so that each time a code is entered into the machine and has already been labelled, then the machine, from its previous experience knows what algorithms are suited to solving it. Thus, the processor 5ais directed to perform algorithmic processing in a particular sub-set of its possible range of possibilities rather than use the complete set of algorithms that are available, thereby speeding up the process.
  • the processor 5a also carries out a checking of the solution obtained from the code breaking algorithms in order to determine whether a solution has been found or whether further attempts to break the code are required using different algorithms.
  • the machine of Figure 5 When the machine of Figure 5 is first switched on, it has no knowledge of the characteristics of the encrypted signal applied to input I or which algorithm should be employed in processor 5a to crack the code.
  • the first encoded signal When the first encoded signal is presented to the machine, all of the processors 5a, b, c operate on the signal.
  • the coded signal is characterised by each of the processors and associated with the aforementioned label generated by processor 5a. Once characterised, the machine is able to identify the form of the code, in this case the multiplication of two prime numbers. This may need intervention by a human operator. Having identified the make up of the code, the processor 5a will employ one of a number of number-crunching algorithms to crack the code.
  • the processor 5a will associate the code label with the corresponding solution so as to associate a particular part of the solution space provided by the algorithm with the solution.
  • the processor 5a will associate the code label with the corresponding solution so as to associate a particular part of the solution space provided by the algorithm with the solution.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Image Processing (AREA)
  • Optical Communication System (AREA)

Abstract

La présente invention concerne un appareil de traitement des données qui agit sur des données de formats différents afin d'améliorer l'efficacité computationnelle dans un système complexe. L'appareil de l'invention comprend une face arrière (2) destinée à des signaux de données de formats différents tels que les formats électriques et optiques, des filtres adaptatifs (4) qui reçoivent les signaux de données de formats différents depuis la face arrière, et des processeurs (5) qui reçoivent les données de différents formats en provenance de la face arrière, au moins un des processeurs pouvant traiter les données provenant de l'un des filtres et étant sensible au résultat du filtrage de données effectué par au moins un autre filtre pour adapter le traitement effectué. Un processus d'analyse cryptographique est décrit à titre d'exemple.
EP00942235A 1999-07-01 2000-06-30 Appareil de traitement des donnees Withdrawn EP1194863A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP00942235A EP1194863A1 (fr) 1999-07-01 2000-06-30 Appareil de traitement des donnees

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP99305219 1999-07-01
EP99305219 1999-07-01
EP00942235A EP1194863A1 (fr) 1999-07-01 2000-06-30 Appareil de traitement des donnees
PCT/GB2000/002531 WO2001002976A1 (fr) 1999-07-01 2000-06-30 Appareil de traitement des donnees

Publications (1)

Publication Number Publication Date
EP1194863A1 true EP1194863A1 (fr) 2002-04-10

Family

ID=8241490

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00942235A Withdrawn EP1194863A1 (fr) 1999-07-01 2000-06-30 Appareil de traitement des donnees

Country Status (4)

Country Link
EP (1) EP1194863A1 (fr)
AU (1) AU5694000A (fr)
CA (1) CA2377925A1 (fr)
WO (1) WO2001002976A1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3908786A1 (de) * 1989-03-17 1989-08-03 Cordell Steve Verfahren zur informationsuebertragung zwischen platinen einer elektronischen schaltung
US5896473A (en) * 1996-06-26 1999-04-20 Rockwell International Corporation Re-configurable bus back-plane system
JPH10105528A (ja) * 1996-09-30 1998-04-24 Nec Corp マルチプロセッサシステム
US6016212A (en) * 1997-04-30 2000-01-18 At&T Corp Optical receiver and demultiplexer for free-space wavelength division multiplexing communications systems

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0102976A1 *

Also Published As

Publication number Publication date
WO2001002976A1 (fr) 2001-01-11
CA2377925A1 (fr) 2001-01-11
AU5694000A (en) 2001-01-22

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