EP1183603A4 - Appareil et procede pour un processeur de securite programmable - Google Patents

Appareil et procede pour un processeur de securite programmable

Info

Publication number
EP1183603A4
EP1183603A4 EP00932153A EP00932153A EP1183603A4 EP 1183603 A4 EP1183603 A4 EP 1183603A4 EP 00932153 A EP00932153 A EP 00932153A EP 00932153 A EP00932153 A EP 00932153A EP 1183603 A4 EP1183603 A4 EP 1183603A4
Authority
EP
European Patent Office
Prior art keywords
security
programmable
circuit
request
reconfigurable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00932153A
Other languages
German (de)
English (en)
Other versions
EP1183603A1 (fr
Inventor
Stephen L Wasson
David K Varn
John D Ralston
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Deutschland GmbH
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1183603A1 publication Critical patent/EP1183603A1/fr
Publication of EP1183603A4 publication Critical patent/EP1183603A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks

Definitions

  • This invention relates generally to communication systems. More particularly, this invention relates to a programmable reconfigurable security processor for an electronic communication device.
  • a programmable reconf ⁇ gurable security processor enables an electronic communication device to operate according to multiple standards, or to accommodate multiple applications, wherein each standard or application is executed pursuant to proper authorization.
  • the programmable reconfigurable security processor can be exploited in any device in which different applications, algorithms, routines, or utilities may be loaded at or prior to run-time.
  • the security processor can be used to control licenses to intellectual property to enable new standards, applications, system upgrades, and trial periods.
  • the security processor can perform real-time encryption and/or decryption of information streams. This embodiment of the invention can be successfully exploited in multi-mode products, such as multi-mode wireless telephones, information terminals, encryption equipment, and image and multimedia manipulation devices.
  • a digital logic circuit comprises a programmable logic device and a programmable security circuit.
  • the programmable security circuit stores a set of authorized configuration security keys.
  • the programmable security circuit compares the authorized configuration security keys with an incoming configuration request, and selectively enables a new configuration for the programmable logic device in response to the configuration request.
  • the programmable security circuit also stores a set of authorized operation security keys.
  • the programmable security circuit compares the authorized operation security keys with an incoming operation request from the programmable logic device, and selectively enables an operation within the programmable logic device in response to the operation request.
  • FIGURE 1 illustrates an exemplary method for downloading a security algorithm across a network in accordance with an embodiment of the invention.
  • FIGURE 2 illustrates an exemplary process for authorizing, executing, testing, and downloading a security algorithm across a network in accordance with an embodiment of the invention.
  • FIGURE 3 illustrates an exemplary process for transferring the parameters of a security algorithm to a programmable reconfigurable security processor in accordance with an embodiment of the invention.
  • FIGURE 4A illustrates an exemplary process for analyzing a set of security or encryption standards.
  • FIGURE 4B illustrates an exemplary architecture including a programmable reconfigurable security processor in accordance with an embodiment of the invention
  • FIGURE 5 illustrates an exemplary process for profiling a set of security or encryption standards to design a programmable reconfigurable security processor in accordance with an embodiment of the invention.
  • FIGURE 6A illustrates an exemplary kernel in accordance with an embodiment of the invention.
  • FIGURE 6B illustrates exemplary reconfigurable data processing architectures that may be implemented by kernels of the invention.
  • FIGURE 7 illustrates characteristic energy efficiency versus flexibility for several types of fixed or programmable data processors.
  • FIGURE 8 illustrates a programmable reconfigurable security processor in accordance with an embodiment of the invention.
  • FIGURE 9 illustrates an exemplary kernel in accordance with an embodiment of the invention.
  • FIGURE 10 illustrates an exemplary kernel in accordance with an embodiment of the invention.
  • FIGURE 11 illustrates an exemplary communications device with a programmable security circuit in accordance with an embodiment of the invention.
  • FIGURE 12 illustrates an exemplary programmable security circuit in accordance with an embodiment of the invention.
  • FIGURE 13 illustrates a flow chart of an exemplary process in accordance with an embodiment of the invention.
  • Figure 1 illustrates an exemplary method by which a security algorithm is served by a server 112 across a network 120 to a mobile electronic communications terminal 190.
  • the security algorithm can include, but is not limited to, a public key exchange and data encryption using a secret key.
  • the security algorithm is issued by the server 112 and is sent across the network 120 through a communication link 130 to a repository 140 within the mobile terminal 190.
  • the repository 140 signals the arrival of the security algorithm to the mobile terminal 190.
  • a flexible security framework 150 establishes an identification mechanism for the security algorithm.
  • the security algorithm contains a header 152 that includes definitions of the security algorithm's capabilities and pertinent regulatory parameters/specifications.
  • the security algorithm's capabilities are categorized, for example, as open standard, manufacturer-specific, or proprietary. Further, the capabilities also include an installation procedure 172. Regulatory parameters/specifications include, for example, the source of the security algorithm and definition of additional certification 170. Using information contained in the header 152, installation can proceed based on vendor specified application program interfaces (APIs) and a virtual machine interface (VMI) 180.
  • APIs application program interfaces
  • VMI virtual machine interface
  • the VMI is essentially a software programmer's interface to the available hardware resources 182.
  • Figure 2 illustrates an exemplary process in accordance with an embodiment of the invention.
  • Figure 2 includes a user 202, a download process management routine 204, an authentication function/party 206, and a network 208.
  • the user 202 operates a mobile communication terminal 190.
  • the network 208 defines available security services.
  • the mobile terminal 190 which is controlled by the user 202, requests a specific service, the network 208 identifies itself for authentication purposes (step 210A). If the mobile terminal 190 requests an authentication to the authentication function/party 206 (i.e., by a trusted third party, TTP, or other authentication provider), authentication validation is returned to the mobile terminal 190 by the authentication function/party 206 (step 210B).
  • TTP trusted third party
  • the mobile terminal 190 then sends its authentication information to the network 208 (step 210B).
  • the network 208 requests and receives capability description from the mobile terminal 190 (step 210C).
  • the network 208 selects an appropriate security algorithm and specifies the security algorithm to the mobile terminal 190, including the necessary quality of service (e.g., bit e ⁇ or rate) required to reliably deliver the selected security algorithm (step 2 IOC).
  • the network 208 specifies and the mobile terminal 190 accepts a scenario for downloading the security algorithm (step 210D).
  • the security algorithm is delivered to the mobile terminal 190, possibly in segments or data packets (step 210E).
  • the mobile terminal 190 performs testing to confirm co ⁇ ect delivery and reports the testing results back to the network 208 (step 210E).
  • the mobile terminal 190 requests and receives another level of authentication (step 210E).
  • the mobile terminal 190 installs the security algorithm and confirms the installation to the network 208 (step 21 OF).
  • Billing negotiations are transacted (step 21 OF). If the installed security algorithm requires additional components to affect end functionality, the mobile terminal 190 sends a key to the authentication function/party 206 to receive such additional software (step 21 OF). Additional software is downloaded and installed (step 21 OF). Finally, full functionality of the security algorithm is tested and confirmed by the mobile terminal 190 (step 210G).
  • Figure 3 illustrates an exemplary process for configuring a programmable reconfigurable security processor 350 in a multi-standard mobile communications terminal 190.
  • the header 152 of the security algorithm is processed to create a configuration table 320.
  • the configuration table 320 includes specific security capabilities and corresponding parameters and values.
  • Information provided in the configuration table 320 is passed through the mobile communication terminal's API and VMI 180 to the security processor 350.
  • the security processor 350 comprises a number of parameterized hardware data processing kernels 360.
  • the functionality of each kernel 360 is defined by a corresponding internal table 370.
  • the contents of internal table 370 are set by the security processor 350 in accordance with definitions in the configuration table 320.
  • Figure 4A illustrates an exemplary method for analyzing constituent algorithms for a programmable reconfigurable security processor 350.
  • Multiple security standards or security algorithms are indicated in columns 410A, 410B, and 4 IOC.
  • Data processing functions pertinent to the various standards or algorithms are indicated in rows 420A, 420B, and 420C. Examples of security standards are AES, DES, RSA, MISTY, and IDEA.
  • the programmable reconfigurable security processor 350 is designed to implement constituent data processing functions of various security algorithms.
  • FIG. 4B illustrates an exemplary architecture 430 that is designed to implement constituent data processing functions of various security algorithms.
  • the architecture 430 includes a programmable reconfigurable security processor 350, software programable processors 440, and a communication bus 434.
  • the software programmable processors 440 include a digital signal processor (DSP) 442 and a control microprocessor 444.
  • the communication bus 434 links the control microprocessor 444, the DSP 442, and the programmable reconfigurable security processor 350. Data from the communication bus 434 is applied to the programmable reconfigurable security processor 350 and the software programmable processors 440.
  • the programmable reconfigurable security processor 350 includes a set of parallel heterogeneous data processors (not shown) or kernels 360.
  • the kernels 360 perform computationally intensive data processing functions and are selected and configured in a modular, non-redundant manner.
  • each kernel 360 and its interconnections can be quickly reconfigured, such that the architecture 430 can quickly (i.e., in milliseconds) switch from one security standard, application, or service to another.
  • the DSP 442 performs the less computationally intensive data processing functions relative to functions performed by the kernels 360 in the programmable reconfigurable security processor 350.
  • the control microprocessor 444 performs control and other functions.
  • FIG. 5 illustrates an exemplary process for designing a programmable reconfigurable security processor 350.
  • Constituent functions 420 are applied in a profiling/mapping analysis (step 530).
  • the profiling/mapping analysis includes the step of analyzing each constituent function 420 to determine computational cost or intensity.
  • the most computationally intensive constituent functions are mapped into one or more processing kernels 360 of the programmable reconfigurable security processor 350.
  • the remaining functions are mapped into the DSP 442 and the control microprocessor 444.
  • the profiling/mapping analysis evaluates inter- kernel communication signals (step 542) to determine the design of a reconfigurable data router 538.
  • Data router 538 affects all necessary inter-kernel data transfer and interface to the communication bus 434.
  • the profiling/mapping also evaluates kernel control and sequencing (step 544).
  • FIG. 6 A illustrates an exemplary kernel 360 in accordance with an embodiment of the invention.
  • the kernel 360 includes a local memory 622, a data sequencer 624, and a parameterizable, configurable arithmetic logic unit (ALU) 626.
  • the ALU 626 performs necessary data processing operations.
  • the local memory 622 serves as a high-speed cache.
  • the data sequencer 624 orchestrates the flow of data between the local memory 622 and the ALU 626. Data is transported into and out of the kernel 360 via a bus 610. Any configuration control or status signal is transported into and out of the kernel 360 via a bus 612. The configuration control is based on the parameter and value set forth in the internal table 370.
  • Figure 6B illustrates additional exemplary configurable architectures for a kernel 360.
  • any one of the four exemplary configurable architectures: reconfigurable logic with programmable function units 642, reconfigurable datapaths 644, reconfigurable arithmetic circuits 646, and reconfigurable control circuits 648 can be mapped into one or more kernels 360.
  • Figure 7 illustrates a comparison of the energy efficiency (evaluated in MOPS per milliwatt) and flexibility of among different types of devices.
  • the programmable reconfigurable security processor 350 is the second best in energy efficiency because it is optimized based on a set of security algorithms.
  • Digital signal microprocessors and embedded processors are less efficient because of overhead required to support instruction-set programmability.
  • Programmable logic devices are the least efficient because PLDs must employ general resources to permit fine-grained reconfiguration.
  • the fixed-function hardware is the most efficient, it is not as desirable as the programmable reconfigurable security processor 350 because the fixed-function hardware is not as flexible.
  • the programmable reconfigurable security processor 350 can be employed to perform various functionality, for example, (1) to perform encryption/decryption of data, and 2) to perform encryption/decryption of configuration information.
  • Figures 8, 9, and 10 illustrate the first exemplary functionality and Figures 11, 12, and 13 illustrate the second exemplary functionality.
  • Figure 8 illustrates a programmable reconfigurable security processor 350.
  • the security processor 350 includes a plurality of logic modules or kernels 360A, 360B, 360C, and 360D that are interconnected by signal sets 802 and 804.
  • the signal set 802 enables the kernels 360 adjacent in one dimension (i.e., vertically) to be cascaded.
  • kernel 360A and kernel 360C are cascaded by the signal 802 A, such that the output of kernel 360A becomes the input of kernel 360C.
  • kernel 360B and kernel 360D are cascaded by the signal 802B, such that the output of kernel 360B becomes the input of kemel 360D.
  • the signal set 804 enables kernels 360 adjacent in another dimension (i.e., horizontally) to be concatenated.
  • kernel 360A and kernel 360B are concatenated by the signal 804 A, such that the most significant stages of kernel 360B are passed to the least significant stages of kernel 360A.
  • kernel 360C and kemel 360D are concatenated by the signal 804B, such that the most significant stages of kernel 360D are passed to the least significant stages of kemel 360C.
  • kernels 360 are configured by input and control signal 803. Untransformed data is applied to kernels 360A and 360B via a signal set 806. Such untransformed data is processed by the kernels 360 and outputs via a signal set 805.
  • Figure 9 illustrates an exemplary embodiment of a kernel 360.
  • the kernel 360 implements a reduced instruction set computing element expressly optimized for computing encryption/decryption rounds.
  • the kernel 360 comprises a programmable microsequencer 903, a reconfigurable data transformation unit 906, and an operand memory 908.
  • the microsequencer 903 is designed to execute a highly reduced instruction set including, but not limited to, branch instructions and a limited number of input/output functions.
  • the microsequencer 903 is configured by input and control signal 902, which is a subset of signal 803 in Figure 8.
  • the microsequencer 903 instruction word comprises at least an operation code (OP), a branch condition field (BC), a next-state field (NS), and an output function field (OF).
  • OP operation code
  • BC branch condition field
  • NS next-state field
  • OF output function field
  • the OP defines the type of instruction being executed
  • the BC determines what condition alters the course of instruction execution
  • the NS determines the branch destination
  • the OF sources control signals to both the reconfigurable data transformation unit 906 and the operand memory 908.
  • Operations of reconfigurable data transformation unit 906 are controlled by two mechanisms, namely, the input and control signal 902 and a sequence control signal 904.
  • the input and control signal 902 Prior to mn-time, the input and control signal 902 configures operations and constants to be used during an operation.
  • the sequence control signal 904 from the microsequencer 903 determines the micro-operation sequence.
  • the reconfigurable data transformation unit 906 operations are optimized for computing encryption/decryption rounds. Operations include, but are not limited to, XOR, shift right, shift left, rotate right, rotate left, bit-serial multiple, substitution, permutation, and signal swap.
  • the operand memory 908 accepts data input from signal set 909, which is a subset of the signal set 806 in Figure 8.
  • Data is fetched from memory 908 according to a signal 901 from the microsequencer 903.
  • Fetched data is passed to the reconfigurable data transformation unit 906 via a bi-directional signal 907 to be transformed according to the current configuration and the programmed sequence.
  • the transformed data is either returned to the operand memory 908 via the bidirectional signal 907 or transferred out of the reconfigurable data transformation unit 906 via a signal set 905, which is a subset of the signal set 805 in Figure 8.
  • the microsequencer 903 is programmed to perform multiple rounds, thus, increasing the number of transformations executable by a single kemel 360.
  • the microsequencer 903 is programmed to execute multiple cycles on an input wider than is provided by the signal set 806, thus, effectively increasing the encryption/decryption word width.
  • the same effect and benefit of programming a kernel to execute multiple cycles can be realized by concatenating adjacent kernels until the desired word width is obtained. Concatentaion consumes more resources but reduces the time to accomplish the same number of transformations.
  • cascaded kernels can effectively implement consecutive rounds thereby decreasing overall latency.
  • cascaded kernels may be used to implement more complex algorithms such as encrypt-decrypt-encrypt.
  • Figure 10 illustrates an exemplary higher performance encryption/decryption kernel 360.
  • the kernel 360 comprises a pure datapath structure consisting of n-bit wide transformation slices 1001.
  • the slices 1001 are configurable via input and control signal set 1003, which is a subset of the signal 803 in Figure 8.
  • the set of operations which a transformation slice 1001 may perform include, but is not limited to, XOR, shift right, shift left, rotate right, rotate left, bit-serial multiple, substitution, permutation, signal swap, and programmable delay.
  • the transformation slices 1001 perform a single operation per clock cycle.
  • the output of one transformation slice 1001 is the input to the next transformation slice 1001 via an input signal set 1002.
  • Kemel input is applied via a signal set 1005, which is a subset of the input signal set 806 in Figure 8.
  • Kernel output exits via a signal set 1004, which is a subset of the output signal set 805 in Figure 8.
  • FIG 11 illustrates an exemplary communication device 1100.
  • the communication device 1100 includes a programmable logic device 1102 and a programmable security circuit 1104.
  • the programmable logic device 1102 may be implemented as any known programmable logic circuit. For example, small, medium, or large granularity programmable logic blocks may be implemented in the programmable logic device 1102.
  • the programmable security circuit 1104 is a programmable logic block that may be implemented as a volatile, non-volatile, static, or dynamic device. In an exemplary embodiment, the programmable security circuit 1104 operates in two modes. In a first mode, the programmable security circuit 1104 provides authentication for new configurations of the programmable logic device 1102.
  • the programmable security circuit 1104 provides authentication for selected operations to be performed by the programmable logic device 1102.
  • a security request and read-back line 1106 is used to program a set of security keys into the programmable security circuit 1104. Each security key specifies a permitted programmable logic device configuration or programmable logic device operation.
  • the security request and read-back line 1106 may be used to query the programmable security circuit 1104 to determine whether the programmable logic device 1102 can assume a new configuration.
  • the programmable device 1100 also includes an external configuration data input line 1108 which provides new configurations to the programmable logic device 1102, a permission line 1110 which transfers new configuration to the programmable logic device 1102 when such new configuration is permitted or sends an enable signal to the programmable logic device 1102 when permission is granted by the programmable security circuit for requested operation, and an internal operation input line 1112 which passes requests from the programmable logic device 1102 to the programmable security circuit 1104 to perform operations.
  • FIG 12 illustrates an exemplary embodiment of the programmable security circuit 1104.
  • the programmable security circuit 1104 includes a linear feedback shift register 1202 and a comparator circuit 1204.
  • the linear feedback shift register 1202 stores security keys through the read-back line 1106. After the security keys have been programmed into the linear feedback shift register 1202, the read-back line 1106 is used as a security request line.
  • a programmable logic device 1102 may request to perform an operation or to reconfigure itself in response to a control signal or a predetermined set of conditions.
  • the comparator circuit 1204 compares the security keys in the linear feedback shift register 1202 with the request input from the security request line 1106.
  • the programmable security circuit 1104 may authorize the requested operation or reconfiguration.
  • the proposed configuration may be downloaded over the external configuration data input line 1108. The proposed configuration is then passed into the programmable logic device 1102 via the permission line 1110 to reconfigure the programmable logic device 1102. If the comparator circuit 1204 does not find a match between the request and one of the security keys stored in the linear feedback shift register 1202, the programmable logic device 1102 will be inhibited from accepting the new configuration.
  • the programmable logic device 1102 sends requests through the internal operation input line 1112 to the programmable security circuit 1104 to verify acceptable operations. If the programmable security circuit 1104 contains a matching key for the requested operation, then an enable signal is sent via the permission line 1110, to enable the programmable logic device 1102 to perform the requested operation.
  • Figure 13 illustrates an exemplary process in accordance with an embodiment of the invention.
  • a request is sent to a programmable security circuit to perform a certain operation on or to reconfigure a programmable logic device.
  • the programmable security circuit receives the request (step 1302).
  • the programmable security circuit compares the request to a set of preprogrammed security keys (step 1304).
  • the programmable security circuit authorizes the request (step 1308). If a match between the requested operation/configuration is not found in the set of security keys (step 1306), the programmable security circuit prohibits the PLD from accepting the new reconfiguration (step 1310). Alternately, the programmable security circuit returns a denial for the request for an impermissible operation.
  • the invention can be successfully exploited in any device in which different data, algorithms, routines, or utilities may be loaded at run-time. For example, the invention is useful in controlling licenses to intellectual property, such as for enabling new standards, system upgrades, and trial periods.
  • the invention can be successfully exploited in multi-mode products, such as multi-mode wireless telephones, encryption equipment, and image manipulation devices.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Storage Device Security (AREA)

Abstract

L'invention concerne un dispositif logique numérique comprenant un circuit de sécurité programmable qui stocke un jeu de clés de sécurité d'autorisation (538) pour la configuration. Le circuit de sécurité compare les clés d'autorisation (360) pour la configuration avec une demande entrante de configuration et effectue par sélection une nouvelle configuration (544) pour le dispositif logique programmable.
EP00932153A 1999-05-07 2000-05-05 Appareil et procede pour un processeur de securite programmable Withdrawn EP1183603A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13313199P 1999-05-07 1999-05-07
US133131P 1999-05-07
PCT/US2000/012479 WO2000068791A1 (fr) 1999-05-07 2000-05-05 Appareil et procede pour un processeur de securite programmable

Publications (2)

Publication Number Publication Date
EP1183603A1 EP1183603A1 (fr) 2002-03-06
EP1183603A4 true EP1183603A4 (fr) 2009-01-07

Family

ID=22457158

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00932153A Withdrawn EP1183603A4 (fr) 1999-05-07 2000-05-05 Appareil et procede pour un processeur de securite programmable

Country Status (6)

Country Link
EP (1) EP1183603A4 (fr)
JP (1) JP2003525481A (fr)
KR (1) KR100717577B1 (fr)
AU (1) AU4992200A (fr)
CA (1) CA2372391A1 (fr)
WO (1) WO2000068791A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2432294A1 (fr) * 2001-11-20 2003-05-30 Contentguard Holdings, Inc. Systeme de traitement d'expression de droits extensible
KR100447511B1 (ko) * 2001-12-26 2004-09-07 한국전자통신연구원 역할기반 접근제어 방법
KR100866951B1 (ko) * 2005-10-28 2008-11-05 삼성전자주식회사 메모리에 저장된 데이터를 보호할 수 있는 프로그래머블프로세서 및 방법
JP2007142591A (ja) * 2005-11-15 2007-06-07 Matsushita Electric Ind Co Ltd 暗号管理方法
US8931082B2 (en) * 2012-08-17 2015-01-06 Broadcom Corporation Multi-security-CPU system
US9363508B2 (en) 2012-09-12 2016-06-07 Broadcom Corporation Delta QP handling in a high efficiency video decoder

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0895164A2 (fr) * 1997-08-01 1999-02-03 Motorola, Inc. Procédé et dispositif de traitement cryptographique configurable

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52119137A (en) * 1976-03-31 1977-10-06 Mitsubishi Electric Corp Multi-processor system
US4914697A (en) * 1988-02-01 1990-04-03 Motorola, Inc. Cryptographic method and apparatus with electronically redefinable algorithm
US5448698A (en) * 1993-04-05 1995-09-05 Hewlett-Packard Company Inter-processor communication system in which messages are stored at locations specified by the sender
US5896449A (en) * 1993-12-02 1999-04-20 Alcatel Usa Sourcing L.P. Voice enhancement system and method
US5682478A (en) * 1995-01-19 1997-10-28 Microsoft Corporation Method and apparatus for supporting multiple, simultaneous services over multiple, simultaneous connections between a client and network server
DE19539700C1 (de) * 1995-10-25 1996-11-28 Siemens Ag Sicherheitschip
US5848231A (en) * 1996-02-12 1998-12-08 Teitelbaum; Neil System configuration contingent upon secure input
US5907580A (en) * 1996-06-10 1999-05-25 Morphics Technology, Inc Method and apparatus for communicating information
JP3783800B2 (ja) * 1996-08-09 2006-06-07 富士通株式会社 プログラマブルな論理素子／装置を用いた暗号化／復号化装置および方法
US6029245A (en) * 1997-03-25 2000-02-22 International Business Machines Corporation Dynamic assignment of security parameters to web pages

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0895164A2 (fr) * 1997-08-01 1999-02-03 Motorola, Inc. Procédé et dispositif de traitement cryptographique configurable

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
MIRSKY E ET AL: "MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources", FPGAS FOR CUSTOM COMPUTING MACHINES, 1996. PROCEEDINGS. IEEE SYMPOSIUM ON NAPA VALLEY, CA, USA 17-19 APRIL 1996, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 17 April 1996 (1996-04-17), pages 157 - 166, XP010206378, ISBN: 978-0-8186-7548-5 *
RUPP C R ET AL: "The NAPA adaptive processing architecture", FPGAS FOR CUSTOM COMPUTING MACHINES, 1998. PROCEEDINGS. IEEE SYMPOSIUM ON NAPA VALLEY, CA, USA 15-17 APRIL 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 15 April 1998 (1998-04-15), pages 28 - 37, XP010298175, ISBN: 978-0-8186-8900-0 *
See also references of WO0068791A1 *

Also Published As

Publication number Publication date
CA2372391A1 (fr) 2000-11-16
WO2000068791A1 (fr) 2000-11-16
EP1183603A1 (fr) 2002-03-06
JP2003525481A (ja) 2003-08-26
AU4992200A (en) 2000-11-21
KR20020007403A (ko) 2002-01-26
KR100717577B1 (ko) 2007-05-15

Similar Documents

Publication Publication Date Title
US7937594B2 (en) Apparatus and method for a programmable security processor
US8412915B2 (en) Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US7320062B2 (en) Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
EP0908810B1 (fr) Processeur sécurisé avec mémoire externe utilisant le chaînage par blocs et reséquencement des blocs
US8683215B2 (en) Programmable security platform
EP1840784B1 (fr) Dispositif memoire a semi-conducteur
US20040250095A1 (en) Semiconductor device and method utilizing variable mode control with block ciphers
US20230315913A1 (en) Multi-chip secure and programmable systems and methods
KR100717577B1 (ko) 프로그래머블 보안 프로세서 장치 및 방법
Hieb et al. A Prototype Security Hardened Field Device for Industrial Control Systems
WO2004012373A2 (fr) Procede et systeme de manipulation de multiples protocoles de securite dans un systeme de traitement
MXPA98008403A (en) Security processor with external memory that uses blocking and block reordering

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20011114

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

A4 Supplementary search report drawn up and despatched

Effective date: 20081209

17Q First examination report despatched

Effective date: 20090403

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INTEL MOBILE COMMUNICATIONS GMBH

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INTEL DEUTSCHLAND GMBH

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20181201