EP1177700A1 - Procede d'etablissement de profils de communications disparates, de normes de traitement de signaux et de services - Google Patents

Procede d'etablissement de profils de communications disparates, de normes de traitement de signaux et de services

Info

Publication number
EP1177700A1
EP1177700A1 EP00935876A EP00935876A EP1177700A1 EP 1177700 A1 EP1177700 A1 EP 1177700A1 EP 00935876 A EP00935876 A EP 00935876A EP 00935876 A EP00935876 A EP 00935876A EP 1177700 A1 EP1177700 A1 EP 1177700A1
Authority
EP
European Patent Office
Prior art keywords
signal processing
communications
functions
processing standards
standards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00935876A
Other languages
German (de)
English (en)
Inventor
Ravi Subramanian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Morphics Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Morphics Technology Inc filed Critical Morphics Technology Inc
Publication of EP1177700A1 publication Critical patent/EP1177700A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W48/00—Access restriction; Network selection; Access point selection
    • H04W48/18—Selecting a network or a communication service

Definitions

  • This invention relates generally to the design of multi-function digital devices. More particularly, this invention relates to a technique for profiling disparate communications and signal processing standards and services to facilitate the development of an application-specific processor.
  • TDMA Frequency Division Multiplexing
  • TDMA Time Division Multiple Access
  • CDMA Code Division Multiple Access
  • GSM Global System for Mobile
  • GPRS General Packet Radio Service
  • CDMA Global Positioning System
  • WCDMA Wide Band CDMA
  • a wireless communications device can be designed using a general purpose Digital Signal Processor (DSP) that would be programmed to realize a set of functional blocks specifying the minimum performance requirements for the application.
  • DSP Digital Signal Processor
  • system designers design algorithms (sequences of arithmetic, trigonometric, logic, control, memory access, indexing operations, and the like) to encode, transmit, and decode signals. These algorithms are typically specified in software.
  • the set of algorithms which achieve the target performance-specification is collectively referred to as the executable specification.
  • This executable specification can then be compiled and run on the DSP, typically via the use of a compiler.
  • an application-specific processor is a processor that excels in the efficient execution (power, area, flexibility) of a set of algorithms tailored to the application.
  • An application-specific processor fares extremely poorly for algorithms outside the intended application space. In other words, the improved speed and power efficiency of application-specific-processors comes at the cost of function flexibility.
  • Figure 1 illustrates, in block diagram form, a wireless communications device designed with this approach.
  • Figure 1 includes a micro-controller core 20 and a DSP 22 having access to a memory 24.
  • the wireless communications device also includes a set of application-specific fixed function circuits 26A-26D, including an AMPS circuit 26A, a CDMA circuit 26B, an IS-136 circuit 26C, and a GSM circuit 26D.
  • the method of the present invention profiles disparate communications and signal processing standards to define a programmable processor that may be programmed to execute any of the disparate communications and signal processing standards.
  • the method includes the steps of selecting a set of communications and signal processing standards for analysis and identifying functions common to the selected set of communications and signal processing standards. Thereafter, the common functions are ranked according to computational intensity. Using this ranking, a set of high computational intensity functions are selected for implementation as kernels, the set of kernels forming a programmable processor with which any one of the set of communications and signal processing standards can be implemented.
  • the invention enables the identification of optimum datapaths and control state-machines for use in the design of application-specific processors.
  • the methodology can be used to identify functions that are poorly executed by existing microprocessors and digital signal processors.
  • the technique can also define new datapaths and state-machines required to efficiently implement functions.
  • the methodology of the invention offers a systematic way to analyze functions across many applications or standards, thereby reducing the time to define a processor architecture and increasing the amount of design reuse possible in the design of new processors for digital signal processing of multi-standard applications.
  • FIGURE 1 illustrates a prior art communications and signal processing system utilizing a set of application-specific processors.
  • FIGURE 2 illustrates the steps of profiling communications and signal processing functions across multiple standards in accordance with an embodiment of the invention.
  • FIGURE 3 illustrates the canonical function blocks of a receiver.
  • FIGURE 4 illustrates a set of sub- functions for implementing a Parameter Estimator.
  • FIGURE 5 illustrates a table ranking sub-functions according to computational intensity.
  • FIGURE 6 illustrates a Kernel for implementing a function.
  • FIGURE 7A illustrates a first portion of a method of identifying the components of an add-compare-select loop of a Niterbi algorithm.
  • FIGURE 7B illustrates a second portion of a method of identifying the components of an add-compare-select loop of a Niterbi algorithm.
  • FIGURE 7C illustrates a third portion of a method of identifying the components of an add-compare-select loop of a Niterbi algorithm.
  • FIGURE 8 illustrates a method of identifying the critical sequence of operations for a Finite Impulse Response Filter (FIR).
  • FIR Finite Impulse Response Filter
  • FIGURE 9 illustrates the process of profiling canonical functions.
  • FIGURE 10 illustrates a programmable multi-standard application-specific
  • FIGURE 11 illustrates an example of necessary programmable interconnections between Kernels for a given application.
  • Figure 2 illustrates the steps 30 of the method of the present invention for profiling and analyzing functions across many signal processing applications to design a processor that can be programmed to efficiently execute the algorithms associated with any of the profiled signal processing standards or applications.
  • the process of Figure 2 will reduce the time to define a processor architecture and increases the amount of design reuse possible in the design of new processors for digital signal processing of multi-standard applications.
  • the method of the present invention begins with the selection of a set of communications and signal processing standards and services for analysis. Next, functions common to the selected set of communications and signal processing standards are identified. Thereafter, the common functions are ranked according to computational intensity and a set of high computational intensity functions are selected for implementation as programmable kernels, these kernels forming a programmable multi-standard processor.
  • a set of communications and signal processing standards are selected for analysis from the set of possible standards. Any arbitrary set of standards may be selected in compliance with the present invention; however, it is likely that the standards selected will be influenced by the target market for the programmable processor being designed. For example, the target market might be manufacturers of wireless mobile devices intended for sale in Japan.
  • Figure 3 illustrates the functional blocks when the selected application is Baseband Processor 51 of a receiver.
  • the functional blocks to be implemented are Digital Front-End Processor 52, Detector/Demodulator 54, Symbol Decoder 56, Source Decoder 58, and Parameter Estimator 60.
  • each of the selected communications and signal processing standards will specify a number of sub- functions.
  • Figure 4 which illustrates in tabular form the set of sub- functions to implement Parameter Estimator 60 for a number of standards.
  • Many Parameter Estimation sub-functions are common to multiple standards. For example, IS- 136, GSM, GPRS, EDGE, IS-95B, IS-2000 and WCDMA-FDD all use the Windowed Average Energy Estimator.
  • Figure 2 illustrates that during step 36 the functional blocks are ranked to identify functions ill-suited to realization via programming of a general purpose DSP. Stated another way, the functions are ranked to identify those suited to implementation via an application-specific multi-standard processor.
  • This is a multi-step process that begins with generating the executable specification for each function across the selected communications and signal processing standards.
  • the executable specification is coded using either the C or C++ language.
  • the executable specification for each standard may then be ranked using a number of metrics.
  • One useful metric is the computational intensity of each function.
  • the computational intensity of each function may be determined using dynamic profiling of each executable specification to quantify the associated number of millions-of-operations-per-second (MOPS). This may be done via simulations and automated test benches.
  • MOPS millions-of-operations-per-second
  • results may be presented in a table demonstrating which functions have the highest MOPS. This characterization can be made with a generic processor or with respect to a particular digital signal processor or microprocessor. If a characterization is made with respect to a specific processor, the executable specification must run on that processor for profiling purposes.
  • the table that results from this exercise shows functions for which the instruction set architecture, datapath, or memory bandwidth of the native processor is not necessarily well-suited.
  • Figure 5 illustrates a portion of such a table, which includes MOPS for a single standard and a subset of sub-functions of Baseband Processor 51 (see Fig. 3). The computational intensity of each sub-function is indicated for a subset of the channels supported by Baseband Processor 51.
  • Figure 5 indicates that the Receive (Rx) Filter is the most computationally intensive of the listed sub-functions and, as such, is the best suited for implementation in a programmable application-specific processor.
  • Figure 5 also indicates that the Complex despreader is computationally intensive and well-suited to implementation is a programmable application-specific processor.
  • Other sub-functions likely to be computationally intensive, but which are not illustrated in Figure 5, are RAKE receivers, Turbo Coders, Interference Cancellers, Multi-user Detectors and Searchers.
  • Other metrics that may be used to rank the functions across the selected set of communications and signal processing standards include power consumption and silicon area. Determining the power consumption of each function requires identifying the amount of time spent by the function on each of a set of operation types.
  • the set of operation types includes move-and-transfer, loop-and-control, trigonometric and arithmetic. Each type of operation consumes some number of mW per operation. Thus, given the number of operations of each type the total power consumption of each function can be determined across the selected set of communications and signal processing standards. Such an analysis is likely to reveal that RAKE receivers tend to consume a great deal of power as compared to other sub-functions.
  • the silicon area required to store the executable code can be estimated for each function across the selected set of communications and signal processing standards by counting the number and types of operations required for each of the executable specifications, and then using a cost table showing the cost in silicon areas for each operator.
  • RAKE receivers are likely to require many more gates to store their executable code than are other sub-Functions.
  • kernel means a sequence of operations that may be represented by a control-dataflow graph and may be implemented in either software or hardware.
  • Figure 6 illustrates, in block diagram form, Kernel 65, which includes three modules: a Sequencer 66, a local Memory 67, and a parameterizable, configurable Arithmetic Logic Unit 68.
  • a function-centric, rather than an application-centric, approach is taken to profile functions.
  • the profiling of the functions begins with an executable specification of each
  • inventions of functions include identification of critical sequences of operations. Sequences of operations may involve move-and-transfer, loop- and-control, trigonometric or arithmetic operations.
  • critical sequences of operations, or components are those sequences of operations whose timely completion is necessary to performing a canonical function in a fixed period of time.
  • Figures 7A-7C illustrate a method of identifying the components of an add-compare-select loop of a machine implemented Niterbi algorithm.
  • a machine implemented Viterbi algorithm is a dynamic-programming algorithm employed in digital communications to find the most likely sequence of transmitted symbols in a digital transmission system.
  • Figure 7A describes the first two steps of a computer implemented Niterbi algorithm.
  • Figure 7B illustrates the third step of a machine implemented Niterbi algorithm, the add- compare recursion, which includes a compute stage and a survivor storage stage.
  • Figure 7C illustrates the data flow and control flow of the add-compare-select recursion of the computer implemented Niterbi algorithm.
  • Figure 7C shows the loop with the sequence of operations that are used during the recursion and the relationship between the sequence of operations for one iteration of the computer implemented Niterbi algorithm.
  • Figure 8 illustrates a machine implemented method of identifying the critical sequence of operations for a Finite Impulse Response Filter (FIR).
  • FIR Finite Impulse Response Filter
  • the illustrated equation describes mathematically the convolution of an input sequence x(n) with a set of filter coefficients a(n) .
  • the structure illustrated beneath the equation in Figure 8 illustrates the most common subset of data flow and control flow operations in realization of the FIR.
  • Highlighting in Figure 8 illustrates the all the computation required for a single stage of the FIR.
  • the canonical functions are analyzed across multiple standards to identify the components that are common across all instances of the function, and those components that are variable. The process of profiling canonical functions is more fully appreciated with reference to Figure 9.
  • Baseband Processor 51 A function profile for a particular application, in this case Baseband Processor 51 , is listed on the left of Figure 9.
  • the canonical functions of Baseband Processor 51 include an MPSK frequency estimator, a convolutional decoder, a rake receiver, and an MLSE equalization unit.
  • Figure 9 represents as rectangles the Functional Component Collections 70a-g, 72a-d, 74a-d and 76a-b which make up each canonical function.
  • Each rectangular Functional Component Collection is divided into a multiplicity of squares, with each square representing a single Component 71 &73. While Functional Component Collections 70, 72, 74 & 76 are illustrated as including six Components 71 &73, the number of Components 71 &73 per Functional Component Collection varies with each canonical function. For each Functional Component Collection 70, 72, 74 & 76 an arbitrary number of Components 71 &73 are included for purposes of illustration.
  • a single set of partially programmable Kernels 82 may be designed to support all Functional Component Collections 72a-72d associated with the Convolutional Decoder function; a single set of partially programmable Kernels 84 may be designed to supportthe Functional Component Collections 74a-74d associated with the Rake Receiver Function; and a single set of partially programmable Kernels 86 may be designed to support the Functional Component Collections 76a-76b associated with the MLSE Equalization function.
  • a Kernel 65 includes three modules 66, 67, 68, which form a computational unit.
  • Sequencer 66 and ALU 68 are partially programmable.
  • those programmable parts of Sequencer 66 and ALU form the programmable computation unit
  • Memory 67 and the fixed parts of Sequencer 66 and ALU 68 form the fixed computation unit.
  • Engine 90 is a standard-independent, CDMA-specific processor that includes a set of partially programmable set of Kernels for each canonical function of an application.
  • Engine 90 may include, as an example, partially programable set of Kernels 78, 82, 84 and 86.
  • Engine 92 is a standard-independent, TDMA-specific processor that includes a set of partially programmable set of Kernels for each canonical function of an application.
  • a multi-standard, protocol independent Engine 94 may be designed.
  • FIG. 10 illustrates, in block diagram form, a programmable, multi-standard, application-specific Processor 100.
  • Processor 100 includes Program Control Unit 102, a Kernel Bank 104, and Reconfigurable Data Router 106.
  • Program Control Unit 102 controls the programming of Kernel Bank 104 and Reconfigurable Data Router 106 so that Processor 100 may be configured to support any one of a set of supported standards.
  • Program Control Unit 102 includes Memory 110, which stores executive code for programming Controller 112 and Bus Manager 114. Controller 112 controls the programming of the programmable units within each Kernel of Kernel Bank 104, while Bus Manager 144 controls the configuration of Reconfigurable Data Router 106.
  • Kernel Bank 104 includes a multiplicity of Kernels, one for each canonical function of the application.
  • Reconfigurable Data Router 106 routes data between Kernels as necessary to implement the application according to a particular standard.
  • Reconfigurable Data Router 106 need not be completely programmable.
  • Figure 11 is an example of the interconnections between Kernels that must be programmable for a given application. The Kernels of the application are listed both at the top and to the left of Figure 11. Interconnections that must be supported for the application are indicated by an x. For each Kernel there are relatively few interconnections that must be supported.
  • the Turbo Decoder Core kernel need only be capable of connecting to the Convolutional Decoder Core Unit kernel and the Memory Management Unit kernel.
  • the invention provides a systematic method for dealing with designing processors for multiple standards, multiple functions, and multiple parameters.
  • the technique of the invention reduces processor design cycle time via function profiling and definition of datapath and control state- machine engines that can be reused across many processors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Transceivers (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

L'invention concerne un procédé d'établissement de profils de communications disparates et de normes de traitement de signaux consistant à sélectionner un ensemble de normes à analyser (32), puis à identifier (34) et classer (36) les fonctions assumées par l'ensemble des normes, à exécuter un ensemble des fonctions les mieux classées comme noyaux (38), l'ensemble de noyaux formant un processeur programmable permettant la réalisation d'un des ensembles de normes (42) de traitement de signaux et de communication.
EP00935876A 1999-05-07 2000-05-05 Procede d'etablissement de profils de communications disparates, de normes de traitement de signaux et de services Withdrawn EP1177700A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13313099P 1999-05-07 1999-05-07
US133130P 1999-05-07
PCT/US2000/012474 WO2000069192A1 (fr) 1999-05-07 2000-05-05 Procede d'etablissement de profils de communications disparates, de normes de traitement de signaux et de services

Publications (1)

Publication Number Publication Date
EP1177700A1 true EP1177700A1 (fr) 2002-02-06

Family

ID=22457152

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00935876A Withdrawn EP1177700A1 (fr) 1999-05-07 2000-05-05 Procede d'etablissement de profils de communications disparates, de normes de traitement de signaux et de services

Country Status (6)

Country Link
EP (1) EP1177700A1 (fr)
JP (1) JP2003527768A (fr)
KR (1) KR100743882B1 (fr)
AU (1) AU5127200A (fr)
CA (1) CA2371140A1 (fr)
WO (1) WO2000069192A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278726B1 (en) 1999-09-10 2001-08-21 Interdigital Technology Corporation Interference cancellation in a spread spectrum communication system
US6115406A (en) 1999-09-10 2000-09-05 Interdigital Technology Corporation Transmission using an antenna array in a CDMA communication system
US6839830B2 (en) 2000-03-01 2005-01-04 Realtek Semiconductor Corporation Logical pipeline for data communications system
AU2001286410A1 (en) 2000-07-31 2002-02-13 Morphics Technology, Inc. Method and apparatus for time-sliced and multi-threaded data processing in a communication system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922412A (en) * 1986-10-09 1990-05-01 The Babcock & Wilcox Company Apparatus and method using adaptive gain scheduling
FR2678400B1 (fr) * 1991-06-27 1995-08-04 Texas Instruments France Processeur de protocole destine a l'execution d'un ensemble d'instructions en un nombre reduit d'operation.
AUPM414394A0 (en) * 1994-02-28 1994-03-24 Voxson International Pty. Limited Multi-mode communications system
US5664004A (en) * 1995-01-13 1997-09-02 Nokia Telecommunications Oy Support of multiplicity of radio interfaces over an interface between a base station system and a mobile switch
US5956651A (en) * 1996-09-30 1999-09-21 Qualcomm Incorporated Cellular telephone interface system for AMPS and CDMA data services

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0069192A1 *

Also Published As

Publication number Publication date
WO2000069192A9 (fr) 2002-06-13
CA2371140A1 (fr) 2000-11-16
WO2000069192A1 (fr) 2000-11-16
KR100743882B1 (ko) 2007-07-30
AU5127200A (en) 2000-11-21
JP2003527768A (ja) 2003-09-16
KR20020011408A (ko) 2002-02-08

Similar Documents

Publication Publication Date Title
US6967999B2 (en) Method and apparatus to support multi standard, multi service base-stations for wireless voice and data networks
JP3202750B2 (ja) 特定用途向けプロセッサおよびその設計方法
US20120173864A1 (en) Flexible multi-processing system
US7373121B1 (en) Apparatus and method for processing a deterministic data flow associated with a wireless communication signal
TWI469584B (zh) 用於在無線通訊系統中處理透過通道所傳送的信號之方法與接收器
US8526965B2 (en) Distributed micro instructions set processor architecture for high-efficiency signal processing
US6807155B1 (en) Method of profiling disparate communications and signal processing standards and services
Kaiser et al. Prototyping for MIMO systems-an overview
WO2000069084A9 (fr) Dispositif de communication numerique sans fil reprogrammable et procede de fonctionnement
EP1177700A1 (fr) Procede d'etablissement de profils de communications disparates, de normes de traitement de signaux et de services
EP1317832B1 (fr) Procede et appareil pour un traitement de donnees a tranche de temps et multifiliere dans un systeme de communication
KR100784412B1 (ko) 개선된 멀티-스레드 신호처리 방법 및 장치
KNEIP et al. Single chip programmable baseband ASSP for 5 GHz wireless LAN applications
Becker et al. Parametric design for reconfigurable software-defined radio
Guo et al. Rapid scheduling of efficient VLSI architectures for next-generation HSDPA wireless system using Precision C synthesizer
Boyapati et al. A comparison of DSP, ASIC, and RISC DSP based implementations of multiple access in LTE
Bluethgen et al. A programmable baseband platform for software-defined radio
Pulley et al. Software defined baseband processing for 3G base stations
Harju et al. A programmable baseband receiver platform for WCDMA/OFDM mobile terminals
Nilsson Design of programmable multi-standard baseband processors
Harju Programmable receiver architectures for multimode mobile terminals
Lin et al. A programmable Vector coprocessor architecture for wireless applications
Rounioja et al. Implementation of an hsdpa receiver with a customized vector processor
Lee et al. Reducing idle mode power in software defined radio terminals
Nilsson et al. A fully programmable Rake-receiver architecture for multi-standard baseband processors

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20011122

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20080207