EP1159763A1 - Multi-layer diodes and method of producing same - Google Patents

Multi-layer diodes and method of producing same

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Publication number
EP1159763A1
EP1159763A1 EP00915114A EP00915114A EP1159763A1 EP 1159763 A1 EP1159763 A1 EP 1159763A1 EP 00915114 A EP00915114 A EP 00915114A EP 00915114 A EP00915114 A EP 00915114A EP 1159763 A1 EP1159763 A1 EP 1159763A1
Authority
EP
European Patent Office
Prior art keywords
layer
grooves
multilayer
arrangement
multilayer arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00915114A
Other languages
German (de)
French (fr)
Inventor
Richard Spitz
Alfred Goerlach
Barbara Will
Helga Uebbing
Ning Qu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
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Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1159763A1 publication Critical patent/EP1159763A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0817—Thyristors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0839—Cathode regions of thyristors

Definitions

  • Multi-layer diodes and method for producing multi-layer diodes are Multi-layer diodes and method for producing multi-layer diodes
  • the invention is based on a method for producing multilayer diodes or thyristors according to the preamble of the independent claim. From the book "Power Semiconductor Devices" by B. Jayant Baliga, 1995, ISBN number 0-534-94098-6, PS Publishing Company, page 266, thyristors with an emitter short-circuit structure are already known, in which the top heavily n-doped layer the multilayer arrangement is limited to defined areas on the surface by photolithography.
  • features of the independent claim have the advantage of providing an emitter short-circuit structure which can be produced in a simple manner and in parallel with notches for separating the diodes or thyristors from the wafer used.
  • the diffused layers also have a high degree of homogeneity due to their lateral extension over the entire silicon wafer, which means that high yield is achieved in the manufacture of individual diodes or thyristors.
  • FIG. 1 shows a silicon wafer
  • FIG. 2 shows a silicon wafer with notches
  • FIG. 3 shows a silicon wafer immediately before it is cut into individual chips.
  • Figure 1 shows the side view of part of a
  • Silicon wafers 1 with a diameter of 125 millimeters and a thickness of 200 micrometers. It shows a layer arrangement 2, 3, 4, 5. Before the layer arrangement was introduced, the (raw) wafer had a phosphorus doping of approximately 2.5 ⁇ 10 17 atoms per cubic centimeter.
  • an approximately 2 micrometer thick glass layer with approximately 3.2 percent by weight boron is first deposited on both sides of the raw wafer.
  • the separation takes place by chemical Steam separation Chemical Vapor Deposition ("CVD"), from borosilane under atmospheric pressure (Atmospheric Pressure CVD, "APCVD").
  • APCVD Admospheric Pressure CVD
  • a first diffusion step follows in order to drive the boron into the silicon wafer.
  • the diffusion time is approx. 28 hours at a temperature of approx. 1265 degrees Celsius in an oxidizing atmosphere.
  • the glass layers on both sides of the wafer are removed by immersing them in fifty percent hydrofluoric acid.
  • an approximately 1.6 micron thick glass layer which contains 6.5 percent by weight phosphorus, is deposited again on APCVD on one side of the wafer, which is now referred to as the front side, to produce the n-doped top layer 2.
  • Phosphorus silane can be used as the gas.
  • a 3 micron thick glass layer with 5 percent by weight boron is applied to the back of the wafer opposite the front side with APCVD.
  • the dopants applied to the front and the back in this and in the previously described coating step are then driven in a further diffusion step at 1265 degrees Celsius for 15 hours under an oxidizing atmosphere.
  • the glass layers on both sides of the wafer are removed again by immersion in fifty percent hydrofluoric acid.
  • the silicon wafer is now in the layer sequence shown in FIG. 1, the heavily n-doped layer 2 having a thickness of 20 micrometers, the p doped layer 3 has a thickness of 45 micrometers and the heavily p-doped layer 5 has a thickness of 50 micrometers.
  • the n-doped layer 4 has the doping of the raw wafer used.
  • FIG. 2 shows the silicon wafer 1 with grooves 10 made therein in a cross-sectional side view.
  • the distance between the parallel grooves is optionally in a range between 2 and 3 millimeters, in particular in a range from 2.2 to 2.6 millimeters, the groove depth is approximately
  • a second group of grooves is arranged at an angle of approximately 90 degrees to the grooves shown in FIG. 2, so that the front is divided into rectangular, in particular square, areas.
  • metal layers are sputtered on both sides of the wafer simultaneously, first a 70 nanometer thick chrome layer, followed by a 160 nanometer thick nickel-vanadium layer and a 100 nanometer thick silver layer.
  • FIG. 3 shows the silicon wafer with applied metal layers, the metal layer on the back forming the rear contact 21 and the metal layer on the front forming the emitter short-circuit contact 20.
  • Emitter short-circuit contact closes the top strongly n doped layer 2 with the underlying p-doped layer 3 short.
  • the wafer is cut, for example, along every second groove, or, as shown in FIG. 3, along every third groove, in each case in the middle of the groove along the dividing lines 25 by a sawing step. If the wafer is diced along every second groove, the dicing results in chips with individual four-layer diodes (thyristor diodes) with chip dimensions of approximately 4.5 by 4.5 millimeters.
  • Break voltage 49 to 52 volts
  • break current 0.8 to 1.2 amps.
  • three-layer diodes (transistor diodes) with an n + / n / p / n + layer sequence can also be produced.
  • the only difference from the manufacturing process described is that an approximately 1.6 micron thick glass layer with 6.5% by weight phosphorus (instead of boron) is deposited on the back of the wafer during the coating steps.
  • the thickness of the rear, heavily n-doped layer is approximately 50 micrometers.
  • Typical electrical parameters for the three-layer diodes are: Break voltage: 49 to 52 volts, break current: 0.8 to 1.2 amps,
  • the described method can also be carried out with other steps which likewise lead to the layer arrangements described (for example layer arrangement 2, 3, 4, 5). Pay for this, for example
  • thyristors differ from four-layer diodes essentially by an additional gate connection. It is thus possible, with small changes in the production method described, to also produce thyristors which have an emitter short circuit implemented by a groove.

Abstract

According to the invention the emitter short-circuit structure of a multi-layer diode is embodied by grooves which separate the top layer (2) of the multi-layer diode. A metal layer (20) deposited thereon electrically short-circuits the top layer and the layer (3) situated below it.

Description

Mehrschichtdioden sowie Verfahren zur Herstellung von MehrschichtdiodenMulti-layer diodes and method for producing multi-layer diodes
Stand der TechnikState of the art
Die Erfindung geht aus von einem Verfahren zur Herstellung von Mehrschichtdioden beziehungsweise Thyristoren nach der Gattung des unabhängigen Anspruchs. Aus dem Buch „Power Semiconductor Devices" von B. Jayant Baliga, 1995, ISBN- Nummer 0-534-94098-6, P S Publishing Company, Seite 266, sind bereits Thyristoren mit Emitterkurzschlußstruktur bekannt, bei denen die oberste stark n-dotierte Schicht der Mehrschichtanordnung durch Fotolitografie auf festgelegte Bereiche an der Oberfläche begrenzt ist.The invention is based on a method for producing multilayer diodes or thyristors according to the preamble of the independent claim. From the book "Power Semiconductor Devices" by B. Jayant Baliga, 1995, ISBN number 0-534-94098-6, PS Publishing Company, page 266, thyristors with an emitter short-circuit structure are already known, in which the top heavily n-doped layer the multilayer arrangement is limited to defined areas on the surface by photolithography.
Vorteile der ErfindungAdvantages of the invention
Das erfindungsgemäße Verfahren mit den kennzeichnendenThe inventive method with the characteristic
Merkmalen des unabhängigen Anspruchs hat demgegenüber den Vorteil, eine Emitterkurzschlußstruktur bereitzustellen, die in einfacher Weise und parallel mit Einkerbungen zum Vereinzeln der Dioden bzw. Thyristoren aus dem verwendeten Wafer herstellbar ist. Die diffundierten Schichten weisen überdies aufgrund ihrer lateralen Erstreckung über den ganzen Siliziumwafer eine hohe Homogenität auf, wodurch eine hohe Ausbeute bei der Herstellung einzelner Dioden beziehungsweise Thyristoren erzielt wird.In contrast, features of the independent claim have the advantage of providing an emitter short-circuit structure which can be produced in a simple manner and in parallel with notches for separating the diodes or thyristors from the wafer used. The diffused layers also have a high degree of homogeneity due to their lateral extension over the entire silicon wafer, which means that high yield is achieved in the manufacture of individual diodes or thyristors.
Durch die in den abhängigen Ansprüchen und in der Beschreibung aufgeführten Maßnahmen sind vorteilhafte Weiterbildungen und Verbesserungen des im unabhängigen Anspruch angegebenen Verfahrens möglich.The measures listed in the dependent claims and in the description make advantageous developments and improvements of the method specified in the independent claim possible.
Zeichnungdrawing
Ausführungsbeispiele der Erfindung sind in der Zeichnung dargestellt und werden in der nachfolgenden Beschreibung näher erläutert. Figur 1 zeigt einen Siliziumwafer, Figur 2 einen Siliziumwafer mit Einkerbungen und Figur 3 einen Siliziumwafer unmittelbar vor dem Zerteilen in einzelne Chips .Exemplary embodiments of the invention are shown in the drawing and are explained in more detail in the following description. FIG. 1 shows a silicon wafer, FIG. 2 shows a silicon wafer with notches and FIG. 3 shows a silicon wafer immediately before it is cut into individual chips.
Beschreibung der AusführungsbeispieleDescription of the embodiments
Figur 1 zeigt die Seitenansicht eines Teils einesFigure 1 shows the side view of part of a
Siliziumwafers 1 mit einem Durchmesser von 125 Millimetern und einer Dicke von 200 Mikrometern. Er zeigt eine Schichtanordnung 2 , 3 , 4 , 5. Vor dem Einbringen der Schichtanordnung hat der (Roh-)Wafer eine Phosphordotierung von ca. 2,5 x 10 17 Atomen pro Kubikzentimeter aufgewiesen.Silicon wafers 1 with a diameter of 125 millimeters and a thickness of 200 micrometers. It shows a layer arrangement 2, 3, 4, 5. Before the layer arrangement was introduced, the (raw) wafer had a phosphorus doping of approximately 2.5 × 10 17 atoms per cubic centimeter.
Im folgenden wird die Herstellung der Schichtanordnung beschrieben.The production of the layer arrangement is described below.
Auf beiden Seiten des Rohwafers wird zunächst zur Erzeugung der p-dotierten Schichten 5 und 3 eine ca. 2 Mikrometer dicke Glasschicht mit ca. 3,2 Gewichtsprozent Bor abgeschieden. Die Abscheidung erfolgt durch chemische Dampfabscheidung, engl . Chemical Vapor Deposition („CVD"), aus Borsilan unter Atmosphärendruck (Atmospheric Pressure CVD, „APCVD") . Nach diesem Belegungsschritt folgt ein erster Diffusionsschritt, um das Bor in den Siliziumwafer einzutreiben. Die Diffusionszeit beträgt ca. 28 Stunden bei einer Temperatur von ca. 1265 Grad Celsius unter oxidierender Atmosphäre. Nach diesem Diffusionsschritt werden die Glasschichten auf beiden Waferseiten durch Eintauchen in fünfzigprozentige Flußsäure entfernt.To produce the p-doped layers 5 and 3, an approximately 2 micrometer thick glass layer with approximately 3.2 percent by weight boron is first deposited on both sides of the raw wafer. The separation takes place by chemical Steam separation Chemical Vapor Deposition ("CVD"), from borosilane under atmospheric pressure (Atmospheric Pressure CVD, "APCVD"). After this assignment step, a first diffusion step follows in order to drive the boron into the silicon wafer. The diffusion time is approx. 28 hours at a temperature of approx. 1265 degrees Celsius in an oxidizing atmosphere. After this diffusion step, the glass layers on both sides of the wafer are removed by immersing them in fifty percent hydrofluoric acid.
In einem weiteren Schritt wird auf einer Seite des Wafers, die nunmehr als Vorderseite bezeichnet wird, zur Erzeugung der n-dotierten obersten Schicht 2 wieder über APCVD eine ca. 1,6 Mikrometer dicke Glasschicht, die 6,5 Gewichtsprozent Phosphor enthält, abgeschieden. Als Gas ist Phosphorsilan verwendbar.In a further step, an approximately 1.6 micron thick glass layer, which contains 6.5 percent by weight phosphorus, is deposited again on APCVD on one side of the wafer, which is now referred to as the front side, to produce the n-doped top layer 2. Phosphorus silane can be used as the gas.
Zur weiteren Ausbildung der p-dotierten Schicht 5 wird in einem weiteren Schritt auf die der Vorderseite gegenüberliegenden Rückseite des Wafers mit APCVD eine 3 Mikrometer dicke Glasschicht mit 5 Gewichtsprozent Bor aufgebracht . Die auf der Vorder- und der Rückseite in diesem und im zuvor beschriebenen Belegungsschritt aufgebrachten Dotierstoffe werden nun in einem weiteren Diffusionsschritt bei 1265 Grad Celsius 15 Stunden lang unter oxidierender Atmosphäre eingetrieben. Nach diesem Diffusionsschritt werden die Glasschichten auf beiden Waferseiten wieder durch Eintauchen in fünfzigprozentige Flußsäure entfernt.To further develop the p-doped layer 5, in a further step a 3 micron thick glass layer with 5 percent by weight boron is applied to the back of the wafer opposite the front side with APCVD. The dopants applied to the front and the back in this and in the previously described coating step are then driven in a further diffusion step at 1265 degrees Celsius for 15 hours under an oxidizing atmosphere. After this diffusion step, the glass layers on both sides of the wafer are removed again by immersion in fifty percent hydrofluoric acid.
Nunmehr liegt der Siliziumwafer in der in Figur 1 dargestellten Schichtenfolge vor, wobei die stark n-dotierte Schicht 2 ein Dicke von 20 Mikrometern aufweist, die p- dotierte Schicht 3 eine Dicke von 45 Mikrometern und die stark p-dotierte Schicht 5 eine Dicke von 50 Mikrometern. Die n-dotierte Schicht 4 weist die Dotierung des verwendeten Rohwafers auf .The silicon wafer is now in the layer sequence shown in FIG. 1, the heavily n-doped layer 2 having a thickness of 20 micrometers, the p doped layer 3 has a thickness of 45 micrometers and the heavily p-doped layer 5 has a thickness of 50 micrometers. The n-doped layer 4 has the doping of the raw wafer used.
In einem weiteren Schritt werden Rillen in die Schicht 2 eingebracht, beispielsweise durch Sägen mit einer Diamantsäge, so daß der Rillengrund jeweils in der Schicht 3 liegt, so daß die Schicht 2 im Bereich der Rillen vollständig durchtrennt ist. Figur 2 zeigt den Siliziumwafer 1 mit darin eingebrachten Rillen 10 in Querschnittsseitenansicht. Der Abstand der parallel verlaufenden Rillen liegt wahlweise in einem Bereich zwischen 2 und 3 Millimetern, insbesondere in einem Bereich von 2,2 bis 2,6 Millimetern, die Rillentiefe beträgt zirkaIn a further step, grooves are introduced into layer 2, for example by sawing with a diamond saw, so that the groove base lies in layer 3, so that layer 2 is completely severed in the region of the grooves. FIG. 2 shows the silicon wafer 1 with grooves 10 made therein in a cross-sectional side view. The distance between the parallel grooves is optionally in a range between 2 and 3 millimeters, in particular in a range from 2.2 to 2.6 millimeters, the groove depth is approximately
30 Mikrometer. Dabei wird unter einem Winkel von ca. 90 Grad zu den in Figur 2 ersichtlichen Rillen eine zweite Gruppe von Rillen angeordnet, so daß die Vorderseite in rechteckige, insbesondere quadratische, Bereiche aufgeteilt wird.30 microns. A second group of grooves is arranged at an angle of approximately 90 degrees to the grooves shown in FIG. 2, so that the front is divided into rectangular, in particular square, areas.
In einem weiteren Schritt werden simultan auf beiden Seiten des Wafers Metallschichten aufgesputtert , zunächst eine 70 Nanometer dicke Chromschicht, gefolgt von einer 160 Nanometer dicken Nickel -Vanadium-Schicht und einer 100 Nanometer dicken Silberschicht. Figur 3 zeigt den Siliziumwafer mit aufgebrachten Metallschichten, wobei die Metallschicht auf der Rückseite den Rückseitenkontakt 21 und die Metallschicht auf der Vorderseite den Emitterkurzschlußkontakt 20 bildet. DerIn a further step, metal layers are sputtered on both sides of the wafer simultaneously, first a 70 nanometer thick chrome layer, followed by a 160 nanometer thick nickel-vanadium layer and a 100 nanometer thick silver layer. FIG. 3 shows the silicon wafer with applied metal layers, the metal layer on the back forming the rear contact 21 and the metal layer on the front forming the emitter short-circuit contact 20. The
Emitterkurzschlußkontakt schließt die oberste stark n- dotierte Schicht 2 mit der darunterliegenden p-dotierten Schicht 3 kurz.Emitter short-circuit contact closes the top strongly n doped layer 2 with the underlying p-doped layer 3 short.
In einem weiteren Schritt wird der Wafer beispielsweise entlang jeder zweiten Rille, oder, wie in Figur 3 gezeigt, entlang jeder dritten Rille, jeweils in der Rillenmitte entlang der Zerteilungslinien 25 durch einen Sägeschritt zerteilt. Wird der Wafer entlang jeder zweiten Rille zerteilt, so ergeben sich durch die Zerteilung Chips mit einzelnen Vierschichtdioden (Thyristordioden) mit Chipmaßen von zirka 4,5 mal 4,5 Millimetern.In a further step, the wafer is cut, for example, along every second groove, or, as shown in FIG. 3, along every third groove, in each case in the middle of the groove along the dividing lines 25 by a sawing step. If the wafer is diced along every second groove, the dicing results in chips with individual four-layer diodes (thyristor diodes) with chip dimensions of approximately 4.5 by 4.5 millimeters.
Die Chips werden anschließend in an sich bekannte Einpreßdiodengehäuse eingelötet und mit Epoxidharz vergossen. Typische elektrische Kenngrößen für die Vierschichtdioden sind:The chips are then soldered into known press-in diode housings and cast with epoxy resin. Typical electrical parameters for the four-layer diodes are:
Kippspannung: 49 bis 52 Volt, Kippstrom: 0,8 bis 1,2 Ampere.Break voltage: 49 to 52 volts, break current: 0.8 to 1.2 amps.
In analoger Weise zu Vierschichtdioden können auch Dreischichtdioden (Transistordioden) mit einer n+/n/p/n+ - Schichtenfolge hergestellt werden. Der einzige Unterschied zum beschriebenen Herstellungsverfahren besteht darin, daß bei den Belegungsschritten auf der Rückseite des Wafers eine zirka 1,6 Mikrometer dicke Glasschicht mit 6,5 Gewichtsprozent Phosphor (statt Bor) abgeschieden wird. Nach dem zweiten Diffusionsschritt beträgt die Dicke der rückseitigen, stark n-dotierten Schicht analog zur vorgenannten Schicht 5 zirka 50 Mikrometer. Typische elektrische Kenngrößen für die Dreischichtdioden sind: Kippspannung: 49 bis 52 Volt, Kippstrom: 0,8 bis 1,2 Ampere,Analogous to four-layer diodes, three-layer diodes (transistor diodes) with an n + / n / p / n + layer sequence can also be produced. The only difference from the manufacturing process described is that an approximately 1.6 micron thick glass layer with 6.5% by weight phosphorus (instead of boron) is deposited on the back of the wafer during the coating steps. After the second diffusion step, the thickness of the rear, heavily n-doped layer, analogous to the aforementioned layer 5, is approximately 50 micrometers. Typical electrical parameters for the three-layer diodes are: Break voltage: 49 to 52 volts, break current: 0.8 to 1.2 amps,
Flußspannung: 1,5 bis 2,0 Volt bei einem Strom von 100Forward voltage: 1.5 to 2.0 volts at a current of 100
Ampere in Durchlaßrichtung.Forward ampere.
Das beschriebene Verfahren kann in alternativen Ausfuhrungsformen auch mit anderen Schritten durchgeführt werden, die ebenfalls zu den beschriebenen Schichtanordnungen (zum Beispiel der Schichtanordnung 2, 3, 4, 5) fuhren. Dazu zahlen beispielsweiseIn alternative embodiments, the described method can also be carried out with other steps which likewise lead to the layer arrangements described (for example layer arrangement 2, 3, 4, 5). Pay for this, for example
Foliendiffusions erfahren, Gasphasenbelegungsverfahren und/oder Ionenimplantationsverfahren. Ferner wird durch Variation der Chipmaße, der Rillentiefen, des Rillenmusters sich kreuzender Rillen, der Schichtdicken oder der Kennwerte des Rohwafers eine Variation der elektrischen Kenngroßen der Dioden ermöglicht. Wie aus der in der Beschreibungseinleitung genannten Literaturstelle ersichtlich, unterscheiden sich Thyristoren von Vierschichtdioden im wesentlichen durch einen zusätzlichen Gateanschluß. Somit ist es möglich, mit kleinen Änderungen des beschriebenen Herstellungsverfahrens auch Thyristoren herzustellen, die einen durch eine Rille realisierten Emitterkurzschluß aufweisen. Experience film diffusion, gas phase allocation process and / or ion implantation process. Furthermore, variation of the chip dimensions, the groove depths, the groove pattern of intersecting grooves, the layer thicknesses or the characteristic values of the raw wafer enables a variation of the electrical characteristics of the diodes. As can be seen from the literature cited in the introduction to the description, thyristors differ from four-layer diodes essentially by an additional gate connection. It is thus possible, with small changes in the production method described, to also produce thyristors which have an emitter short circuit implemented by a groove.

Claims

Ansprüche Expectations
1. Verfahren zur Herstellung von Mehrschichtdioden oder Thyristoren mit Emitterkurzschlußstruktur, bei dem in einem ersten Schritt aus einem Halbleiterwafer (1) eine Mehrschichtanordnung (2,3,4,5) erzeugt wird, dadurch gekennzeichnet, daß1. A method for producing multilayer diodes or thyristors with an emitter short-circuit structure, in which, in a first step, a multilayer arrangement (2, 3, 4, 5) is produced from a semiconductor wafer (1), characterized in that
in einem weiteren Schritt Rillen auf einer Vorderseite der Mehrschichtanordnung eingesägt werden, so daß die oberste Schicht (2) der Mehrschichtanordnung (2, 3, 4, 5) durchtrennt wird,in a further step, grooves are sawn in on a front side of the multilayer arrangement, so that the uppermost layer (2) of the multilayer arrangement (2, 3, 4, 5) is severed,
in einem weiteren Schritt ein Rückseitenkontakt (21) auf der der Vorderseite gegenüberliegenden Rückseite der Mehrschichtanordnung sowie ein Emitterkurzschlußkontakt (20) auf der Vorderseite aufgebracht werden, so daß die oberste Schicht (2) und die darunterliegende Schicht (3) kurzgeschlossen werden,in a further step, a rear side contact (21) is applied to the rear side of the multilayer arrangement opposite the front side, and an emitter short-circuit contact (20) is applied to the front side, so that the top layer (2) and the layer below (3) are short-circuited,
und in einem weiteren Schritt die Mehrschichtanordnung entlang eines Teils der eingesägten Rillen zerteilt wird zur Erzeugung vereinzelter Mehrschicht-Chips, so daß zusätzlich zu den Rillen, entlang derer die Zerteilung erfolgt, jederand in a further step the multi-layer arrangement is cut along a part of the sawn-in grooves to produce individual multi-layer chips, so that in addition to the grooves along which the cutting takes place, each
Mehrschicht-Chip zumindest eine weitere vom Zerteilen nicht beanspruchte Rille aufweist. Multilayer chip has at least one further groove that is not claimed by the cutting.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Rillen äquidistant angeordnet werden.2. The method according to claim 1, characterized in that the grooves are arranged equidistant.
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß zwei Gruppen von Rillen angeordnet werden, die sich unter einem Winkel von ca. 90 Grad schneiden, so daß die Vorderseite in rechteckige, insbesondere quadratische, Bereiche aufgeteilt wird.3. The method according to claim 1 or 2, characterized in that two groups of grooves are arranged which intersect at an angle of approximately 90 degrees, so that the front is divided into rectangular, in particular square, areas.
4. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß für die oberste Schicht (2) eine Dicke von zirka 20 Mikrometern, für die darunterliegende Schicht (3) eine Dicke von zirka 45 Mikrometern und für die Rillen eine Tiefe von zirka 30 Mikrometern gewählt wird.4. The method according to any one of the preceding claims, characterized in that for the top layer (2) a thickness of about 20 microns, for the underlying layer (3) a thickness of about 45 microns and for the grooves a depth of about 30 microns is chosen.
5. Verfahren nach Anspruch 3 und 4, dadurch gekennzeichnet, daß die Rillen jeder Gruppe in einem Abstand von zirka 2,5 mm angeordnet werden.5. The method according to claim 3 and 4, characterized in that the grooves of each group are arranged at a distance of about 2.5 mm.
6. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Mehrschichtanordnung in einem chemischen Dampfabscheideverfahren, insbesondere in einem APCVD-Verfahren, erzeugt wird.6. The method according to any one of the preceding claims, characterized in that the multilayer arrangement is produced in a chemical vapor deposition process, in particular in an APCVD process.
7. Verfahren nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, daß die Mehrschichtanordnung in einem Foliendiffusionsverfahren, einem Gasphasenbelegungsverfahren und/oder mittels eines Ionenimplantationsverfahrens erzeugt wird. 7. The method according to any one of claims 1 to 5, characterized in that the multilayer arrangement is produced in a film diffusion process, a gas phase coating process and / or by means of an ion implantation process.
EP00915114A 1999-02-26 2000-02-24 Multi-layer diodes and method of producing same Withdrawn EP1159763A1 (en)

Applications Claiming Priority (3)

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DE19908399 1999-02-26
DE19908399A DE19908399B4 (en) 1999-02-26 1999-02-26 Process for the production of multilayer diodes or thyristors with an emitter short-circuit structure
PCT/DE2000/000508 WO2000052761A1 (en) 1999-02-26 2000-02-24 Multi-layer diodes and method of producing same

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DE19938209B4 (en) * 1999-08-12 2007-12-27 Robert Bosch Gmbh Semiconductor device and method of manufacture
NL1019613C2 (en) * 2001-12-19 2003-06-20 Micronit Microfluidics Bv Method for dividing a substrate into a number of individual chip parts.

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US3706129A (en) * 1970-07-27 1972-12-19 Gen Electric Integrated semiconductor rectifiers and processes for their fabrication
JPS5310279A (en) * 1976-07-16 1978-01-30 Mitsubishi Electric Corp Mesa type semiconductor device
DE2815606A1 (en) * 1978-04-11 1979-10-31 Fiz Tekhn I Im A F Joffe Akade Thyristor with differently doped base layers - has specified mean impurities concentration in higher doped base layer and matrix of shunt channels of specified width
JPS5526690A (en) * 1978-08-16 1980-02-26 Nec Corp Manufacturing semiconductor device
JPS58174A (en) * 1981-06-24 1983-01-05 Mitsubishi Electric Corp Monolithic hybrid thyristor
US5468976A (en) * 1993-08-27 1995-11-21 Evseev; Yury Semi conductor rectifying module
JP3789580B2 (en) * 1996-12-25 2006-06-28 関西電力株式会社 High voltage semiconductor device
TW406319B (en) * 1998-12-22 2000-09-21 Gen Semiconductor Of Taiwan Lt Method of manufacturing inactivated semiconductor devices

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WO2000052761A1 (en) 2000-09-08
JP2002538627A (en) 2002-11-12
DE19908399A1 (en) 2000-09-07
US6518101B1 (en) 2003-02-11

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