EP1129477A1 - Salicide process for mosfet integrated circuit - Google Patents

Salicide process for mosfet integrated circuit

Info

Publication number
EP1129477A1
EP1129477A1 EP00956383A EP00956383A EP1129477A1 EP 1129477 A1 EP1129477 A1 EP 1129477A1 EP 00956383 A EP00956383 A EP 00956383A EP 00956383 A EP00956383 A EP 00956383A EP 1129477 A1 EP1129477 A1 EP 1129477A1
Authority
EP
European Patent Office
Prior art keywords
isolation layer
region
larger
trench
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00956383A
Other languages
German (de)
French (fr)
Inventor
Walter J. A. De Coster
Eric Gerritsen
Marie-Therese Basso
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Orange SA
Koninklijke Philips NV
Original Assignee
STMicroelectronics SA
France Telecom SA
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA, France Telecom SA, Koninklijke Philips Electronics NV filed Critical STMicroelectronics SA
Publication of EP1129477A1 publication Critical patent/EP1129477A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01324—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T or inverted-T
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes

Definitions

  • the invention relates to the manufacture of an integrated circuit, more particularly to the formation of metal silicide zones on the polysilicon regions forming, for example, the gate regions of the field effect transistors.
  • FIG. 1 which very diagrammatically shows a field effect transistor in accordance with the prior art the gate of which is covered with a metal silicide 5
  • reference numeral 1 denotes a semiconductor substrate within which the field effect transistor is formed.
  • said field effect transistor comprises a projecting portion of polysilicon 2, which forms the gate region of the transistor, said projecting portion being isolated from the substrate by a gate oxide 3, which typically consists of silicon dioxide.
  • the transistor also comprises lateral isolation zones or spacers 4, which are provided at the sides of the gate region 2 so as to be in contact therewith. These spacers are customarily composed of two layers, i.e.
  • a smaller isolation layer 40 which is generally composed of an oxide (for example, tetraethyl orthosilicate ( Si (OC 2 H 5 ) ); also referred to as TEOS in English), and a larger isolation layer 41, which is generally composed of silicon nitride Si 3 N 4 .
  • Silicon nitride enables better etching of the spacers while the smaller isolation layer forms a buffer layer against the stresses induced in the underlying silicon by the nitride layer.
  • the manufacture of the transistor also comprises a stage wherein the source, drain and gate regions of the transistor are subjected to a silicidation process.
  • This silicidation process includes, inter alia, the deposition of a metal, such as titanium or cobalt, which, in combination with silicon, is capable of forming a metal silicide, for example titanium silicide TiSi 2 .
  • a metal silicide for example titanium silicide TiSi 2 .
  • the silicidation stage enables a less elevated resistance of the polysilicon track 2 to be obtained.
  • the silicide zone 5 contacting the polysilicon region 2 has a curved interface with this polysilicon region, which is caused by mechanical stresses induced during the chemical reaction between titanium and silicon.
  • the thickness of the silicide formed is smaller at certain locations, and it has been found that the bonding power obtained would cause a partial retreat of the silicide during subsequent process steps.
  • the invention more particularly aims at improving the silicidation of the polysilicon tracks, thereby causing, in particular, the adhesion of the silicide to the silicon to be improved and hence a more efficacious reduction of the resistance of these polysilicon tracks.
  • the invention also aims at reducing the mechanical stresses induced in the polysilicon in the course of the silicidation process, thus enabling, in particular, a substantially flat upper silicide surface to be obtained.
  • a method of manufacturing an integrated circuit which method includes a stage wherein lateral isolation regions ( spacers ) are formed at the sides of at least one projecting polysilicon region so as to be in contact therewith, said lateral isolation regions each being composed of a smaller isolation layer, which is in contact with said projecting region, and of a larger isolation layer.
  • the method also includes a silicidation process to which the upper part of the polysilicon region is subjected, which silicidation process includes the deposition on said upper part of a metal layer which is capable of forming a metal silicide with the silicon.
  • the silicidation process includes, prior to the deposition of said metal layer, an etch step to which at least the vertical portion of the smaller isolation layer is subjected so as to form a trench of predetermined depth between the larger isolation layer of each lateral isolation region and the corresponding side of the polysilicon layer.
  • the deposition of the metal layer for example of titanium, is a directional deposition, which is carried out using, for example, a honeycomb-structured collimator, enabling the trenches thus obtained to be correctly filled.
  • an etch process carried out on the smaller isolation layer ( at least the vertical portion thereof) so as to detach at least the upper part of the polysilicon layer is inherent in the invention, said etch process enabling the mechanical stresses developing in this upper part during the silicidation to be reduced.
  • filling the trenches obtained by means of the directional metal deposition results in an improved lateral silicidation of the polysilicon region.
  • Those skilled in the art will be capable of adjusting the desired depth of the trenches as a function of, in particular, the dimensional characteristics of the polysilicon regions and the spacers in order to achieve the effect as desired by the invention, and taking into account the intended application.
  • the depth of the trenches preferably should be at least 1/20* of the height of the projecting polysilicon region.
  • the vertical portion of the smaller isolation layer of the spacers may be etched using an anisotropic etch process. In this case, only the vertical portion of the smaller isolation layer of the spacers is etched. The vertical portion of the smaller isolation layer may alternatively be etched using an isotropic etch process.
  • the invention also aims at providing an integrated circuit comprising lateral isolation regions formed at the sides of at least one projecting region of polysilicon so as to be in contact therewith, each lateral isolation region being composed of a smaller isolation layer, contacting said projecting region, and a larger isolation layer.
  • the integrated circuit further comprises a zone including a metal silicide situated in the upper part of the polysilicon region.
  • each lateral isolation region comprises a vertical trench made in the smaller isolation layer between the larger isolation layer and the corresponding side of the projecting region, said trench extending from the top of the larger isolation layer of the corresponding lateral isolation region down to a predetermined depth.
  • Fig 1 already described hereinabove, diagrammatically shows a transistor in accordance with the prior art
  • Figs. 2 through 8 diagrammatically show different steps in the implementation of the method in accordance with the invention; Fig. 8 more particularly shows a part of an integrated circuit in accordance with the invention.
  • reference numeral 1 denotes a semiconductor substrate of silicon
  • reference numeral 70 denotes a lateral isolation zone, or field oxide, which is typically made of silicon dioxide, and which serves, for example, to isolate the active zone formed in the silicon substrate 1 from another active zone.
  • polysilicon tracks 2 are obtained (shown in section in different planes), comprising, for example, a projecting region which is formed above the substrate and which serves to form the field-effect gate region of a transistor, and another projecting region which is formed above the field oxide and which serves to connect together two gate regions of two adjacent transistors.
  • the height of the projecting region of polysilicon 2 generally lies in the range between 1500 and 2500 A, for example approximately 2000 A.
  • a smaller isolation layer 400 typically of TEOS oxide
  • a larger isolation layer 410 typically of silicon nitride
  • Fig. 4 After subjecting the larger isolation layer 410 to an anisotropic etch process, the configuration shown in Fig. 4 is obtained, wherein the etched, larger isolation layer 41 lis used to form the larger isolation layer of the spacers arranged so as to contact the vertical, lateral sides of the projecting regions of polysilicon.
  • the smaller isolation layer 400 can be used as a stop layer in this anisotropic etch process. Subsequently (see Fig. 5), a customary process is carried leading to a reduction of portions of the smaller isolation layer 401 obtained in Fig.4, which portions are situated on the polysilicon regions and outside the layer 411.
  • the total thickness of the spacers generally lies in the range between 50 nm and 100 nm, for example 70 nm.
  • the thickness E of the larger isolation layer 411 is, for example, 50 nm while the thickness of the smaller isolation layer 402 is, for example, 20 nm.
  • a layer 8 is deposited which is composed of a material which serves to protect a part of the integrated circuit against the subsequent silicidation step.
  • This protection material may be silicon dioxide or TEOS oxide or TEOS oxide covered with silicon nitride.
  • the material 8 is subjected to an etch treatment so as to remove it at the location of the region of the integrated circuit involved in the silicidation process.
  • the etch treatment of the material 8 is extended so as to include an overetch treatment leading to the formation of a vertical trench TR having a predetermined depth h between the larger isolation region 411 of the spacers and the corresponding side F of the projecting polysilicon region.
  • the etch treatment of the material 8 and, possibly, the additional etch treatment are anisotropic etch treatments, then only the vertical portion of the smaller isolation layer 402 is etched.
  • one or more isotropic etch processes are carried out in order to form also horizontal trenches TH between the larger isolation layer 411 and the substrate 1, said trenches extending from the outer lateral edge of the larger isolation layer 411 of the spacers. The function and the usefulness of these horizontal trenches TH will be described hereinbelow.
  • the depth h of the vertical trenches TR is preferably at least equal to 1/20* of the height H of the projecting polysilicon region, resulting in a substantial improvement of the silicidation by a reduction of the mechanical stresses in the polysilicon.
  • said depth h preferably remains below half the height HI of the larger isolation layer 411, and also below half the thickness E of said layer 411.
  • the presence of the oblique sides FO on the field oxide 70 is caused by oxide consumption during the manufacturing process.
  • a metal 9 which is capable of forming a metal silicide with the polysilicon is deposited.
  • This is a directional deposition which is carried out using, for example, a honeycomb-structured collimator, so that the trenches TR can be filled, which would not be possible if use was made of a customary powder-coating process.
  • a first annealing step is carried out using equipment that is known per se, said annealing step being carried out a temperature in the range between 650°C and 800°C (for titanium) for a period of time ranging between 10 and 30 seconds, and a temperature of, for example 450°C for cobalt.
  • This first annealing process causes the titanium to be converted to titamum silicide TiSi 2 , more particularly to a titanium silicide known to those skilled in the art as TiS_ 2 -C49. This formation of titanium silicide takes place through contact with the polysilicon as well as through contact with the silicon of the substrate.
  • titanium nitride TiN and titanium oxides TiO x are formed. Titanium nitrides also form above the titanium silicide.
  • trenches TR which have been filled with titanium at an earlier stage, improve the lateral silicidation of the polysilicon regions.
  • a selective reduction, which is known per se, of the titanium nitride, the titanium oxides TiO x and the titanium is carried out.
  • This selective reduction is obtained, for example, by wet-etching in a bath on the basis of ammonia and hydrogen peroxide (H 2 O 2 ). It is to be noted that a small quantity of TiSi 2 is consumed in this wet-etching process.
  • a second high-temperature annealing process is carried out, typically at temperatures above 800°C, for example 900°C, for a few seconds, for example about ten seconds, in order to convert the titanium silicide C49 to a less resistive titanium silicide known to those skilled in the art as C54. Also in this case, the conversion takes place under more favorable conditions than in the method according to the prior art, which can be attributed to the reduction of the mechanical stresses in the polysilicon, which reduction is attributable to the presence of vertical trenches.
  • FIG. 8 After said annealing process, the configuration shown in Fig. 8 is obtained.
  • reference numeral 5 denotes the metal silicide zone situated on the upper part of the projecting regions of silicon.
  • Reference numerals 6 and 7 denote the metal silicide zones situated on the source and drain regions of the transistor.
  • the upper surface of the metal silicide zone 5 is quasi planar. Furthermore, in the course of the annealing processes, particularly during the first annealing process, a small portion of the silicon is consumed. However, if said reduction in height is taken into account as well as the height of the metal silicide 5, a height H2 of the silicidized polysilicon region is obtained which is approximately equal to the initial height H of the polysilicon region.
  • the height h of the vertical trenches TR remains preferably equal to at least 1/20* of the height H2.
  • the selective reduction of the titanium oxides, the titanium nitride and, possibly, the unreacted titanium, carried out between the two annealing processes may result in titanium nitride residues and/or titanium oxide residues being left behind on the surface of the larger isolation layer 411, which residues may cause short- circuits between the zones if they simultaneously contact the silicidized gate zones and the silicidized drain/source zones. This risk of short-circuits is minimized by the presence of the horizontal trenches TH

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The integrated circuit comprises lateral isolation regions formed at the sides of at least one projecting polysilicon region so as to be in contact therewith, said lateral isolation regions each being composed of a smaller isolation layer (402), which is in contact with said projecting region (2), and of a larger isolation layer (411), and it further comprises a zone (5) including a metal silicide situated in the upper part of the polysilicon region (2). Each lateral isolation region comprises a vertical trench (TR) made in the smaller isolation layer (402) between the larger isolation layer (411) and the corresponding side (F) of the projecting region (2), said trench (TR) extending from the top of the larger isolation layer (411) of the corresponding lateral isolation region down to a predetermined depth (h).

Description

SALICIDE PROCESS FOR MOSFET INTEGRATED CIRCUIT
The invention relates to the manufacture of an integrated circuit, more particularly to the formation of metal silicide zones on the polysilicon regions forming, for example, the gate regions of the field effect transistors.
In Figure 1, which very diagrammatically shows a field effect transistor in accordance with the prior art the gate of which is covered with a metal silicide 5, reference numeral 1 denotes a semiconductor substrate within which the field effect transistor is formed. As is customary, said field effect transistor comprises a projecting portion of polysilicon 2, which forms the gate region of the transistor, said projecting portion being isolated from the substrate by a gate oxide 3, which typically consists of silicon dioxide. The transistor also comprises lateral isolation zones or spacers 4, which are provided at the sides of the gate region 2 so as to be in contact therewith. These spacers are customarily composed of two layers, i.e. a smaller isolation layer 40, which is generally composed of an oxide ( for example, tetraethyl orthosilicate ( Si (OC2H5) ); also referred to as TEOS in English), and a larger isolation layer 41, which is generally composed of silicon nitride Si3N4. Silicon nitride enables better etching of the spacers while the smaller isolation layer forms a buffer layer against the stresses induced in the underlying silicon by the nitride layer.
The manufacture of the transistor also comprises a stage wherein the source, drain and gate regions of the transistor are subjected to a silicidation process. This silicidation process includes, inter alia, the deposition of a metal, such as titanium or cobalt, which, in combination with silicon, is capable of forming a metal silicide, for example titanium silicide TiSi2. This results in the formation of metal silicide zones 5, 6 and 7, which are provided on, respectively, the gate, source and drain regions of the transistor.
The silicidation stage enables a less elevated resistance of the polysilicon track 2 to be obtained.
However, as shown in Figure 1 , the silicide zone 5 contacting the polysilicon region 2 has a curved interface with this polysilicon region, which is caused by mechanical stresses induced during the chemical reaction between titanium and silicon. Apart from the fact that said curved surface is less suitable for making contact, at a later stage, than a flat surface, the thickness of the silicide formed is smaller at certain locations, and it has been found that the bonding power obtained would cause a partial retreat of the silicide during subsequent process steps. Finally, this results in a smaller quantity of silicide, causing a smaller reduction of the resistance of the polysilicon track.
It is an object of the invention to overcome this problem.
The invention more particularly aims at improving the silicidation of the polysilicon tracks, thereby causing, in particular, the adhesion of the silicide to the silicon to be improved and hence a more efficacious reduction of the resistance of these polysilicon tracks.
The invention also aims at reducing the mechanical stresses induced in the polysilicon in the course of the silicidation process, thus enabling, in particular, a substantially flat upper silicide surface to be obtained.
This object is achieved in accordance with the invention by a method of manufacturing an integrated circuit, which method includes a stage wherein lateral isolation regions ( spacers ) are formed at the sides of at least one projecting polysilicon region so as to be in contact therewith, said lateral isolation regions each being composed of a smaller isolation layer, which is in contact with said projecting region, and of a larger isolation layer. The method also includes a silicidation process to which the upper part of the polysilicon region is subjected, which silicidation process includes the deposition on said upper part of a metal layer which is capable of forming a metal silicide with the silicon.
In accordance with a general characteristic of the invention, the silicidation process includes, prior to the deposition of said metal layer, an etch step to which at least the vertical portion of the smaller isolation layer is subjected so as to form a trench of predetermined depth between the larger isolation layer of each lateral isolation region and the corresponding side of the polysilicon layer. Moreover, the deposition of the metal layer, for example of titanium, is a directional deposition, which is carried out using, for example, a honeycomb-structured collimator, enabling the trenches thus obtained to be correctly filled.
In other words, an etch process carried out on the smaller isolation layer ( at least the vertical portion thereof) so as to detach at least the upper part of the polysilicon layer is inherent in the invention, said etch process enabling the mechanical stresses developing in this upper part during the silicidation to be reduced. In addition, filling the trenches obtained by means of the directional metal deposition results in an improved lateral silicidation of the polysilicon region. Those skilled in the art will be capable of adjusting the desired depth of the trenches as a function of, in particular, the dimensional characteristics of the polysilicon regions and the spacers in order to achieve the effect as desired by the invention, and taking into account the intended application.
In this case, it has been found that, in order to substantially improve the silicidation, the depth of the trenches preferably should be at least 1/20* of the height of the projecting polysilicon region.
Those skilled in the art will also be capable of adjusting the depth of the trenches in such a way that the larger isolation layer ( typically of silicon nitride ) of the spacers does not become detached. In this respect, it has been found that a trench depth of maximally half the height of the larger isolation layer and maximally half the thickness of the larger isolation layer would reduce the risk of said larger isolation layer becoming detached. The vertical portion of the smaller isolation layer of the spacers may be etched using an anisotropic etch process. In this case, only the vertical portion of the smaller isolation layer of the spacers is etched. The vertical portion of the smaller isolation layer may alternatively be etched using an isotropic etch process. This results in the formation of a horizontal trench inside each spacer, which horizontal trench is made in the smaller isolation layer between the larger isolation layer and the substrate of the integrated circuit, said horizontal trench extending from the side edge of the larger isolation layer of the spacer. Such a horizontal trench enables a further reduction of the risk of short-circuits between the silicidized source and drain regions, on the one hand, and the silicidized gate region on the other hand.
The invention also aims at providing an integrated circuit comprising lateral isolation regions formed at the sides of at least one projecting region of polysilicon so as to be in contact therewith, each lateral isolation region being composed of a smaller isolation layer, contacting said projecting region, and a larger isolation layer. The integrated circuit further comprises a zone including a metal silicide situated in the upper part of the polysilicon region.
In accordance with a general characteristic of the invention, each lateral isolation region comprises a vertical trench made in the smaller isolation layer between the larger isolation layer and the corresponding side of the projecting region, said trench extending from the top of the larger isolation layer of the corresponding lateral isolation region down to a predetermined depth.
These and other objects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. In the drawings:
Fig 1, already described hereinabove, diagrammatically shows a transistor in accordance with the prior art, and
Figs. 2 through 8 diagrammatically show different steps in the implementation of the method in accordance with the invention; Fig. 8 more particularly shows a part of an integrated circuit in accordance with the invention.
In Fig. 2, reference numeral 1 denotes a semiconductor substrate of silicon, and reference numeral 70 denotes a lateral isolation zone, or field oxide, which is typically made of silicon dioxide, and which serves, for example, to isolate the active zone formed in the silicon substrate 1 from another active zone.
After the formation, in a customary manner, of a gate oxide layer 3, and after the deposition, in a customary manner, of a polysilicon layer and etching of the latter, polysilicon tracks 2 are obtained (shown in section in different planes), comprising, for example, a projecting region which is formed above the substrate and which serves to form the field-effect gate region of a transistor, and another projecting region which is formed above the field oxide and which serves to connect together two gate regions of two adjacent transistors.
The height of the projecting region of polysilicon 2 generally lies in the range between 1500 and 2500 A, for example approximately 2000 A. Subsequently, a smaller isolation layer 400, typically of TEOS oxide, is similarly deposited in a manner which is known per se (Fig. 3), said smaller isolation layer having a thickness of the order of, for example, 200 A. Next, a larger isolation layer 410, typically of silicon nitride, is similarly deposited in a manner which is also known per se. After subjecting the larger isolation layer 410 to an anisotropic etch process, the configuration shown in Fig. 4 is obtained, wherein the etched, larger isolation layer 41 lis used to form the larger isolation layer of the spacers arranged so as to contact the vertical, lateral sides of the projecting regions of polysilicon.
It is to be noted that the smaller isolation layer 400 can be used as a stop layer in this anisotropic etch process. Subsequently (see Fig. 5), a customary process is carried leading to a reduction of portions of the smaller isolation layer 401 obtained in Fig.4, which portions are situated on the polysilicon regions and outside the layer 411.
This results in the formation of spacers formed by the smaller isolation layer 402 and the larger isolation layer 411. The total thickness of the spacers generally lies in the range between 50 nm and 100 nm, for example 70 nm. To be more precise, the thickness E of the larger isolation layer 411 is, for example, 50 nm while the thickness of the smaller isolation layer 402 is, for example, 20 nm.
After the customary doping operations of the drain and source regions have been carried out in the semiconductor substrate as well as the subsequent high-temperature annealing process at a temperature above, for example, 1000°C for 5 to 50 seconds, a layer 8 is deposited which is composed of a material which serves to protect a part of the integrated circuit against the subsequent silicidation step. This protection material may be silicon dioxide or TEOS oxide or TEOS oxide covered with silicon nitride. Next (see Fig. 6), the material 8 is subjected to an etch treatment so as to remove it at the location of the region of the integrated circuit involved in the silicidation process.
If the material 8 is identical to the material used for the smaller isolation layer 402, then the etch treatment of the material 8 is extended so as to include an overetch treatment leading to the formation of a vertical trench TR having a predetermined depth h between the larger isolation region 411 of the spacers and the corresponding side F of the projecting polysilicon region.
If, however, the material 8 differs from the material of the smaller isolation layer 402 of the spacers, then an additional, selective etch treatment is carried out to form the trenches TR.
If the etch treatment of the material 8 and, possibly, the additional etch treatment are anisotropic etch treatments, then only the vertical portion of the smaller isolation layer 402 is etched. In this case, preferably, but not necessarily, one or more isotropic etch processes are carried out in order to form also horizontal trenches TH between the larger isolation layer 411 and the substrate 1, said trenches extending from the outer lateral edge of the larger isolation layer 411 of the spacers. The function and the usefulness of these horizontal trenches TH will be described hereinbelow.
The depth h of the vertical trenches TR is preferably at least equal to 1/20* of the height H of the projecting polysilicon region, resulting in a substantial improvement of the silicidation by a reduction of the mechanical stresses in the polysilicon.
Moreover, in order to preclude that the larger isolation layer 411 of the spacers becomes detached, said depth h preferably remains below half the height HI of the larger isolation layer 411, and also below half the thickness E of said layer 411. This means, in a practical indication of the above ratios, that for a height H of the polysilicon of the order of 200 nm, a height h of the order of at least 10 nm leads to a substantial improvement of the silicidation.
It is to be noted that the presence of the oblique sides FO on the field oxide 70 is caused by oxide consumption during the manufacturing process.
When the trenches have been formed, a metal 9 (see Fig.7) which is capable of forming a metal silicide with the polysilicon is deposited. This is a directional deposition which is carried out using, for example, a honeycomb-structured collimator, so that the trenches TR can be filled, which would not be possible if use was made of a customary powder-coating process.
After the silicidation step, a first annealing step is carried out using equipment that is known per se, said annealing step being carried out a temperature in the range between 650°C and 800°C (for titanium) for a period of time ranging between 10 and 30 seconds, and a temperature of, for example 450°C for cobalt. This first annealing process causes the titanium to be converted to titamum silicide TiSi2, more particularly to a titanium silicide known to those skilled in the art as TiS_2-C49. This formation of titanium silicide takes place through contact with the polysilicon as well as through contact with the silicon of the substrate.
Through contact with the larger isolation layer 411 of the spacers, titanium nitride TiN and titanium oxides TiOx are formed. Titanium nitrides also form above the titanium silicide.
It is to be noted that the trenches TR, which have been filled with titanium at an earlier stage, improve the lateral silicidation of the polysilicon regions.
After the first annealing process, a selective reduction, which is known per se, of the titanium nitride, the titanium oxides TiOx and the titanium is carried out. This selective reduction is obtained, for example, by wet-etching in a bath on the basis of ammonia and hydrogen peroxide (H2O2). It is to be noted that a small quantity of TiSi2 is consumed in this wet-etching process.
Subsequently, a second high-temperature annealing process is carried out, typically at temperatures above 800°C, for example 900°C, for a few seconds, for example about ten seconds, in order to convert the titanium silicide C49 to a less resistive titanium silicide known to those skilled in the art as C54. Also in this case, the conversion takes place under more favorable conditions than in the method according to the prior art, which can be attributed to the reduction of the mechanical stresses in the polysilicon, which reduction is attributable to the presence of vertical trenches.
After said annealing process, the configuration shown in Fig. 8 is obtained. In Fig. 8, reference numeral 5 denotes the metal silicide zone situated on the upper part of the projecting regions of silicon. Reference numerals 6 and 7 denote the metal silicide zones situated on the source and drain regions of the transistor. The upper surface of the metal silicide zone 5 is quasi planar. Furthermore, in the course of the annealing processes, particularly during the first annealing process, a small portion of the silicon is consumed. However, if said reduction in height is taken into account as well as the height of the metal silicide 5, a height H2 of the silicidized polysilicon region is obtained which is approximately equal to the initial height H of the polysilicon region.
Consequently, the height h of the vertical trenches TR remains preferably equal to at least 1/20* of the height H2.
Furthermore, the selective reduction of the titanium oxides, the titanium nitride and, possibly, the unreacted titanium, carried out between the two annealing processes, may result in titanium nitride residues and/or titanium oxide residues being left behind on the surface of the larger isolation layer 411, which residues may cause short- circuits between the zones if they simultaneously contact the silicidized gate zones and the silicidized drain/source zones. This risk of short-circuits is minimized by the presence of the horizontal trenches TH

Claims

CLAIMS:
1. A method of manufacturing an integrated circuit, which method includes a stage wherein lateral isolation regions ( spacers ) are formed at the sides of a projecting polysilicon region so as to be in contact therewith, said lateral isolation regions each being composed of a smaller isolation layer (402), which is in contact with said projecting region (2), and of a larger isolation layer, which method also includes a silicidation process to which the upper part of the polysilicon region is subjected, which silicidation process includes the deposition on said upper part of a metal layer which is capable of forming a metal silicide (5) with the silicon, characterized in that the silicidation process includes, prior to the deposition of said metal layer, an etch step to which at least the vertical portion of the smaller isolation layer (402) is subjected so as to form a trench (TR) of predetermined depth (h) between the larger isolation layer (411) of each lateral isolation region and the corresponding side (F) of the polysilicon region (2), and in that the deposition of the metal layer is a directional deposition.
2. A method as claimed in claim 1 , characterized in that the depth (h) of the trench is at least equal to 1/20* of the height (H) of the projecting region.
3. A method as claimed in claim 1 or 2, characterized in that the depth (h) of the trench is equal to maximally half the height (HI) of the larger isolation layer and maximally half the thickness (E) of the larger isolation layer.
4. A method as claimed in any one of the preceding claims, characterized in that the vertical portion of the smaller isolation layer (402) is anisotropically etched.
5. A method as claimed in any one of the claims 1 to 3, characterized in that the vertical portion of the smaller isolation layer (402) is isotropically etched.
6. An integrated circuit comprising lateral isolation regions formed at the sides of at least one projecting region of polysilicon so as to be in contact therewith, each lateral isolation region being composed of a smaller isolation layer (402), contacting said projecting region (2), and a larger isolation layer (411), and comprising a zone (5) including a metal silicide situated in the upper part of the polysilicon region (2), characterized in that each lateral isolation region comprises a vertical trench (TR) made in the smaller isolation layer (402) between the larger isolation layer (411) and the corresponding side (F) of the projecting region (2), said trench (TR) extending from the top of the larger isolation layer (411) of the corresponding lateral isolation region down to a predetermined depth (h).
7. An integrated circuit as claimed in claim 6, characterized in that the depth (h) of the trench (TR) is at least equal to 1/10^ of the height (H2) of the projecting region of silicidized polysilicon.
8. An integrated circuit as claimed in claim 6 or 7, characterized in that the depth (h) of the trench (TR) is equal to maximally half the height (HI) of the larger isolation layer and equal to maximally half the thickness( E) of the larger isolation layer.
9. An integrated circuit as claimed in any one of the claims 6 to 8, characterized in that each lateral isolation region comprises a horizontal trench (TH) made in the smaller isolation layer (402) between the larger isolation layer (411) and the substrate (1) of the integrated circuit, said trench extending from the lateral edge of the larger isolation layer of the lateral isolation region.
EP00956383A 1999-08-09 2000-08-02 Salicide process for mosfet integrated circuit Withdrawn EP1129477A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9910309A FR2797522A1 (en) 1999-08-09 1999-08-09 METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT HAVING IMPROVED SILICIURATION AND CORRESPONDING INTEGRATED CIRCUIT
FR9910309 1999-08-09
PCT/EP2000/007519 WO2001011669A1 (en) 1999-08-09 2000-08-02 Salicide process for mosfet integrated circuit

Publications (1)

Publication Number Publication Date
EP1129477A1 true EP1129477A1 (en) 2001-09-05

Family

ID=9549012

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00956383A Withdrawn EP1129477A1 (en) 1999-08-09 2000-08-02 Salicide process for mosfet integrated circuit

Country Status (4)

Country Link
EP (1) EP1129477A1 (en)
JP (1) JP2003506893A (en)
FR (1) FR2797522A1 (en)
WO (1) WO2001011669A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3574644B2 (en) 2002-11-20 2004-10-06 沖電気工業株式会社 Method for manufacturing semiconductor device
US7298011B2 (en) * 2005-08-30 2007-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with recessed L-shaped spacer and method of fabricating the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766406A (en) * 1993-08-25 1995-03-10 Oki Electric Ind Co Ltd Salicide MOSFET and manufacturing method thereof
JP2606143B2 (en) * 1994-07-22 1997-04-30 日本電気株式会社 Semiconductor device and manufacturing method thereof
US5783479A (en) * 1997-06-23 1998-07-21 National Science Council Structure and method for manufacturing improved FETs having T-shaped gates

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0111669A1 *

Also Published As

Publication number Publication date
FR2797522A1 (en) 2001-02-16
JP2003506893A (en) 2003-02-18
WO2001011669A1 (en) 2001-02-15

Similar Documents

Publication Publication Date Title
JP3773755B2 (en) Vertical MOS transistor and manufacturing method thereof
US20010014533A1 (en) Method of fabricating salicide
KR100299880B1 (en) Self-aligned dual thickness cobalt silicide layer formation process
JP3554514B2 (en) Semiconductor device and manufacturing method thereof
KR20040029119A (en) Improved high k-dielectrics using nickel silicide
US7501672B2 (en) Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device
US6667204B2 (en) Semiconductor device and method of forming the same
JP2675713B2 (en) Semiconductor device and manufacturing method thereof
KR20040079518A (en) MOSFET having recessed channel and fabricating method thereof
JPH07254574A (en) Electrode forming method
US6673665B2 (en) Semiconductor device having increased metal silicide portions and method of forming the semiconductor
US20020070452A1 (en) Formation of micro rough polysurface for low sheet resistance salicided sub-quarter micron polylines
EP1129477A1 (en) Salicide process for mosfet integrated circuit
JP3168992B2 (en) Method for manufacturing semiconductor device
US7109116B1 (en) Method for reducing dendrite formation in nickel silicon salicide processes
JPH03288443A (en) Manufacture of semiconductor device
KR100850068B1 (en) Semiconductor device and silicide film manufacturing method thereof
JPH08274187A (en) Method for manufacturing semiconductor device
US6642592B2 (en) Semiconductor device and method for fabricating same
KR100588686B1 (en) Method for manufacturing a silicide film of a semiconductor device
US20040175911A1 (en) Method for forming MOS transistors with improved sidewall structures
JPH08264771A (en) Semiconductor device and manufacturing method thereof
JPH09162392A (en) Semiconductor device
JP3039419B2 (en) Semiconductor device and manufacturing method thereof
JP3767583B2 (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

17P Request for examination filed

Effective date: 20010816

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V.

Owner name: FRANCE TELECOM

Owner name: STMICROELECTRONICS S.A.

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20040325

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB IT