EP1128661A1 - Verfahren zur Steuerung eines CMOS-Bildsensors - Google Patents

Verfahren zur Steuerung eines CMOS-Bildsensors Download PDF

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Publication number
EP1128661A1
EP1128661A1 EP00200597A EP00200597A EP1128661A1 EP 1128661 A1 EP1128661 A1 EP 1128661A1 EP 00200597 A EP00200597 A EP 00200597A EP 00200597 A EP00200597 A EP 00200597A EP 1128661 A1 EP1128661 A1 EP 1128661A1
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EP
European Patent Office
Prior art keywords
signal
phase
initialization
memory node
photodiode
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Withdrawn
Application number
EP00200597A
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English (en)
French (fr)
Inventor
Stefan Lauxtermann
Steve Tanner
Joachim Grupp
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Asulab AG
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Asulab AG
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H04N25/621—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/53—Control of the integration time
    • H04N25/532—Control of the integration time by controlling global shutters in CMOS SSIS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present invention generally relates to a method for operating an integrated image sensor. More particularly, the present invention relates to a process for operating an image sensor integrated in CMOS technology. Of such CMOS image sensors are in particular intended for the production of devices integrated photographic and video.
  • Such an integrated device of image capture incorporates, on the same chip, a photo-detector component formed of a set of photo-detector elements typically organized in the form of matrix, and a processing component intended to ensure the setting operations of images and of reading of the information captured by the photodetector component.
  • CCD components charge-coupled devices
  • CID charge injection devices
  • This document describes an image sensor integrated in CMOS technology. as a single chip.
  • the architecture of this sensor which is similar to that of RAM memories, is illustrated in FIG. 1.
  • This sensor generally indicated by the reference numeral 1, comprises a matrix 10 of pixels arranged in M lines and N columns. This matrix 10 occupies most of the surface of the sensor. The reading of a particular pixel of the matrix 10 is carried out by the addressing of the line and from the corresponding column. To this end, the sensor further comprises a circuit line addressing 20 coupled to the lines of the matrix 10 and an output bus 30 coupled to the columns of the matrix 10, both controlled by a circuit of command 40.
  • Each pixel of the matrix 10 has a structure in accordance with the illustration of Figure 2A.
  • This pixel generally indicated by the reference numeral 50 in the FIG. 2A, comprises a photo-detector element PD, a first stage A1, a means storage C1 and a second stage A2.
  • the photodetector element PD is formed of a reverse polarized photodiode which collects the photo-generated electrons during a so-called integration period.
  • the first stage A1 is a "sample-and-hold" type circuit ensuring the sampling, at a determined time, of the voltage value present across the PD photodiode. This sampled value is memorized in the storage means C1 which is typically formed of a capacity.
  • the value of the voltage stored on the capacitor C1 depends on the function of transfer of the first stage A1 and in particular of the ratio between the value of the capacity of the photodiode PD and of the capacity of the storage means C1.
  • the second floor A2 allows reading the memorized sampled voltage in the storage means C1.
  • the structure schematically described in the figure 2A advantageously allows the separation of the detection and reading processes.
  • FIG. 2B shows in particular one of these embodiments in which the pixel 50 comprises the photodiode PD (of n type) reverse polarized and five transistors M1 to M5 of n-MOS type.
  • Each pixel 50 has a node memory 55 formed of a capacity (capacity C1) and protected from light, for example with a metallic protective layer.
  • the transistor M1 initializes the photodiode PD at a determined voltage before each integration period.
  • the transistor M2 ensures the sampling of the charge accumulated by the photodiode PD and the storage of the signal thus sampled on the memory node 55.
  • This transistor M2 also provides isolation or decoupling of the photodiode PD and the memory node 55.
  • the transistor M3 ensures in particular the initialization of the memory node 55 at a determined voltage.
  • the transistor M4 is a "follower source transistor" and the transistor M5 is a line selection transistor and ensures, during the reading process, the transfer of the voltage from the transistor M4 on a bus. output common to all pixels in a column.
  • the signals applied to this structure include a high supply voltage V DD and a low supply voltage V SS forming mass, a first initialization signal TI, a sampling signal SH, a second initialization signal RST, and an RSEL line selection signal.
  • a first terminal of the photodiode PD is connected to the ground V SS and the other terminal is connected to the sources of the transistors M1 and M2 whose gates are respectively controlled by the signals T1 and SH.
  • the drains of the transistors M1, M3 and M4 are connected to the high supply voltage V DD .
  • the second initialization signal RST is applied to the gate of the transistor M3.
  • the source of transistor M3, the drain of transistor M2 and the gate of transistor M4 are connected together to the memory node 55 of the pixel.
  • the source of transistor M4 is connected, via line selection transistor M5, to the output bus common to all the pixels in a column.
  • the line selection signal RSEL is applied to the gate of transistor M5.
  • a problem, in terms of performance, encountered with the pixel structure 50 illustrated in FIG. 2B resides in the fact that the sampled charge stored on the memory node 55 does not remain constant during the reading process. Indeed, as described in the aforementioned document, the capacity of the memory node 55 discharges relatively quickly due to the fact that the photo-generated charges under the PD photodiode have a long enough lifetime to diffuse in the substrate and come to discharge the capacity of the memory node 55 although this one be protected from light. This problem of diffusion of charge carriers is all the more pronounced as the intensity of the light on the photosensitive area of the sensor is high. It will therefore be understood that this phenomenon of diffusion limits drastically the time available to allow a reading of the tensions sampled stored on the capacities of the pixels.
  • An object of the present invention is thus to propose a method allowing to operate a CMOS image sensor of the aforementioned type which addresses the problem of charge carrier diffusion encountered with such sensors.
  • Another object of the present invention is to provide a method for to operate a CMOS image sensor of the aforementioned type which allows use of this sensor for applications where the exposure time is decisive because very short.
  • Yet another object of the present invention is to provide a method allowing to operate a CMOS image sensor of the aforementioned type which does not not require the use of a mechanical shutter.
  • An advantage of the method according to the present invention lies in the fact that a once the charges accumulated by the photodiode during the integration period have been sampled and stored on the storage capacity of each pixel, the photodiode voltage is directly brought to its initialization voltage in view of the next acquisition. In this way, any photo-generated charge is captured or drained and thus does not diffuse through the substrate to the memory node.
  • the signal sampled on each pixel of the sensor therefore remains constant. The process of reading of each pixel, line by line, can then take place conventionally without any additional exposure step being necessary.
  • the present invention makes possible the use of the sensor image for applications where the exposure time is very short. We reduce by more greatly the total time required for the exposure and treatment of a picture. We can thus effectively speak of a sensor with global shutter or "global shutter".
  • Another advantage of the present invention lies in the fact that the exposure and reading operations are made completely independent. We furthermore effectively performs electronic shuttering so that any means mechanical shutter is no longer necessary to allow proper operation of the image taking device. This also reduces the manufacturing costs of these devices.
  • FIG. 3 thus shows a time diagram of the evolution of the control signals TI, SH, RST and RSEL making it possible to operate the pixel structure of FIG. 2B. Also shown in this figure is the evolution of the voltage V PD of the photodiode PD as well as the evolution of the voltage V 1 at the memory node 55 of the pixel.
  • the method according to the present invention is not limited to the operation of a structure such as the structure illustrated in Figure 2B, but perhaps applied analogously to any type of structure schematically in the form of the structure illustrated in FIG. 2A, that is to say a structure comprising a photo-detector element and a storage means capable of being coupled to the photodetector element at a determined time in order to generate and store a sampled signal representative of the charge carriers accumulated by the photo-detector element during integration.
  • the structure of the figure 2B nevertheless constitutes a simple and particularly advantageous structure.
  • the first initialization signal Tl of the transistor M1 ensures the initialization of the photodiode PD, before each integration period, at a determined initialization voltage.
  • the first TI initialization signal is applied globally on the sensor pixels, i.e. the PD photodiodes all the pixels of the sensor are simultaneously initialized, at the start of each period integration, at the initialization voltage.
  • sampling signal SH is applied globally to the pixels of the sensor, so that the voltages of the photodiodes are simultaneously sampled and stored on the memory node 55 of the pixels.
  • the second initialization signal RST is applied either globally or line by line. As will be seen later in detail, this second signal initialization is first applied globally to initialize the node memory of each pixel at a determined initialization voltage, then, in a later phase, is applied line by line during the reading process.
  • the RSEL line selection signal is applied line by line during the reading process.
  • first and second initialization signals TI and RST are all two bring it to a high positive voltage level so as to initialize respectively the photodiode PD and the memory node 55 of each pixel at a initialization voltage determined.
  • the sampling signal SH is at a level low such that the transistor M2 is not conductive, thus decoupling the photodiode PD and the memory node 55.
  • the line selection signal RSEL is at one low level so that the line selection transistor M5 is not conductive.
  • the resulting voltages V PD and V 1 on the photodiode PD and the memory node 55 respectively are therefore at levels substantially equal to the determined initialization voltage.
  • the first initialization signal TI goes to a low level making the transistor M1 non-conductive.
  • the photodiodes PD begin to discharge in proportion to the quantity of light that each of them receives as shown by the evolution of the voltage V PD in Figure 3. It will be understood that the passage of the initialization signal TI from a high level to a low level thus gives the start of the exposure of the sensor to light. It is the beginning of the integration period.
  • the second initialization signal RST is maintained at a level such that the voltage of memory node 55 of each pixel is maintained at a constant value substantially equal to the initialization voltage determined.
  • the second initialization signal RST goes to a low level, thus freeing the memory node 55.
  • a third phase C then follows directly this passage of the initialization signal RST from a high level to a level low.
  • the sampling signal SH briefly goes to a level high to make the M2 transistor conductive and thus allow sampling of the voltage value present on the photodiode PD and its storage, via the sampling transistor M2, on the memory node 55.
  • the voltage V1 of memory node 55 thus evolves as shown in FIG. 3.
  • the end of this third phase C therefore determines the end of the sensor exposure time.
  • the memory node 55 of each pixel has memorized a value of voltage representative of the quantity of charges which have been generated under the PD photodiode during exposure of the sensor.
  • the first initialization signal Tl is brought again to a level such that each photodiode is again initialized at a voltage substantially equal to the voltage initialization.
  • any charge that would be generated under the effect of light at level of the photodiode is drained via transistor M1.
  • the sampled voltage stored on the memory node of each pixel of the sensor is thus not disturbed by the phenomenon of diffusion of charge carriers, so that the tension present at this memory node remains constant.
  • each line of pixels of the sensor can thus be read successively without running the risk that the capacity of memory nodes are not discharged under the effect of photo-generated charges which would diffuse into the substrate.
  • each line is addressed successively in order to allow the reading of the sampled voltages of each pixel via the output bus of each column.
  • the signals are applied in accordance with the first initialization phase A and the next acquisition operation can start.
  • this reading operation is carried out according to a technique known to a person skilled in the art under the name "correlated double sampling” or CDS.
  • CDS correlated double sampling
  • the operation of reading each line is breaks down into a first phase of reading the voltage present on the nodes pixel memories in a line followed by a second reading phase during which the memory nodes of the pixels in the line are reset.
  • a signal formed from the difference between the measured sampled voltage and the voltage memory node initialization is then produced for each pixel.
  • This technique allows the removal of "stable noise” or "fixed pattern noise", that is to say the suppression of the noise present on each pixel of the sensor and which is due to the slight differences in sensitivity that may exist between pixels.
  • both the RSEL line selection signal and the second initialization signal RST are thus applied line by line during the fourth phase D.
  • CMOS image sensor operated according to the present invention thus works like a photographic device having a mechanical shutter.
  • the M2 sampling transistors together perform the function of an electronic shutter.
  • n-well type photodiodes i.e. photodiodes formed in n-type boxes.
  • This structure offers the advantage of constitute a better obstacle to the spread of charge carriers than a structure photodiode formed conventionally, for example of a simple region of n-type diffusion.
  • the pixel structure used as an example to illustrate the process according to the present invention could in principle be performed using complementary p-mos technology or, where appropriate include additional transistors. It will be understood, for example, that the main purpose of the M2 sampling transistor is to decouple the photodiode and the pixel memory node and that other arrangements can be intended to fulfill this function.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)
EP00200597A 2000-02-22 2000-02-22 Verfahren zur Steuerung eines CMOS-Bildsensors Withdrawn EP1128661A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP00200597A EP1128661A1 (de) 2000-02-22 2000-02-22 Verfahren zur Steuerung eines CMOS-Bildsensors

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EP00200597A EP1128661A1 (de) 2000-02-22 2000-02-22 Verfahren zur Steuerung eines CMOS-Bildsensors

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1796373A1 (de) * 2005-12-12 2007-06-13 The Swatch Group Research and Development Ltd. Abbildungsverfahren mit Hilfe eines Bildsensors mit grossem dynamik Bereich
WO2015052864A1 (en) * 2013-10-10 2015-04-16 Sony Corporation Image-capturing device, radiation detection apparatus, and control method for image-capturing device
US10691907B2 (en) 2005-06-03 2020-06-23 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array
US10721429B2 (en) 2005-03-11 2020-07-21 Hand Held Products, Inc. Image reader comprising CMOS based image sensor array
CN112565642A (zh) * 2020-11-27 2021-03-26 上海华力微电子有限公司 一种具有线性对数输出的cis传感器
US12026580B2 (en) 2022-10-28 2024-07-02 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array

Citations (3)

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Publication number Priority date Publication date Assignee Title
US4839735A (en) * 1986-12-22 1989-06-13 Hamamatsu Photonics K.K. Solid state image sensor having variable charge accumulation time period
WO1999044359A1 (en) * 1998-02-27 1999-09-02 Intel Corporation Method to reduce reset noise in photodiode based cmos image sensors
WO2000005874A1 (en) * 1998-07-22 2000-02-03 Foveon, Inc. Multiple storage node active pixel sensors

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US4839735A (en) * 1986-12-22 1989-06-13 Hamamatsu Photonics K.K. Solid state image sensor having variable charge accumulation time period
WO1999044359A1 (en) * 1998-02-27 1999-09-02 Intel Corporation Method to reduce reset noise in photodiode based cmos image sensors
WO2000005874A1 (en) * 1998-07-22 2000-02-03 Foveon, Inc. Multiple storage node active pixel sensors

Non-Patent Citations (1)

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Title
MIKIO KYOMASU: "A NEW MOS IMAGER USING PHOTODIODE AS CURRENT SOURCE", IEEE JOURNAL OF SOLID-STATE CIRCUITS,US,IEEE INC. NEW YORK, vol. 26, no. 8, 1 August 1991 (1991-08-01), pages 1116 - 1122, XP000258579, ISSN: 0018-9200 *

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11317050B2 (en) 2005-03-11 2022-04-26 Hand Held Products, Inc. Image reader comprising CMOS based image sensor array
US11968464B2 (en) 2005-03-11 2024-04-23 Hand Held Products, Inc. Image reader comprising CMOS based image sensor array
US11863897B2 (en) 2005-03-11 2024-01-02 Hand Held Products, Inc. Image reader comprising CMOS based image sensor array
US11323650B2 (en) 2005-03-11 2022-05-03 Hand Held Products, Inc. Image reader comprising CMOS based image sensor array
US10721429B2 (en) 2005-03-11 2020-07-21 Hand Held Products, Inc. Image reader comprising CMOS based image sensor array
US10735684B2 (en) 2005-03-11 2020-08-04 Hand Held Products, Inc. Image reader comprising CMOS based image sensor array
US11323649B2 (en) 2005-03-11 2022-05-03 Hand Held Products, Inc. Image reader comprising CMOS based image sensor array
US10958863B2 (en) 2005-03-11 2021-03-23 Hand Held Products, Inc. Image reader comprising CMOS based image sensor array
US11238251B2 (en) 2005-06-03 2022-02-01 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array
US11625550B2 (en) 2005-06-03 2023-04-11 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array
US12020111B2 (en) 2005-06-03 2024-06-25 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array
US12001913B2 (en) 2005-06-03 2024-06-04 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array
US10949634B2 (en) 2005-06-03 2021-03-16 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array
US10691907B2 (en) 2005-06-03 2020-06-23 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array
US11604933B2 (en) 2005-06-03 2023-03-14 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array
US11238252B2 (en) 2005-06-03 2022-02-01 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array
US12001914B2 (en) 2005-06-03 2024-06-04 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array
US7583304B2 (en) 2005-12-12 2009-09-01 The Swatch Group Research And Development Ltd Method of obtaining an image using an image sensor with a broad dynamic range
EP1796373A1 (de) * 2005-12-12 2007-06-13 The Swatch Group Research and Development Ltd. Abbildungsverfahren mit Hilfe eines Bildsensors mit grossem dynamik Bereich
WO2015052864A1 (en) * 2013-10-10 2015-04-16 Sony Corporation Image-capturing device, radiation detection apparatus, and control method for image-capturing device
CN112565642A (zh) * 2020-11-27 2021-03-26 上海华力微电子有限公司 一种具有线性对数输出的cis传感器
US12026580B2 (en) 2022-10-28 2024-07-02 Hand Held Products, Inc. Apparatus having hybrid monochrome and color image sensor array

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