EP1126351B1 - Circuit pour produire une tension constante - Google Patents

Circuit pour produire une tension constante Download PDF

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Publication number
EP1126351B1
EP1126351B1 EP20010101805 EP01101805A EP1126351B1 EP 1126351 B1 EP1126351 B1 EP 1126351B1 EP 20010101805 EP20010101805 EP 20010101805 EP 01101805 A EP01101805 A EP 01101805A EP 1126351 B1 EP1126351 B1 EP 1126351B1
Authority
EP
European Patent Office
Prior art keywords
transistor
emitter
terminals
transistors
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP20010101805
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German (de)
English (en)
Other versions
EP1126351A1 (fr
Inventor
Wolfgang Horn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
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Publication date
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Publication of EP1126351A1 publication Critical patent/EP1126351A1/fr
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to a circuit arrangement for generating constant voltages according to the bandgap principle (bandgap principle), in which the forward voltages of two P-N junctions are used to generate a reference voltage, according to the preamble of claim 1.
  • bandgap principle bandgap principle
  • a further problem can result, for example, according to FIG. 1 in the case of a barrier-layer-isolated mixing technology on a p-substrate 13.
  • the diode formed from an n-type drain terminal 11 and the p-type substrate 13 becomes conductive, and the charge carriers injected into the substrate 13 form the emitter current of a parasitic npn bipolar junction transistor 12.
  • All epitaxial n-wells 10a, ... 10x (for example BJT collectors) of the circuit represent for this transistor 12 potential collectors from which collector currents Icl, .. Icx can be subtracted during reverse operation of the DMOS power transistor.
  • This can lead to sensitive other circuit parts with high impedance connected n-wells, such as a circuit arrangement of the type mentioned in the band-gap principle, be impaired in their function or even fail completely.
  • EP-A-0 680 048 A1 describes a reference voltage circuit operating according to the bandgap principle which has two bipolar transistors whose collector terminals are connected to a supply potential and whose base terminals are short-circuited and likewise connected to the supply potential via a resistor.
  • the emitter terminals of the two bipolar transistors are connected to a circuit arrangement for adjusting the currents through the bipolar transistors to reference potential.
  • the resistor connected to the base terminal of the bipolar transistors is likewise connected to reference potential via a transistor of this circuit device.
  • EP-A-0 329 247 A1 and US-A-4,348,633 describe further bandgap-mode reference voltage circuits.
  • the invention has for its object to provide a circuit arrangement which produces a temperature and operating voltage independent constant voltage with a bandgap reference in other limits and which is particularly insensitive to influences of the reverse operation described above.
  • the object is achieved according to claim 1 with a circuit arrangement of the type mentioned, which is characterized by the following features: a first and a second transistor whose base terminals are connected to each other via a first resistor and whose collector terminals are applied to a supply voltage, and a second resistor , which is connected between the base terminal of the first transistor and the supply voltage, so that by the difference of the base-emitter voltages across the transistors through the first and second resistor is generated according to ground flowing reference current, and a reference to the supply voltage sourced reference voltage at the emitter of the first transistor can be tapped.
  • an output buffer / driver is provided, with which the reference voltage is divided and passed at low impedance at an output.
  • the circuit arrangement preferably comprises a comparator with a current mirror circuit with which the emitter currents of the first and second transistors and the reference current are regulated to an equilibrium state in which these currents are substantially equal.
  • an actuator is provided with a start circuit for acting on the comparator, which has a third transistor, with which a voltage or current difference at the emitter terminals of the first and second transistor is controlled by driving a fourth and fifth transistor in the comparator.
  • the embodiment according to the invention comprises a bandgap circuit 1 for generating a reference voltage according to the bandgap principle, which is related to a positive supply voltage Vdd, an output buffer / driver 4 whose input is connected to the output of the bandgap circuit 1 and to the latter Output is applied to an output reference voltage Vref, a current and voltage comparator 2, which is insensitive to reverse current and is connected via a first and a second terminal A, B to the bandgap circuit 1, and an actuator 3 with start circuit, which acts on the comparator 2 ,
  • the reference voltage generated by the bandgap circuit 1 is divided to almost any desired values (for example ⁇ 1.26 volts) and provided at the output with low resistance.
  • the comparator 2 controls by means of the actuator 3, the bandgap circuit 1, wherein the condition to be met for the controlled state is the equality of the voltages at the two terminals A, B and the equality of the currents I1, I2 through these terminals.
  • FIG. 3 shows an overall circuit diagram of the preferred embodiment, wherein these components are each delimited by dashed lines.
  • the bandgap circuit 1 comprises a first and a second npn bipolar transistor T1, T2, whose base terminals are connected to each other via a first resistor R1.
  • the collector terminals are connected to a positive supply voltage Vdd, while the emitter terminal of the first transistor T1 is connected to the first terminal A and the emitter terminal of the second transistor T2 to the second terminal B.
  • the base terminal of the first transistor T1 is finally connected via a second resistor R2 to the supply voltage Vdd.
  • the comparator 2 comprises a fourth and a fifth bipolar pnp transistor T4, T5, whose base terminals are interconnected, wherein the emitter of the fourth transistor T4 via the second terminal B to the emitter of the second transistor T2 and the emitter of the fifth transistor T5 via the first terminal A is connected to the emitter of the first transistor T1.
  • the collector of the fifth transistor T5 is connected to ground via a first (eg MOSFET) transistor M1 and to a gate of this transistor M1.
  • the collector of the fourth transistor T4 is grounded via a third MOSFET transistor M3.
  • a second MOSFET transistor M2 is provided which allows a reference current Iref to flow from the base of the second transistor T2 to ground.
  • a temperature-independent bias current I BIAS can be generated to ground via a tenth MOSFET transistor M10 and coupled out as required.
  • the circuit arrangement can thus additionally as a generator for a temperature-compensated bias current I BIAS for the relevant chip serve and thus include an inherent "auto-biasing".
  • the bases of the MOSFET transistors M1, M2, M3, M10 are connected together.
  • the actuator 3 comprises a third npn bipolar transistor T3 whose collector is connected to the positive supply voltage Vdd and its emitter to the interconnected base terminals of the fourth and fifth transistors T4, T5 and via a third resistor R3 to ground. Between the supply voltage Vdd and ground, a fourth and a seventh MOSFET transistor M4, M7 are connected in series, between which the base of the third transistor T3 is located. The gate of the fourth MOSFET transistor M4 is connected to the collector of the fourth transistor T4, the gate of the seventh MOSFET transistor M7 is connected to the gate of an eighth MOSFET transistor M8 connected in series with a ninth MOSFET transistor M9 between the supply voltage Vdd and mass is.
  • the gate of the seventh and eighth MOSFET transistors M7, M8 is connected between the eighth and ninth MOSFET transistors M8, M9.
  • the gate of the ninth MOSFET transistor M9 is connected to the interconnected gate terminals of the first, second, third and tenth MOSFET transistors M1, M2, M3, M10.
  • the output buffer / driver 4 comprising a sixth bipolar PNP transistor T6, whose emitter via a series connection of a fourth and fifth resistor R4, R5 to the supply voltage Vdd and its collector via a fifth MOSFET transistor M5 Mass is connected. The emitter is also connected via a sixth MOSFET transistor M6 to ground whose gate is connected to the collector of the sixth transistor T6.
  • the base of the fifth MOSFET transistor M5 is in turn connected to the interconnected gate terminals of the first, second, third, ninth and tenth MOSFET transistors M1, M2, M3, M9, M10.
  • the reference voltage Vref is tapped at the voltage divider formed by the fourth and fifth resistors R4, R5.
  • An essential core of the invention is the implementation of the bandgap principle in the bandgap circuit 1, which is also independent, that is, without the circuit parts 2 to 4 can be used. However, it is particularly suitable for use in combination with the comparator 2, through which the insensitivity of the overall circuit compared to the aforementioned reverse currents results. Furthermore, the temperature response of the difference between the two base-emitter voltages of T1 and T2 dU BE is compensated with the current-determining first resistor R1, so that the reference current Iref is temperature-independent.
  • the circuit is self-sufficient, resulting in two possible operating points, on the one hand a desired and on the other hand such an operating point, in which the reference current Iref is equal to zero and the reference voltage Vref is equal to the positive supply voltage Vdd.
  • the starting circuit which is often difficult to implement in known circuits having this property, is integrated according to the invention into the actuator 3, without requiring a substantial additional outlay.
  • the reference voltage results as the sum of the voltage drop across the second resistor R2 generated by the reference current Iref and the voltage U BE at the base-emitter diode of the first transistor T1.
  • the reference voltage Vref can be tapped off at the first terminal A and related to the positive supply voltage Vdd.
  • the comparator 2 controls in conjunction with the actuator 3, the bandgap circuit 1 always to this equilibrium state, in which the reference current Iref equal to the first and the second current I1, I2 (emitter current of the first and second transistor T1, T2) through the first and second terminal A, B is.
  • This current condition is realized by the current mirror circuit formed by the first to third MOSFET transistors M1, M2, M3.
  • T4, T5 By the upstream of the current mirror pnp transistors T4, T5, a potential difference at the terminals A, B directly results in a current difference and is therefore also regulated.
  • This control process takes place in detail as follows:
  • the third resistor R3 forms a current sink for the third transistor T3 and simultaneously acts as a starting resistor by pulling in the de-energized state, the base terminals of the fourth to sixth transistor T4, T5, T6 to ground and thus excludes the undesirable operating point.
  • the optional output buffer / driver 4 drives the sixth transistor T6 with a base potential and an emitter current which is identical to those at the fourth and fifth transistor T4, T5.
  • the emitter potential corresponds to the potential at the first and second terminals A, B and thus the reference voltage Vref.
  • the requirement of the identical emitter current is met by the fifth and sixth MOSFET transistor M5, M6.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Claims (6)

  1. Circuit pour générer des tensions constantes selon le principe de la largeur de bande interdite,
    caractérisé par
    - un premier et un deuxième transistors (T1, T2) dont les bornes de base sont reliées l'une à l'autre par une première résistance (R1) et dont les bornes de collecteur sont reliées à une tension d'alimentation (Vdd),
    - une deuxième résistance (R2) montée entre la borne de base du premier transistor (T1) et la tension d'alimentation (Vdd),
    - un comparateur (2) relié aux bornes d'émetteur du premier et du deuxième transistors (T1, T2), à la première résistance (R1) et à la masse, qui génère un courant de différence (Iréf) traversant la première et la deuxième résistances (R1, R2) vers la masse en fonction de la différence des tensions d'émetteur de base au niveau des transistors (T1, T2),
    une tension d'alimentation (Vdd) se référant à la tension de référence pouvant être prélevée au niveau de l'émetteur du premier transistor (T1).
  2. Circuit selon la revendication 1,
    caractérisé par
    un tampon de sortie/excitateur (4) comprenant une sortie à basse impédance délivrant une tension de référence (Vréf) divisée qui dépend de la tension de référence au niveau de l'émetteur du premier transistor (T1).
  3. Circuit selon la revendication 1 ou 2,
    caractérisé en ce que
    le comparateur (2) présente un circuit de courant symétrique (M1, M2, M3) qui reçoit les courants d'émetteur (I1, I2) des premier et deuxième transistors (T1, T2) ainsi que le courant de référence, et configuré pour régler les courants d'émetteur (Iréf) essentiellement identiques.
  4. Circuit selon la revendication 3,
    caractérisé en ce que
    le comparateur (2) présente un quatrième et un cinquième transistors (T4, T5) dont les bornes des grille sont reliées l'une à l'autre et dont les bornes d'émetteur sont reliées aux bornes d'émetteur du premier ou du deuxième transistor (T1, T2), de sorte qu'une différence de tension sur ces bornes engendre une différence de courant régulée à l'aide du circuit de courant symétrique (M1, M2, M3).
  5. Circuit selon la revendication 3 ou 4,
    caractérisé par
    un dixième transistor (M10) commandé par le circuit de courant symétrique, qui fournit un courant de dérivation (IBIAS) indépendant de la température.
  6. Circuit selon l'une quelconque des revendications 3 à 5,
    caractérisé en ce qu'
    un organe de réglage (3) avec un circuit de démarrage pour solliciter le comparateur (2), présente un troisième transistor (T3) qui règle une différence de tension ou de courant aux bornes d'émetteur du premier et du deuxième transistors (T1, T2) par la commande du quatrième et du cinquième transistors (T4, T5).
EP20010101805 2000-02-16 2001-01-26 Circuit pour produire une tension constante Expired - Lifetime EP1126351B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2000106950 DE10006950C1 (de) 2000-02-16 2000-02-16 Schaltungsanordnung zur Konstantspannungs- und / oder Konstantstromerzeugung
DE10006950 2000-02-16

Publications (2)

Publication Number Publication Date
EP1126351A1 EP1126351A1 (fr) 2001-08-22
EP1126351B1 true EP1126351B1 (fr) 2007-03-28

Family

ID=7631122

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20010101805 Expired - Lifetime EP1126351B1 (fr) 2000-02-16 2001-01-26 Circuit pour produire une tension constante

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EP (1) EP1126351B1 (fr)
DE (2) DE10006950C1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103699171B (zh) * 2012-09-27 2015-10-28 无锡华润矽科微电子有限公司 具有高稳定性的能隙基准电流电路结构

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4348633A (en) * 1981-06-22 1982-09-07 Motorola, Inc. Bandgap voltage regulator having low output impedance and wide bandwidth
EP0329247B1 (fr) * 1988-02-19 1993-12-29 Koninklijke Philips Electronics N.V. Circuit de tension de référence à bande interdite
EP0680048B1 (fr) * 1994-04-29 2000-03-29 STMicroelectronics, Inc. Circuit de référence du type bandgap

Also Published As

Publication number Publication date
DE50112251D1 (de) 2007-05-10
EP1126351A1 (fr) 2001-08-22
DE10006950C1 (de) 2002-01-24

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