Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
  • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
  • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Definitions

• the invention relates to a synchronous circuit, such as a synchronous integrated memory, for example .
• Synchronous SpeI ⁇ cher such as synchronous DRAMs (SDRAMs) or Rambus DRAMs (RDRAMs), having data terminals via which data are transmitted in synchronism with a se from a control unit, such as beispielswei ⁇ a controller that transmitted the first clock signal.
• SDRAMs synchronous DRAMs
• RDRAMs Rambus DRAMs
• a first phase locked loop (core DLL) generates six intermediate clocks, each phase-shifted by 30 °, from the input clock.
• a second phase control loop (peripheral DLL) connected downstream of the first control loop generates the output clock by interpolating two adjacent intermediate clocks.
• the DLL circuit proposed by Sidiropoulos and Horowitz is therefore regulated in two stages:
• the phase position of the intermediate clocks is regulated to a phase difference of exactly 30 ° in each case and in the second control loop, the phase position of the output clock pulse is regulated so that it is subsequently in phase with the input clock pulse.
• the second control loop selects to generate the output clock depending on the fixed the phase deviations from the input clock which were the most suitable for this purpose, were those of the intermediate clocks adjacent to one another for carrying out the interpolation. If, for example, larger temperature changes lead to phase deviations of the intermediate clocks compared to their setpoints, the first control loop adjusts. Under certain circumstances, this readjustment can lead to a sudden change in the phase position of the intermediate clocks. Since the second control loop always uses two of these intermediate clocks for its interpolation, these sudden changes also have sudden changes in the output clock generated by the second control loop.
• the invention has for its object a synchronous
• the second clock should have a phase position that is as rigid as possible to the first clock, but the data transmission via the driver should not be subjected to sudden changes in the second clock.
• the synchronous circuit can be, for example, a synchronous memory or a processor. It is only essential that the circuit is used for data transmission synchronous with a first clock.
• the synchronous integrated circuit has a clock input for supplying a first clock and a clock generator for generating a second clock, which is phase-locked to the first clock. That is, the two bars have a fixed Phase relationship to each other.
• the clock generator has an input which is connected to the clock input, and a clock output for outputting the second clock which is connected to a control input of a data transmission unit which is used for outputting data from and / or for reading in data serves essentially in sync with the first bar.
• the clock generator has at least two series-connected control loops which are used to regulate the phase position of the second clock cycle, the first control loop being used to generate at least two intermediate clock cycles from the first clock cycle, each of which has a specific phase relationship to the first clock cycle, and wherein the second control loop is used to generate the second cycle from the intermediate cycles.
• the circuit has a deactivation unit for deactivating the regulation of the first control circuit during the transmission of data by the data transmission unit, so that the regulation of the phase position of the intermediate clocks is interrupted and corresponding control signals for setting these phase positions are kept constant.
• the control of the first control loop is deactivated during the transmission of data, there are no sudden changes in the phase positions of the intermediate clock cycles during the data transmission. For this reason, there are no otherwise sudden changes in the phase position of the second cycle, which the second control loop first had to correct. If, on the other hand, no data is transmitted from the data transmission unit, abrupt changes in the phase position of the intermediate clocks and the second clock are not critical, since the second clock m is not required for controlling the data transmission unit in these time periods. The control of the first control loop can therefore always be activated if no data is to be transmitted from the data transmission unit. Since periods in which data are transmitted and periods in which no data are to be transferred alternate during normal operation, at E ach reactivate the first control loop an ge ⁇ precise adjustment of the phase positions of the intermediate clock.
• the data transmission unit can be an input and / or an output circuit of the synchronous circuit.
• Phase drift of the intermediate clock is chiefly by temperature ⁇ ing temperatures of the circuit drawn during operation.
• large ⁇ ßere temperature fluctuations take place only within rela- tively long periods of time. It is therefore not critical to deactivate the first control loop during the generally relatively short periods of time during which the data transmission takes place. Since the second control loop remains activated during the data transmission, sufficient regulation of smaller disturbances is also ensured during the data transmission.
• the clock generator can be designed, for example, like the two-stage DLL circuit described in the above-mentioned article by Sidiropoulos and Horowitz.
• the first control loop then generates from the first cycle a plurality of intermediate clocks phase-shifted with respect to one another by the same phase angle in each case, and its second control loop generates the second clock cycle by interpolation between two intermediate clock pulses which are adjacent in terms of the phase.
• the first control loop has a phase detector for determining the phase difference between at least one of the intermediate clocks and the first clock.
• the first control loop provides its control signals, which are used to set the phase positions of the intermediate clocks, as a function of an output signal of the phase detector em.
• the first control circuit has a memory unit for storing the control signals, the memory content of which is constantly changed when the first control circuit is activated and whose memory content remains constant when the first control circuit is deactivated.
• the S peicher bain advantageously provides for the con- stanthalten of the control signals during the deactivation of the first control loop, that is, during the data transmission through the ubertragungsemheit.
• the synchronous circuit has an input for receiving a control signal from an external control unit which is used to control the data transmission by the data transmission unit, the deactivation unit of the memory deactivating the control of the first control loop as a function of the control signal.
• the control unit can be, for example, a controller or microprocessor which controls the transmission of data via the data transmission unit by addressing the memory. Since in this case the external control unit determines when a data transmission is to take place, it can also be used without problems to transmit the corresponding control signal to the deactivation unit, so that the first control circuit is deactivated at the same time as the data transmission to be carried out.
• the circuit has an output for transmitting a control signal to an external control unit, which is used to control the data transmission by the data transmission unit, the control signal indicating whether the first control loop is deactivated by the deactivation unit.
• an external control unit which is used to control the data transmission by the data transmission unit, the control signal indicating whether the first control loop is deactivated by the deactivation unit.
• the to the external control unit via it Telte control signal indicates that when the data transfer above may be started over the ubertragungsemheit since then the first loop st disabled, and when not allowed to be transferred ü Since ⁇ th, as the first control loop is active.
• FIG. 1 shows an exemplary embodiment of the synchronous circuit in the form of an integrated memory
• Figure 2 shows an exemplary embodiment of a first control loop from Figure 1 and
• FIG. 3 shows a phase diagram for intermediate clocks from FIG. 2.
• FIG. 1 shows a synchronous integrated memory M, of which only the components essential for the invention are shown.
• the memory M has a memory area MC with memory cells in which data are stored. It also has a data transmission unit or an interface DRV, which transmits data 7 to be stored to the memory area MC and data 7 to be read out from the memory area MC to the outside of the memory M.
• An external control unit CTR for example a microprocessor, is arranged outside the memory. The control unit CTR transmits data to be written into the memory M to the data transmission unit DRV. In addition, data to be read out are transmitted from the data transmission unit DRV to the external control unit CTR.
• the memory M furthermore has an internal control unit 3, to which control signals 4 are supplied by the external control unit CTR, the dependence of which signals and addressing the memory cells within the memory area MC Activation or deactivation of the memory cells within the memory area MC Activation or deactivation of the memory cells within the memory area MC Activation or deactivation of the memory cells within the memory area MC Activation or deactivation of the memory cells within the memory area MC Activation or deactivation of which signals and addressing the memory cells within the memory area MC Activation or deactivation of which signals and addressing the memory cells within the memory area MC Activation or deactivation of which signals and addressing the memory cells within the memory area MC Activation or deactivation of which signals and addressing the memory cells within the memory area MC Activation or deactivation of which signals and addressing the memory cells within the memory area MC Activation or deactivation of which signals and addressing the memory cells within the memory area MC Activation or deactivation of which signals and
• the memory M For the synchronous output of the data 7 by the data transmission unit DRV with the first clock CLKE, the memory M has a clock generator G, which generates a second clock CLKINT, which is phase-rigid with respect to this, from the first clock signal CLKE.
• the second clock CLKINT is fed to a control input of the data transmission unit DRV in order to achieve a transmission of the data 7 clocked by the second clock CLKINT.
• the clock generator G m Figure 1 has two control loops 1, 2 connected in series.
• the first clock CLKE is fed to the input of the first control circuit 1.
• the first control loop 1 has eight outputs, on which it generates eight intermediate clocks CLKi, each of which has a phase shift of 45 ° with respect to one another.
• the eight intermediate clocks CLKi are fed to inputs of the second control circuit 2.
• the second control loop At its output, which is connected to the control input of the data transmission unit DRV, the second control loop generates the second clock CLKINT, which is synchronous with the first clock CLKE.
• FIG. 2 shows an exemplary embodiment of the first control loop 1.
• the first control loop 1 and the second control loop 2 form a DLL circuit.
• the second control loop 2 but also some components of the first control loop 1, can be designed like the control loops in the article by Sidiropoulos and Horowitz mentioned at the beginning.
• the first control circuit 1 has four analog delay elements D, which are arranged in series in a series connection and whose delay times are adjustable.
• One Input of the series is the first CLKE leads supplied ⁇ .
• Each Verzogtechnischsglied D effects a phase shift of its input clock ⁇ bung 45 °.
• a driver circuit T Before and after each delay Verzo ⁇ membered D a driver circuit T is arranged, which serves to amplify the input and output signals of the delay elements D distorted, and for outputting the inverted and non m m inverted form. As output signals of the first control circuit, the driver circuits T each transmit the corresponding clock signal phase-shifted by the associated delay element as the intermediate clock CLKi and the clock / CLKi inverted to the second control circuit 2.
• FIG. 3 shows a phase diagram which shows the phase relationship of the eight intermediate clocks CLKi in the regulated state.
• the inverted output signal / CLK4 of the last delay element D of the series circuit m FIG. 2 is fed to a first phase detector ⁇ l, which compares the phase position of the phase position of the first clock CLKE. The result of the comparison is transmitted to a control unit 10 of the first control circuit 1, which generates corresponding digital control signals 20 which are used to set the delay by the delay elements D.
• the control signals 20 are stored in a memory unit MEM and are continuously updated in the event of phase errors detected by the first phase detector ⁇ l.
• the control signals stored in the memory unit MEM are fed to a digital / analog converter D / A, which supplies the control signals of the delayed elements D to the control signals which are converted to analog.
• control unit 10 of the first control loop and its memory unit MEM are digital components.
• these components can also be implemented analogously in other exemplary embodiments of the invention.
• the delay elements D game about digital components. Then the need for the D ⁇ g ⁇ tal- / analog converter at the output of the memory unit MEM.
• the first phase detector ⁇ l can also be constructed either analog or digital.
• the eight intermediate clocks CLKi generated by the first control loop 1 are fed to the second control loop 2.
• the second control circuit 2 selects phasenudgeig adjacent the respective 45 ° phase difference having intermediate clocks CLKINT from . Furthermore, the second control circuit 2 carries out an interpolation between these two selected intermediate clock cycles CLKi m depending on the phase difference determined by the second phase detector ⁇ 2.
• the memory M has a deactivation unit AKT, the output of which is connected to the control unit 10 of the first control circuit 1 according to FIG.
• the deactivation unit AKT activates the first control loop 1 whenever no data is to be transmitted from the data transmission unit DRV. It deactivates the first control loop 1 when data 7 are transmitted by the data transmission unit DRV. In the activated state, the first control loop 1 regulates the phase positions of its intermediate clocks CLKi by changing its control signals 20. However, if it is deactivated by the deactivation unit AKT, the regulation of the first control circuit 1 is interrupted and its control unit 10 no longer adapts the control signals stored in the memory unit MEM.
• control signals stored in the memory unit MEM are kept constant, even if the first phase detector ⁇ l detects a phase deviation.
• the control signals 20 which are kept constant mean that a change in the phase position of the intermediate clocks CLKi can only be caused by error influences such as , will be drawn game as temperature changes, not per ⁇ but under a scheme.
• the second control circuit 2 While the first control loop 1 is sporadically disabled, the second control circuit 2 is constantly activated so that he gel during the transmission of data 7 on the ubertra ⁇ gungsemheit DRV the phase position of the second clock CLKINT re ⁇ .
• the well in the deactivated state Re first ⁇ gel Vietnamesees 1 ensures an accurate phase control of the second clock CLKINT.
• the deactivation of the first control circuit 1 during the transmission of data 7 by the data transmission unit DRV has the advantage that during this period the control unit 10 of the first control circuit 1 does not change the control signals 20 stored in the memory unit MEM. Thus, no sudden change in the delay times of the delay elements D is triggered.
• the second control circuit 2 is sufficient to compensate for the errors occurring during the deactivation of the first control circuit 1.
• the synchronicity with the external clock signal CLKE is thus ensured without sudden changes which would manifest themselves in a phase jitter of the internal clock signal CLKINT.
• the first control circuit 1 is reactivated by the deactivation unit AKT, so that even larger errors can then be corrected with the participation of the first control circuit 1.
• the control emissions occurring due to sudden changes in the control signals 20 within the first control circuit 1 are then harmless, since the second clock CLKINT is not required to control the data transmission unit DRV during these periods.
• activated first control loop 1 that is before the night vi ⁇ th data output by the ubertragungsemheit DRV, it follows ⁇ so optimum control of the internal clock signal C LKINT.
• the first control circuit 1 is disabled and the exak ⁇ te phase position of the second clock CLKINT is mainly ensured by the control of the second control loop. 2
• FIG. 1 shows that the memory M has an input IN, via which the deactivation unit AKT is supplied with a control signal 5 from the external control unit CTR.
• the external control unit CTR controls the activation state of the first control circuit 1 via this control signal 5.
• the external control unit CTR uses the control signal 5 to ensure that the first control circuit 1 is deactivated by the deactivation unit AKT whenever the external control unit CTR internal control unit 3 of the memory M transmits the instruction for outputting data 7 stored in the memory area MC or for reading data 7 to be stored. In this way it is ensured that the deactivation of the control circuit 1 takes place at the same time as a transmission of data 7 by the data transmission unit DRV.
• this control signal 5 can also be derived from the control signals 4 of the external control unit CTR transmitted to the internal control unit 3 of the memory M within the memory, so that no additional input of the memory is necessary.
• the memory M can also (as shown in dashed lines in FIG. 1) have an output OUT for outputting a control signal 6 from the deactivation unit AKT to the external control unit CTR.
• the deactivation unit AKT tells the external control unit CTR when it activates the first control loop 1 and when it deactivates it.
• the control signal 6 in that the first control circuit 1 is just at cardt, the external control unit CTR of the internal control unit 3 no A MANUAL for transmitting data 7 transmitted. Only when the Deffer michsemheit AKT telling it that the first has been disabled re gel Vietnamese 1, the transmission takes place of a command for transferring the data 7.
• the memory has the advantage that the activation or deactivation of the first Control circuit 1 can be self-controlled by the memory M.
• the deactivation unit AKT tells the external control unit CTR when it activates the first control loop 1 and when it deactivates it.
• the control signal 6 in that the first control circuit 1 is just at cardt, the external control unit CTR of
• AKT then contain a timer unit and carry out the activation or deactivation at regular, not too long time intervals, so that there is always an optimal regulation of the phase position of the second clock CLKINT og-
• control loops are connected in series.
• the control loops arranged at the input of the clock generator G serve to roughly regulate the phase position of the second clock CLKINT.
• control loops which are arranged closer to the output of the clock generator G, serve to regulate its phase position ever more precisely.
• the first control loop 1 is therefore responsible for the coarse control and the second control loop 2 for fine control of the phase position of the second clock CLKINT. If there are more than two control loops within the clock generator G, it makes sense to always deactivate those control loops (one or more) that are responsible for the coarse control and to keep the fine control activated.
• control loops 1, 2 described here form a DLL circuit
• the invention can also be implemented with other control principles, for example using PLL (phase locked loop) circuits.
• PLL phase locked loop
• the clock generator G has an at least two-stage control loop, as shown in FIG. 1.
• the control of crizkrei ⁇ ses is not deactivated at each transmission of data by the data transmission unit DRV. 1 For example, this can only be done in a normal operating mode of the memory M, while in a test operating mode the first control loop 1 remains activated continuously.
• the first control circuit 1 is not reactivated each time when no data is being output, but only during certain operating states of the memory M, for example during its initialization or a calibration of output drivers within the data transmission unit DRV.
• the first control loop it is possible for the first control loop to be deactivated only by the data transmission unit DRV either when outputting or when reading in data 7.

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Manipulation Of Pulses (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
• Dram (AREA)
• Control Or Security For Electrophotography (AREA)
• Information Transfer Systems (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=7881416

Family Applications (1)

Country Status (7)

Families Citing this family (3)

Family Cites Families (7)

• 1998
  • 1998-09-18 DE DE19842818A patent/DE19842818C2/de not_active Expired - Fee Related
• 1999
  • 1999-09-08 EP EP99953713A patent/EP1114422A1/de not_active Ceased
  • 1999-09-08 WO PCT/DE1999/002845 patent/WO2000017883A1/de not_active Application Discontinuation
  • 1999-09-08 JP JP2000571458A patent/JP2003505896A/ja not_active Ceased
  • 1999-09-08 KR KR1020017003280A patent/KR100646892B1/ko not_active IP Right Cessation
  • 1999-09-14 TW TW088115812A patent/TW437225B/zh not_active IP Right Cessation
• 2001
  • 2001-03-19 US US09/811,881 patent/US6779124B2/en not_active Expired - Lifetime

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events