EP1080410A1 - Emulateur a tres haute integration comprenant des processeurs et des circuits reconfigurables - Google Patents

Emulateur a tres haute integration comprenant des processeurs et des circuits reconfigurables

Info

Publication number
EP1080410A1
EP1080410A1 EP00911468A EP00911468A EP1080410A1 EP 1080410 A1 EP1080410 A1 EP 1080410A1 EP 00911468 A EP00911468 A EP 00911468A EP 00911468 A EP00911468 A EP 00911468A EP 1080410 A1 EP1080410 A1 EP 1080410A1
Authority
EP
European Patent Office
Prior art keywords
vlsi
external interface
processing module
reconfigurable
monitoring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00911468A
Other languages
German (de)
English (en)
Inventor
Chong Min Kyung
In Cheol Park
Seung Jong Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Korea Advanced Institute of Science and Technology KAIST
Original Assignee
Korea Advanced Institute of Science and Technology KAIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Korea Advanced Institute of Science and Technology KAIST filed Critical Korea Advanced Institute of Science and Technology KAIST
Publication of EP1080410A1 publication Critical patent/EP1080410A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

  • the present invention relates to an apparatus for verifying a VLSI design through emulation, and more particularly to a VLSI emulator
  • processors and reconfigurable chips for verifying the functional correctness of the design of a VLSI together with a system to which the VLSI will be attached before manufacturing the design into a chip.
  • the host computer and the ASIC emulator consists of a lot of pin signal values required for all pins.
  • the host computer uses software which is slow to execute the whole process related to generation
  • the host computer is connected to the ASIC emulator through a cable whose transmission capability may be slow enough to affect the system.
  • the system should have modules and functions unrelated to emulation, which makes the system unnecessarily bigger.
  • the present invention proposes a scheme for enhancing the emulation speed in order to effectively verify the functional ->
  • the emulation module of a VLSI being designed is divided into
  • a functional part and an external interface part where the functional part is executed by a processing module having at least one processor while the external interface part is executed by an external interface signal processor using field-reconfigurable circuits such as FPGA's(Field
  • the present invention intends to remove or at least alleviate the above problems with Watkins' ASIC emulator by proposing a VLSI
  • emulator being comprised of processor(s) and reconfigurable circuits(s) which can be used to freely verify a VLSI design at its early stage as well
  • Another object of the present invention is to enhance the emulation speed and generate pin signals more timely and appropriately by adopting a processor-based processing module for the functional part of a VLSI
  • An interface control packet is employed for communication between the processing module and the reconfigurable circuits(s).
  • the present invention provides an apparatus for verifying the functional part and the external interface part of a VLSI, separately, using a VLSI emulator comprising: a processing module including at least one processor for verifying the functional part of the VLSI; and an external interface signal processor for verifying the external interface part of the VLSI.
  • the external interface signal processor is implemented using reconfigurable circuits to generate the required pin signals. Communication between the processing module and the external interface signal processor consists of commands and data.
  • the processing module as comprises at least one processor; and at least one memory such as ROM and/or RAM; and a bus for connecting the processor and the memory.
  • the external interface signal processor may
  • a buffer and controller for buffering and synchronizing to fill up the speed gap between the processing module and the pin signal processing unit; a channel for communication of an interface control packet between the processing module and the external interface signal processor; and a socket for connecting the external interface signal processor to a target system to which the VLSI for verification is attached.
  • the apparatus may further comprise a monitoring/ controlling port
  • a monitoring/ controlling computer for monitoring and controlling the emulation states externally, downloading a software model and a monitoring code to the processing module, and reconfiguring the reconfigurable element(s) in the external interface signal processor
  • FIG. 1 shows an example for the explanation of the VLSI emulator according to the present invention
  • FIG. 2 shows an example of a processor-based processing module
  • FIG. 3 shows an example of an external interface signal processor.
  • FIG. 1 is for illustrating an emulation system (or emulator) and its
  • the model of a VLSI to be verified is divided into a software model which represents the functional part of a VLSI and an external interface model which represents the actions of the VLSI related with the external
  • an emulator denoted as 2 includes a processing module 3 having at least one processor for executing the software model
  • an external interface signal processor 4 having reconfigurable circuit (e.g. FPGA) to interface with the external hardware according to the external interface model.
  • the processing module 3 transmits a corresponding interface control packet to the external interface signal processor 4 through a channel 5 when there is a need to
  • the external interface signal processor 4 interprets the interface control packet received to generate and transmit a sequence of electrical signals to a target system 9.
  • the external interface signal processor 4 also reads in electrical signals from the target system 9 to interpret and transmit them to the processing
  • the target system 9 has a socket 6 to which electrical pin signals
  • the socket 6 enables the target system 9 to be electrically connected to the target system 9 consisting of other VLSI chip(s) denoted as 7 and other socket(s) 8 connected to another emulators 1 1 which can be the VLSI emulator described herewith or any other type of emulator.
  • the emulator 2 can be connected to a host computer 10 through a monitoring/ controlling port 1 in order to externally monitor and control the internal state(s) of emulation.
  • the monitoring/ controlling port 1 is used to download the software model of the VLSI chip to be verified from host computer 10 to
  • FIG. 2 is for illustrating an example for the implementation of the processing module 3.
  • the software model for the functional part of a VLSI to be verified is compiled into a form to be executed in a processor 12 in the processing module 3, and then stored in a memory 13 together with a monitoring code.
  • the processor 12 executes the software
  • the memory 13 is composed of ROM and/or RAM, and may have a code, already processed, or receive the code through the monitoring/ controlling port 1.
  • the processor 12 transmits an interface control packet of the software model to the external
  • the interface control packet is composed of a write command, an address and data to be written.
  • the interface control packet is composed of a read command and an address. Then, after confirming that the external interface signal processor 4 reads data in the
  • the interface control packet is sent to bring the data.
  • the emulation state is controlled and monitored by commands, transmitted from the host computer 10 through the monitoring/ controlling port 1.
  • FIG. 3 is illustrates an example of the implementation of the external interface signal processor 4, where the interface control packet from the processing module 3 through the channel 5 is stored in a buffer 15 through a controller 14. Commands and data of the packet are generated according to the sequence of signals by a pin signal processing
  • Array is either reconfigured by a reconfiguring code stored in the memory 13, which can be ROM or a reconfiguration-dedicated ROM/RAM, or downloaded through the monitoring/ controlling port 1 before the emulation starts.
  • the value read from the socket 6 via the pin signal processing unit 16 is stored in the buffer 15, which is then informed to the processing module 3. After that, the processing module 3 takes the stored value.
  • the buffer 15 plays the role of buffering between the processing module 3 and the pin signal processing unit 16.
  • the pin signal processing unit 16 compiles data in the buffer 15 into a sequence of electrical signals, and transmits them to the socket
  • the present invention as constructed above enables one to perform the emulation at the early stage of the VLSI design only with the functional description of the VLSI, i.e., before the gate-level or hardware description of the VLSI is available. Therefore, the present invention

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

L'invention porte sur un appareil permettant de vérifier une conception VLSI à u premier étage ainsi qu'à un second étage, et notamment un émulateur VLSI basé sur des processeurs et des microcircuits reconfigurables. Le modèle du microcircuit VLSI est divisé en une partie fonctionnelle et une partie d'interface externe. La partie fonctionnelle est exécutée par un module de traitement ayant au moins un processeur, et la partie d'interface externe est exécutée par un processeur de signaux d'interface externe de façon à générer des signaux de code réels. La partie interface externe est mise en oeuvre à l'aide de circuits reconfigurables par programmation des circuits. La communication entre la partie fonctionnelle et l'interface externe est réalisée par transmission et/ou réception de paquets de commande composés de commandes de contrôle et/ ou de données de contrôle. La partie fonctionnelle interne et la partie interface externe sont vérifiées sur un système cible à un premier étage de la conception VLSI, ce qui peut réduire le temps de conception du VLSI et de vérifier et concevoir tout le système.
EP00911468A 1999-03-19 2000-03-17 Emulateur a tres haute integration comprenant des processeurs et des circuits reconfigurables Withdrawn EP1080410A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1019990009307A KR100306596B1 (ko) 1999-03-19 1999-03-19 프로세서와 재설정가능 칩을 사용한 집적회로 에뮬레이터
KR9909307 1999-03-19
PCT/KR2000/000229 WO2000057273A1 (fr) 1999-03-19 2000-03-17 Emulateur a tres haute integration comprenant des processeurs et des circuits reconfigurables

Publications (1)

Publication Number Publication Date
EP1080410A1 true EP1080410A1 (fr) 2001-03-07

Family

ID=19577022

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00911468A Withdrawn EP1080410A1 (fr) 1999-03-19 2000-03-17 Emulateur a tres haute integration comprenant des processeurs et des circuits reconfigurables

Country Status (5)

Country Link
EP (1) EP1080410A1 (fr)
JP (1) JP3504572B2 (fr)
KR (1) KR100306596B1 (fr)
AU (1) AU3333600A (fr)
WO (1) WO2000057273A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100392569B1 (ko) * 2000-10-28 2003-07-23 (주)다이나릿시스템 반도체 칩의 논리 기능 검증용 에뮬레이터 장치 및 방법
KR100426304B1 (ko) * 2001-09-17 2004-04-08 한국전자통신연구원 스마트 카드 에뮬레이터 및 그 에뮬레이션 방법
KR100606946B1 (ko) 2001-11-30 2006-08-01 후지쓰 텐 가부시키가이샤 마이크로 컴퓨터의 로직 개발 장치
KR100427029B1 (ko) * 2001-12-29 2004-04-14 주식회사 하이닉스반도체 집적회로의 설계 검증 방법
JP2004234530A (ja) 2003-01-31 2004-08-19 Fujitsu Ten Ltd マイクロコンピュータのロジック開発装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5479355A (en) * 1993-09-14 1995-12-26 Hyduke; Stanley M. System and method for a closed loop operation of schematic designs with electrical hardware
EP0777180A2 (fr) * 1995-12-01 1997-06-04 Eagle Design Automation, Inc. Système et méthode pour la simulation de systèmes d'ordinateur combinant une interaction entre matériel et logiciel
EP0838772A2 (fr) * 1996-10-17 1998-04-29 Quickturn Design Systems, Inc. Procédé et dispositif pour la vérification d'une conception en utilisant émulation et simulation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5355528A (en) * 1992-10-13 1994-10-11 The Regents Of The University Of California Reprogrammable CNN and supercomputer
US5546562A (en) * 1995-02-28 1996-08-13 Patel; Chandresh Method and apparatus to emulate VLSI circuits within a logic simulator
US5638531A (en) * 1995-06-07 1997-06-10 International Business Machines Corporation Multiprocessor integrated circuit with video refresh logic employing instruction/data caching and associated timing synchronization

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5479355A (en) * 1993-09-14 1995-12-26 Hyduke; Stanley M. System and method for a closed loop operation of schematic designs with electrical hardware
EP0777180A2 (fr) * 1995-12-01 1997-06-04 Eagle Design Automation, Inc. Système et méthode pour la simulation de systèmes d'ordinateur combinant une interaction entre matériel et logiciel
EP0838772A2 (fr) * 1996-10-17 1998-04-29 Quickturn Design Systems, Inc. Procédé et dispositif pour la vérification d'une conception en utilisant émulation et simulation

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO0057273A1 *

Also Published As

Publication number Publication date
AU3333600A (en) 2000-10-09
JP3504572B2 (ja) 2004-03-08
JP2000298596A (ja) 2000-10-24
KR20000060737A (ko) 2000-10-16
KR100306596B1 (ko) 2001-09-29
WO2000057273A1 (fr) 2000-09-28

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