EP1074052A1 - Lateral high-voltage sidewall transistor - Google Patents

Lateral high-voltage sidewall transistor

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Publication number
EP1074052A1
EP1074052A1 EP99916792A EP99916792A EP1074052A1 EP 1074052 A1 EP1074052 A1 EP 1074052A1 EP 99916792 A EP99916792 A EP 99916792A EP 99916792 A EP99916792 A EP 99916792A EP 1074052 A1 EP1074052 A1 EP 1074052A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor
lateral high
type
transistor according
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99916792A
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German (de)
French (fr)
Inventor
Jenö Tihanyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
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Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1074052A1 publication Critical patent/EP1074052A1/en
Withdrawn legal-status Critical Current

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    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Definitions

  • the invention relates to a lateral high-voltage sidewall transistor.
  • the drain drift path consists of an n-type region in which one or more p-type regions are embedded (cf. for example DE 43 09 764 C2).
  • a lateral high-voltage sidewall transistor in which mutually alternating semiconductor layers of one and the other conduction type are provided on a weakly doped semiconductor substrate of the other conduction type, in which a source region of one conduction type and a drain region of one conduction type are also located each extend through the semiconductor layers to the semiconductor substrate, in which a gate electrode made of a gate trench (or trench) filled with a gate insulating layer and conductive material also extends through the semiconductor layers to the semiconductor body and adjoins the source region in Direction is arranged on the drain region, and in which finally a semiconductor region of the other conductivity type is provided at least on one side of the source region and gate trench, which extends to the semiconductor substrate and under the source e area and partially extends under the gate electrode.
  • the more pairs of semiconductor layers with alternating conductivity types are provided, the better the conductivity of this sidewall transistor.
  • the one line type is preferably the n line type, so that the other line type is given by the p line type and the semiconductor substrate is therefore p ⁇ -doped.
  • inventive semiconductor layers are first to an example, p "-doped semiconductor substrate over the entire surface with alternately opposite conductivity type. This may in a preferred manner by a plurality of epitaxially diagram deposits occur and subsequent ion implantations.
  • SOI silicon on insulator
  • it is also possible, with Using the SOI technology (SOI silicon on insulator) to use an oxidized silicon wafer as a semiconductor substrate, onto which the semiconductor layers alternating in the line type can then be applied using the direct wafer bonding technology Cut technology with subsequent epitaxial deposition are used, in which thin layers are transferred from a first semiconductor wafer by direct bonding to a second semiconductor wafer.
  • the areal density of the n-doping, for example phosphorus, and the p-doping, for example boron, in the semiconductor layers should not exceed about 10 12 cm “2 when silicon is used as the semiconductor material, ie it should not be above the" breakdown concentration " If silicon carbide (SiC) is used as the semiconductor material, an areal density of the n-doping or the p-doping in the semiconductor layers of about 10 13 cm -2 should be aimed for, which should not be exceeded.
  • SiC silicon carbide
  • a structure is therefore first produced in which n-doped and p-doped semiconductor layers are applied in succession to a weakly p -- doped semiconductor body, which have a surface density of the dopings of the order of 10 12 cm -2 for silicon and 10 13 cm Do not exceed -2 for silicon carbide.
  • Trenches (trenches) for the source and drain areas and for the "body” area are introduced into the structures produced in this way.
  • An n-dopant for example phosphorus or arsenic, is then diffused into the surrounding semiconductor material from the walls of the trenches for the source region and drain region.
  • p-dopant for example boron
  • the respective trenches for source, drain and body can be filled with doped polycrystalline silicon in order to form leads to the individual levels of the semiconductor layers.
  • These supply lines can be separated from one another by an insulating layer made of silicon dioxide, for example. If necessary, it is also possible to reinforce the polycrystalline silicon with a conductive material.
  • the gate trenches are introduced and covered with an insulating layer made of, for example, silicon dioxide.
  • the gate trenches are then filled with n + -conducting polycrystalline silicon.
  • n-type semiconductor layers are thus in contact along the drift path through the source region and drain region. tated, ie connected via the respective trenches for the source electrode and the gate electrode.
  • the p-type semiconductor layers of the drift path are connected through the p-type semiconductor region or the body trench.
  • the position of the source region and the p-type semiconductor region indicated above means that the source regions are interrupted by the p-type semiconductor region and a channel zone is formed in which the current along the trench wall of the gate trench positive gate-source voltage can flow.
  • the lateral high-voltage sidewall transistor according to the invention can optionally also be equipped with a field plate which has an increasing distance from the semiconductor layers continuously or stepwise in the direction from source to drain and is embedded in an insulating layer which consists, for example, of silicon dioxide or silicon nitride.
  • the drain region is expediently enclosed at a distance from the drift path from the source region. This does not apply to a design of the lateral high-voltage sidewall transistor using the SOI technology already mentioned.
  • the source area and drain area are preferably arranged parallel to one another.
  • the trenches are then etched through the entire epitaxial area down to the insulating oxide.
  • the n-doping should predominate in the drift path, so that preferably in addition to respective pairs of semiconductor layers with alternating conductivity types, another n-type layer with a surface doping in the range of 10 12 cm "2 without associated p-type Layer is present.
  • the one line type is the n line type and the other line type is the p line type
  • the reverse line types can also be provided if necessary.
  • FIG. 1 shows a sectional illustration with the output material for producing the lateral high-voltage sidewall transistor according to the invention
  • Fig. 2 is a sectional view of the finished lateral high-voltage side wall transistor
  • FIG. 3 shows a section b-b through FIG. 2, which in turn represents a section a-a of FIG. 2, FIG. 3 having a different scale than FIG. 2.
  • FIGS. 1 and 2 show sectional representations, not all cut surfaces are shown hatched for better clarity.
  • FIG. 1 shows a p " -conducting semiconductor substrate 1 made of silicon, on which a low-doped epitaxial zone 2 is applied. P-doped layers 3 and n-doped layers 4 are introduced into this epitaxial zone 2, so that in the present exemplary embodiment as a whole there are three pairs of layers 5.
  • an additional n-type layer 4 is also present on the surface of the p " -type semiconductor substrate 1.
  • the individual layers 3, 4 are preferably produced by several epitaxial depositions and ion implantations.
  • the dopant also diffuses from the implanted layers 3, 4 into the regions of the adjoining low-doped epizone 2, so that overall a layer sequence of alternating n-type layers and p-type layers is present on the p " -doped semiconductor substrate 1 , in which the n-doping predominates, since in addition to the layer pairs 5 there is still the additional n-conducting layer on the surface of the p " -containing semiconductor substrate 1.
  • the surface density of the doping in the n-type layers 4 and in the p-type layers 3 is below the breakdown concentration, that is to say approximately 10 12 cm “2 for silicon (and 10 13 cm “ 2 for silicon carbide).
  • a trench 6 for a drain region, trenches 7 for source regions and trenches 8 for body regions are then introduced into the starting material shown in FIG. 1 (cf. in particular FIG. 3).
  • the drain region 9 and the source regions 10 with n-type dopant, for example phosphorus, are then diffused out of the trench walls.
  • p-type dopant is diffused from the body trench 8, so that p-type semiconductor regions 11 are formed.
  • the gate trench is produced, the wall of which is covered with insulating material 12 made of, for example, silicon dioxide and / or silicon nitride .
  • the trenches 6, 7 and 8 for the drain region 9 or the source regions 10 or the semiconductor region 11 are as filled with doped polycrystalline silicon or with metallizations 13, which connect the drain region 9 to a drain electrode D and the source region 10 to a source electrode S.
  • the gate trench is filled with n + -conducting polycrystalline silicon 14, which is likewise connected to a metallization 13 for a gate electrode G.
  • the n-type layers 4 are thus contacted in the drift path through the source electrode S via the source regions 10, and the p-type layers 3 are not shown in the figures via the semiconductor regions 11 or their metallization introduced into the trench 8 ) contacted.
  • the semiconductor regions 8 with the p-doping are designed between the source regions 10 in such a way that their n-doping is interrupted in the gate region and a channel zone is formed in which current runs along the trench wall of the gate trench with a positive gate-source Tension can flow.
  • the lateral high-voltage side wall transistor according to the invention can also be equipped with a field plate 15, which is arranged such that its distance from the layers 3, 4 becomes larger as the drain electrode D is approached.
  • This field plate 15 is embedded in an insulating layer 16 made of silicon dioxide.
  • the field plate 15 can rise steadily in the direction of the drain (as shown in FIG. 2) or also gradually.
  • the drain electrode D is expediently enclosed by source. If such a field plate 15 is provided, the n-doping should predominate in the drift path, which is why - as was explained at the beginning - an additional n-conducting layer 4 is provided on the surface of the semiconductor substrate 1 in addition to the pairs 5.

Abstract

The invention relates to a lateral high-voltage sidewall transistor, wherein successively alternating semiconductor layers (4, 3) having a first and a second type of conductivity are provided on a slightly doped semiconductor substrate (1) having a second type of conductivity. A source area (10) having a first type of conductivity and a drain area (9) having a first type of conductivity extend through the semiconductor layers (4, 3) to the semiconductor substrate. The same applies to a gate (G) consisting of a gate trench fitted with a gate insulation layer (12) and filled with conductive material (14), which also extends through the semiconductor layers (4, 3) to the semiconductor body (1) and is located in the boundary area with the source area (10) in the direction of the drain area (9). At least a semiconductor area (11) having a second type of conductivity is provided on one side of the source area (10) and the gate trench, said area extending to the semiconductor substrate (1), below the source area (10) and partially below the gate trench.

Description

Beschreibungdescription
Lateraler Hochvolt-SeitenwandtransistorLateral high-voltage sidewall transistor
Die Erfindung betrifft einen lateralen Hochvolt-Seitenwandtransistor. Es gibt bereits laterale Hochvolttransistoren, bei denen die Drain-Driftstrecke aus einem n-leitenden Bereich besteht, in den ein oder mehrere p-leitende Gebiete eingebettet sind (vgl. beispielsweise DE 43 09 764 C2) .The invention relates to a lateral high-voltage sidewall transistor. There are already lateral high-voltage transistors in which the drain drift path consists of an n-type region in which one or more p-type regions are embedded (cf. for example DE 43 09 764 C2).
Es ist Aufgabe der vorliegenden Erfindung, einen lateralen Hochvolt-Seitenwandtransistor zu schaffen, der sich bei guter Leitfähigkeit durch eine hohe Spannungsfestigkeit auszeichnet und mit einfachen Mitteln herstellbar ist.It is an object of the present invention to provide a lateral high-voltage sidewall transistor which, with good conductivity, is distinguished by a high dielectric strength and can be produced using simple means.
Zur Lösung dieser Aufgabe ist erfindungsgemäß ein lateraler Hochvolt-Seitenwandtransistor vorgesehen, bei dem einander abwechselnde Halbleiterschichten des einen und des anderen Leitungstyps auf einem schwach dotierten Halbleitersubstrat des anderen Leitungstyps vorgesehen sind, bei dem weiterhin ein Sourcebereich des einen Leitungstyps und ein Drainbereich des einen Leitungstyps sich jeweils durch die Halbleiterschichten hindurch bis zu dem Halbleitersubstrat erstrecken, bei dem eine Gateelektrode aus einem mit einer Gateisolierschicht versehenen und leitendem Material gefüllten Gate- Trench (bzw. -Graben) sich ebenfalls durch die Halbleiterschichten hindurch bis zum Halbleiterkörper erstreckt und angrenzend an den Sourcebereich in Richtung auf den Drainbe- reich angeordnet ist, und bei dem schließlich wenigstens auf einer Seite von Sourcebereich und Gate-Trench ein Halbleiterbereich des anderen Leitungstyps vorgesehen ist, der sich bis zum Halbleitersubstrat und unter dem Sourcebereich sowie teilweise unter die Gateelektrode erstreckt. Je mehr Paare der Halbleiterschichten mit abwechselndem Leitungstyp vorgesehen sind, um so besser wird die Leitfähigkeit dieses Seitenwandtransistors.To achieve this object, a lateral high-voltage sidewall transistor is provided according to the invention, in which mutually alternating semiconductor layers of one and the other conduction type are provided on a weakly doped semiconductor substrate of the other conduction type, in which a source region of one conduction type and a drain region of one conduction type are also located each extend through the semiconductor layers to the semiconductor substrate, in which a gate electrode made of a gate trench (or trench) filled with a gate insulating layer and conductive material also extends through the semiconductor layers to the semiconductor body and adjoins the source region in Direction is arranged on the drain region, and in which finally a semiconductor region of the other conductivity type is provided at least on one side of the source region and gate trench, which extends to the semiconductor substrate and under the source e area and partially extends under the gate electrode. The more pairs of semiconductor layers with alternating conductivity types are provided, the better the conductivity of this sidewall transistor.
Bei dem einen Leitungstyp handelt es sich in bevorzugter Weise um den n-Leitungstyp, so daß der andere Leitungstyp durch den p-Leitungstyp gegeben ist und das Halbleitersubstrat also p~-dotiert ist.The one line type is preferably the n line type, so that the other line type is given by the p line type and the semiconductor substrate is therefore p ~ -doped.
Bei der Herstellung des erfindungsgemäßen lateralen Hochvolt- Seitenwandtransistors werden zunächst auf ein beispielsweise p"-dotiertes Halbleitersubstrat ganzflächig Halbleiterschichten mit abwechselnd entgegengesetztem Leitungstyp aufgebracht. Dies kann in bevorzugter Weise durch mehrere epitak- tische Abscheidungen und anschließende Ionenimplantationen geschehen. Jedoch ist es auch möglich, mit Hilfe der SOI- Technik (SOI = Silizium auf Isolator) als Halbleitersubstrat eine oxidierte Siliziumscheibe heranzuziehen, auf die dann mit Hilfe der Direkt-Wafer-Bond-Technik die einander im Lei- tungstyp abwechselnden Halbleiterschichten aufgetragen werden. Gegebenenfalls kann hierfür auch die sogenannte Smart Cut Technik mit anschließender epitaktischer Abscheidung angewandt werden, bei der dünne Schichten von einer ersten Halbleiterscheibe durch Direkt-Bonden auf eine zweite Halb- leiterscheibe übertragen werden.In the preparation of the lateral high-voltage side wall transistor inventive semiconductor layers are first to an example, p "-doped semiconductor substrate over the entire surface with alternately opposite conductivity type. This may in a preferred manner by a plurality of epitaxially diagram deposits occur and subsequent ion implantations. However, it is also possible, with Using the SOI technology (SOI = silicon on insulator) to use an oxidized silicon wafer as a semiconductor substrate, onto which the semiconductor layers alternating in the line type can then be applied using the direct wafer bonding technology Cut technology with subsequent epitaxial deposition are used, in which thin layers are transferred from a first semiconductor wafer by direct bonding to a second semiconductor wafer.
Die Flächendichte der n-Dotierung, beispielsweise Phosphor, und der p-Dotierung, beispielsweise Bor, in den Halbleiterschichten soll bei Verwendung von Silizium als Halbleiterma- terial etwa 1012 cm"2 nicht überschreiten, also nicht über der "Durchbruchskonzentration" liegen. Wird Siliziumcarbid (SiC) als Halbleitermaterial verwendet, so ist eine Flächendichte der n-Dotierung bzw. der p-Dotierung in den Halbleiterschichten von etwa 1013 cm-2 anzustreben, welche aber nicht über- schritten werden sollte. Es wird also zunächst eine Struktur hergestellt, bei der auf einem schwach p~-dotierten Halbleiterkörper nacheinander n- dotierte und p-dotierte Halbleiterschichten aufgetragen sind, die eine Flächendichte der Dotierungen in der Größenordnung von 1012 cm-2 für Silizium und 1013 cm-2 für Siliziumcarbid nicht überschreiten.The areal density of the n-doping, for example phosphorus, and the p-doping, for example boron, in the semiconductor layers should not exceed about 10 12 cm "2 when silicon is used as the semiconductor material, ie it should not be above the" breakdown concentration " If silicon carbide (SiC) is used as the semiconductor material, an areal density of the n-doping or the p-doping in the semiconductor layers of about 10 13 cm -2 should be aimed for, which should not be exceeded. A structure is therefore first produced in which n-doped and p-doped semiconductor layers are applied in succession to a weakly p -- doped semiconductor body, which have a surface density of the dopings of the order of 10 12 cm -2 for silicon and 10 13 cm Do not exceed -2 for silicon carbide.
In die so hergestellten Strukturen werden Trenche (Gräben) für die Source- und Drainbereiche sowie für den "Body"-Be- reich eingebracht. Aus den Wänden der Trenche für Sourcebereich und Drainbereich wird sodann in das umgebende Halbleitermaterial ein n-Dotierungsstoff, beispielsweise Phosphor oder Arsen, eindiffundiert. In ähnlicher Weise wird aus den Wänden des Body-Trenchs p-Dotierungsstoff, also beispielsweise Bor, zur Diffusion in das umgebende Halbleitermaterial gebracht. Nach dieser Diffusion können die jeweiligen Trenche für Source, Drain und Body mit dotiertem polykristallinem Silizium aufgefüllt werden, um so Zuleitungen zu den einzelnen Ebenen der Halbleiterschichten zu bilden. Diese Zuleitungen können voneinander durch eine Isolierschicht aus beispielsweise Siliziumdioxid getrennt werden. Gegebenenfalls ist es auch möglich, das polykristalline Silizium noch mit einem leitfähigen Material zu verstärken.Trenches (trenches) for the source and drain areas and for the "body" area are introduced into the structures produced in this way. An n-dopant, for example phosphorus or arsenic, is then diffused into the surrounding semiconductor material from the walls of the trenches for the source region and drain region. In a similar manner, p-dopant, for example boron, is brought from the walls of the body trench for diffusion into the surrounding semiconductor material. After this diffusion, the respective trenches for source, drain and body can be filled with doped polycrystalline silicon in order to form leads to the individual levels of the semiconductor layers. These supply lines can be separated from one another by an insulating layer made of silicon dioxide, for example. If necessary, it is also possible to reinforce the polycrystalline silicon with a conductive material.
Nach der in der obigen Weise vorgenommenen Herstellung des Sourcebereiches, des Drainbereiches und des p-leitenden Halbleiterbereiches durch Diffusion aus den jeweiligen Trenchen werden die Gate-Trenches eingebracht und mit einer Isolier- schicht aus beispielsweise Siliziumdioxid belegt. Sodann werden die Gate-Trenches mit n+-leitendem polykristallinem Silizium aufgefüllt.After the source region, the drain region and the p-type semiconductor region have been produced in the above manner by diffusion from the respective trenches, the gate trenches are introduced and covered with an insulating layer made of, for example, silicon dioxide. The gate trenches are then filled with n + -conducting polycrystalline silicon.
Damit sind die n-leitenden Halbleiterschichten entlang der Driftstrecke durch Sourcebereich und Drainbereich kontak- tiert, also über die jeweiligen Trenche für die Sourceelek- trode und die Gateelektrode angeschlossen. In ähnlicher Weise sind die p-leitenden Halbleiterschichten der Driftstrecke durch den p-leitenden Halbleiterbereich bzw. den Body-Trench angeschlossen.The n-type semiconductor layers are thus in contact along the drift path through the source region and drain region. tated, ie connected via the respective trenches for the source electrode and the gate electrode. In a similar way, the p-type semiconductor layers of the drift path are connected through the p-type semiconductor region or the body trench.
Durch die oben angegebene Lage von Sourcebereich und p-lei- tendem Halbleiterbereich wird erreicht, daß die Sourceberei- che durch den p-leitenden Halbleiterbereich unterbrochen sind und eine Kanalzone entsteht, in der der Strom an der Trench- wand des Gate-Trenches entlang bei positiver Gate-Source- Spannung fließen kann.The position of the source region and the p-type semiconductor region indicated above means that the source regions are interrupted by the p-type semiconductor region and a channel zone is formed in which the current along the trench wall of the gate trench positive gate-source voltage can flow.
Der erfindungsgemäße laterale Hochvolt-Seitenwandtransistor kann gegebenenfalls auch mit einer Feldplatte ausgerüstet werden, die stetig oder stufenweise in Richtung von Source zu Drain einen steigenden Abstand zu den Halbleiterschichten hat und in einer Isolierschicht eingebettet ist, die beispielsweise aus Siliziumdioxid oder Siliziumnitrid besteht.The lateral high-voltage sidewall transistor according to the invention can optionally also be equipped with a field plate which has an increasing distance from the semiconductor layers continuously or stepwise in the direction from source to drain and is embedded in an insulating layer which consists, for example, of silicon dioxide or silicon nitride.
Der Drainbereich ist zweckmäßigerweise im Abstand der Driftstrecke von dem Sourcebereich umschlossen. Dies gilt nicht für eine Ausführung des lateralen Hochvolt-Seitenwandtran- sistors in der bereits erwähnten SOI-Technik. Hier sind Sour- cebereich und Drainbereich vorzugsweise parallel zueinander angeordnet. Die Trenche sind dann bis zum Isolieroxid durch den gesamten epitaktischen Bereich hindurch geätzt.The drain region is expediently enclosed at a distance from the drift path from the source region. This does not apply to a design of the lateral high-voltage sidewall transistor using the SOI technology already mentioned. Here, the source area and drain area are preferably arranged parallel to one another. The trenches are then etched through the entire epitaxial area down to the insulating oxide.
Bei Verwendung einer Feldplatte sollte in der Driftstrecke die n-Dotierung überwiegen, so daß vorzugsweise zusätzlich zu jeweiligen Paaren von Halbleiterschichten mit einander abwechselndem Leitungstyp noch eine weitere n-leitende Schicht mit einer Flächendotierung im Bereich von 1012 cm"2 ohne zugehörige p-leitende Schicht vorhanden ist. Obwohl oben davon ausgegangen wurde, daß der eine Leitungstyp der n-Leitungstyp und der andere Leitungstyp der p-Leitungs- typ ist, können gegebenenfalls auch die umgekehrten Leitungstypen vorgesehen werden.When using a field plate, the n-doping should predominate in the drift path, so that preferably in addition to respective pairs of semiconductor layers with alternating conductivity types, another n-type layer with a surface doping in the range of 10 12 cm "2 without associated p-type Layer is present. Although it was assumed above that the one line type is the n line type and the other line type is the p line type, the reverse line types can also be provided if necessary.
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The invention is explained in more detail below with reference to the drawings. Show it:
Fig. 1 eine Schnittdarstellung mit dem Ausgangsmate- rial zur Herstellung des erfindungsgemäßen lateralen Hochvolt-Seitenwandtransistors,1 shows a sectional illustration with the output material for producing the lateral high-voltage sidewall transistor according to the invention,
Fig. 2 eine Schnittdarstellung des fertigen lateralen Hochvolt-Seitenwandtransistors, undFig. 2 is a sectional view of the finished lateral high-voltage side wall transistor, and
Fig. 3 einen Schnitt b-b durch Fig. 2, die ihrerseits einen Schnitt a-a von Fig. 2 darstellt, wobei Fig. 3 einen anderen Maßstab als Fig. 2 hat.3 shows a section b-b through FIG. 2, which in turn represents a section a-a of FIG. 2, FIG. 3 having a different scale than FIG. 2.
Obwohl die Fig. 1 und 2 Schnittdarstellungen zeigen, sind hier zur besseren Übersichtlichkeit nicht alle geschnittenen Flächen schraffiert dargestellt.Although FIGS. 1 and 2 show sectional representations, not all cut surfaces are shown hatched for better clarity.
Fig. 1 zeigt ein p"-leitendes Halbleitersubstrat 1 aus Silizium, auf dem eine niedrig dotierte epitaktische Zone 2 aufgebracht ist. In diese epitaktische Zone 2 sind p-dotierte Schichten 3 und n-dotierte Schichten 4 eingebracht, so daß im vorliegenden Ausführungsbeispiel insgesamt drei Schichtpaare 5 vorliegen.1 shows a p " -conducting semiconductor substrate 1 made of silicon, on which a low-doped epitaxial zone 2 is applied. P-doped layers 3 and n-doped layers 4 are introduced into this epitaxial zone 2, so that in the present exemplary embodiment as a whole there are three pairs of layers 5.
Außerdem ist auf der Oberfläche des p"-leitenden Halbleitersubstrates 1 noch eine zusätzliche n-leitende Schicht 4 vorhanden. Die einzelnen Schichten 3, 4 werden in bevorzugter Weise durch mehrere epitaktische Abscheidungen und Ionenimplantationen hergestellt. Dabei diffundiert der Dotierstoff aus den implantierten Schichten 3, 4 auch in die Bereiche der angren- zenden niedrig dotierten Epizone 2, so daß insgesamt auf dem p"-dotierten Halbleitersubstrat 1 eine Schichtenfolge von sich abwechselnden n-leitenden Schichten und p-leitenden Schichten vorliegt, in welcher die n-Dotierung überwiegt, da insgesamt zu den Schichtpaaren 5 noch die zusätzliche n-lei- tende Schicht auf der Oberfläche des p"-leitenden Halbleitersubstrates 1 vorhanden ist.In addition, an additional n-type layer 4 is also present on the surface of the p " -type semiconductor substrate 1. The individual layers 3, 4 are preferably produced by several epitaxial depositions and ion implantations. The dopant also diffuses from the implanted layers 3, 4 into the regions of the adjoining low-doped epizone 2, so that overall a layer sequence of alternating n-type layers and p-type layers is present on the p " -doped semiconductor substrate 1 , in which the n-doping predominates, since in addition to the layer pairs 5 there is still the additional n-conducting layer on the surface of the p " -containing semiconductor substrate 1.
Die Flächendichte der Dotierung in den n-leitenden Schichten 4 und in den p-leitenden Schichten 3 liegt unterhalb der Durchbruchkonzentration, also bei etwa 1012 cm"2 für Silizium (und bei 1013 cm"2 für Siliziumcarbid) .The surface density of the doping in the n-type layers 4 and in the p-type layers 3 is below the breakdown concentration, that is to say approximately 10 12 cm "2 for silicon (and 10 13 cm " 2 for silicon carbide).
In das in Fig. 1 gezeigte Ausgangsmaterial werden sodann ein Trench 6 für einen Drainbereich, Trenche 7 für Sourcebereiche und Trenche 8 für Body-Bereiche eingebracht (vgl. insbesondere Fig. 3) . Aus den Trenchwänden heraus werden sodann der Drainbereich 9 und die Sourcebereiche 10 mit n-leitendem Dotierstoff, beispielsweise Phosphor, eindiffundiert. Ebenso wird aus den Body-Trenchen 8 p-leitender Dotierstoff eindif- fundiert, so daß p-leitende Halbleiterbereiche 11 entstehen.A trench 6 for a drain region, trenches 7 for source regions and trenches 8 for body regions are then introduced into the starting material shown in FIG. 1 (cf. in particular FIG. 3). The drain region 9 and the source regions 10 with n-type dopant, for example phosphorus, are then diffused out of the trench walls. Likewise, p-type dopant is diffused from the body trench 8, so that p-type semiconductor regions 11 are formed.
Nach diesen Diffusionen des n-Dotierstoffes für den Drainbereich 9 bzw. die Sourcebereiche 10 und des p-leitenden Dotierstoffes für die Halbleiterbereiche 11 erfolgt die Her- Stellung des Gate-Trenches, dessen Wand mit Isolierstoff 12 aus beispielsweise Siliziumdioxid und/oder Siliziumnitrid belegt wird.After these diffusions of the n-dopant for the drain region 9 or the source regions 10 and the p-conductive dopant for the semiconductor regions 11, the gate trench is produced, the wall of which is covered with insulating material 12 made of, for example, silicon dioxide and / or silicon nitride .
Die Trenche 6, 7 und 8 für den Drainbereich 9 bzw. die Sour- cebereiche 10 bzw. den Halbleiterbereich 11 werden beispiels- weise mit dotiertem polykristallinem Silizium oder mit Metallisierungen 13 gefüllt, die den Drainbereich 9 an eine Drainelektrode D und den Sourcebereich 10 an eine Sourceelektrode S anschließen. Der Gate-Trench wird mit n+-leitendem polykri- stallinem Silizium 14 gefüllt, das ebenfalls an eine Metallisierung 13 für eine Gateelektrode G angeschlossen ist.The trenches 6, 7 and 8 for the drain region 9 or the source regions 10 or the semiconductor region 11 are as filled with doped polycrystalline silicon or with metallizations 13, which connect the drain region 9 to a drain electrode D and the source region 10 to a source electrode S. The gate trench is filled with n + -conducting polycrystalline silicon 14, which is likewise connected to a metallization 13 for a gate electrode G.
Damit sind die n-leitenden Schichten 4 in der Driftstrecke durch die Sourceelektrode S über die Sourcebereiche 10 kon- taktiert, und die p-leitenden Schichten 3 sind über die Halbleiterbereiche 11 bzw. deren in die Trenche 8 eingebrachten Metallisierung (in den Figuren nicht gezeigt) kontaktiert. Die Halbleiterbereiche 8 mit der p-Dotierung sind dabei zwischen den Sourcebereichen 10 so gestaltet, daß deren n-Dotie- rung im Gatebereich unterbrochen ist und eine Kanalzone entsteht, in der Strom an der Trenchwand des Gate-Trenches entlang bei positiver Gate-Source-Spannung fließen kann.The n-type layers 4 are thus contacted in the drift path through the source electrode S via the source regions 10, and the p-type layers 3 are not shown in the figures via the semiconductor regions 11 or their metallization introduced into the trench 8 ) contacted. The semiconductor regions 8 with the p-doping are designed between the source regions 10 in such a way that their n-doping is interrupted in the gate region and a channel zone is formed in which current runs along the trench wall of the gate trench with a positive gate-source Tension can flow.
Der erfindungsgemäße laterale Hochvolt-Seitenwandtransistor kann noch mit einer Feldplatte 15 ausgerüstet werden, die so angeordnet ist, daß deren Abstand von den Schichten 3, 4 bei Annäherung an die Drainelektrode D immer größer wird. Diese Feldplatte 15 ist in eine Isolierschicht 16 aus Siliziumdioxid eingebettet. Die Feldplatte 15 kann dabei in Richtung auf Drain stetig (wie in Fig. 2 gezeigt) oder auch stufenweise ansteigen. Zweckmäßigerweise ist die Drainelektrode D von Source umschlossen. Wird eine solche Feldplatte 15 vorgesehen, sollte die n-Dotierung in der Driftstrecke überwiegen, weshalb - wie eingangs erläutert wurde - eine zusätzliche n- leitende Schicht 4 auf der Oberfläche des Halbleitersubstrates 1 in Ergänzung zu den Paaren 5 vorgesehen ist. The lateral high-voltage side wall transistor according to the invention can also be equipped with a field plate 15, which is arranged such that its distance from the layers 3, 4 becomes larger as the drain electrode D is approached. This field plate 15 is embedded in an insulating layer 16 made of silicon dioxide. The field plate 15 can rise steadily in the direction of the drain (as shown in FIG. 2) or also gradually. The drain electrode D is expediently enclosed by source. If such a field plate 15 is provided, the n-doping should predominate in the drift path, which is why - as was explained at the beginning - an additional n-conducting layer 4 is provided on the surface of the semiconductor substrate 1 in addition to the pairs 5.

Claims

Patentansprüche claims
1. Lateraler Hochvolt-Seitenwandtransistor, bei dem einander abwechselnde Halbleiterschichten (4, 3) des einen und des anderen Leitungstyps auf einem schwach dotierten Halbleitersubstrat (1) des anderen Leitungstyps vorgesehen sind, bei dem weiterhin ein Sourcebereich (10) des einen Leitungstyps und ein Drainbereich (9) des einen Leitungstyps sich jeweils durch die Halbleiterschichten (4, 3) hin- durch bis zu dem Halbleitersubstrat (1) erstrecken, bei dem eine Gateelektrode (G) aus einem mit einer Isolierschicht (12) versehenen und leitendem Material (14) gefüllten Gate-Trench sich ebenfalls durch die Halbleiterschichten (4, 3) hindurch bis zum Halbleiterkörper (1) erstreckt und angrenzend an den Sourcebereich (10) in1. Lateral high-voltage sidewall transistor, in which mutually alternating semiconductor layers (4, 3) of one and the other conductivity type are provided on a weakly doped semiconductor substrate (1) of the other conductivity type, in which a source region (10) of one conductivity type and a The drain region (9) of the one conductivity type extends in each case through the semiconductor layers (4, 3) to the semiconductor substrate (1), in which a gate electrode (G) is made of a conductive material (14) provided with an insulating layer (12) ) filled gate trench also extends through the semiconductor layers (4, 3) to the semiconductor body (1) and adjoins the source region (10) in
Richtung auf den Drainbereich (9) angeordnet ist, und bei dem wenigstens auf einer Seite von Sourcebereich (10) und Gate-Trench ein Halbleiterbereich (11) des anderen Leitungstyps vorgesehen ist, der sich bis zum Halbleiter- substrat (1) und unter den Sourcebereich (10) sowie teilweise unter die Gate-Isolierschicht (12) erstreckt.Direction towards the drain region (9) is arranged, and in which at least on one side of the source region (10) and gate trench a semiconductor region (11) of the other conduction type is provided, which extends up to the semiconductor substrate (1) and under the Source region (10) and partially extends under the gate insulating layer (12).
2. Lateraler Hochvolt-Seitenwandtransistor nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß der eine Typ der n-Leitungstyp und der andere Leitungstyp der p-Leitungstyp ist.2. Lateral high-voltage sidewall transistor according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the one type is the n-line type and the other line type of the p-line type.
3. Lateraler Hochvolt-Seitenwandtransistor nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß die Flächendotierung der Halbleiterschichten (4, 3) kleiner als 1012 cm"2 ist.3. Lateral high-voltage side wall transistor according to claim 1 or 2, characterized in that the area doping of the semiconductor layers (4, 3) is less than 10 12 cm "2 .
4. Lateraler Hochvolt-Seitenwandtransistor nach einem der Ansprüche 1 bis 3, d a d u r c h g e k e n n z e i c h n e t , daß der Sourcebereich (10) und der Drainbereich (9) sowie der Halbleiterbereich (11) des anderen Leitungstyps durch Diffusion aus jeweiligen Trenchwänden erzeugt sind.4. Lateral high-voltage sidewall transistor according to one of claims 1 to 3, characterized in that the source region (10) and the drain region (9) and the semiconductor region (11) of the other conduction type are produced by diffusion from respective trench walls.
5. Lateraler Hochvolt-Seitenwandtransistor nach einem der Ansprüche 1 bis 4, d a d u r c h g e k e n n z e i c h n e t , daß die Sourcebereiche (10) durch die Halbleiterbereiche (11) des anderen Leitungstyps voneinander getrennt sind.5. Lateral high-voltage sidewall transistor according to one of claims 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the source regions (10) are separated from one another by the semiconductor regions (11) of the other conductivity type.
6. Lateraler Hochvolt-Seitenwandtransistor nach einem der Ansprüche 1 bis 5, g e k e n n z e i c h n e t d u r c h eine Feldplatte (15) mit in Richtung auf den Drainbereich (9) steigendem Abstand von den Halbleiterschichten (4, 3) .6. Lateral high-voltage sidewall transistor according to one of claims 1 to 5, g e k e n n z e i c h n e t d u r c h a field plate (15) with increasing in the direction of the drain region (9) distance from the semiconductor layers (4, 3).
7. Lateraler Hochvolt-Seitenwandtransistor nach den Ansprü- chen 2 und 6, d a d u r c h g e k e n n z e i c h n e t , daß in den Halbleiterschichten (4, 3) die n-Dotierung überwiegt.7. Lateral high-voltage sidewall transistor according to claims 2 and 6, so that the n-doping predominates in the semiconductor layers (4, 3).
8. Lateraler Hochvolt-Seitenwandtransistor nach einem der Ansprüche 1 bis 7, d a d u r c h g e k e n n z e i c h n e t , daß die Halbleiterschichten (4, 3) durch Epitaxie und Ionenimplantation hergestellt sind.8. Lateral high-voltage sidewall transistor according to one of claims 1 to 7, d a d u r c h g e k e n n z e i c h n e t that the semiconductor layers (4, 3) are produced by epitaxy and ion implantation.
9. Lateraler Hochvolt-Seitenwandtransistor nach einem der Ansprüche 1 bis 7, d a d u r c h g e k e n n z e i c h n e t , daß die Halbleiterschichten durch Wafer-Bonden mittels einer oxidierten Silizium-Scheibe hergestellt sind. 109. Lateral high-voltage sidewall transistor according to one of claims 1 to 7, characterized in that the semiconductor layers are produced by wafer bonding by means of an oxidized silicon wafer. 10
10. Lateraler Hochvolt-Seitenwandtransistor nach Anspruch 8, d a d u r c h g e k e n n z e i c h n e t , dadurch gekennzeichnet, daß der Drainbereich (9) von dem Sourcebereich (10) umschlossen ist.10. Lateral high-voltage sidewall transistor according to claim 8, d a d u r c h g e k e n n z e i c h n e t, characterized in that the drain region (9) is enclosed by the source region (10).
11. Lateraler Hochvolt-Seitenwandtransistor nach Anspruch 9, d a d u r c h g e k e n n z e i c h n e t , daß der Drainbereich (9) und der Sourcebereich (10) im wesentlichen parallel zueinander angeordnet sind. 11. Lateral high-voltage sidewall transistor according to claim 9, d a d u r c h g e k e n e z e i c h n e t that the drain region (9) and the source region (10) are arranged substantially parallel to each other.
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