DE19604043C2 - Semiconductor component controllable by field effect - Google Patents

Semiconductor component controllable by field effect

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Publication number
DE19604043C2
DE19604043C2 DE19604043A DE19604043A DE19604043C2 DE 19604043 C2 DE19604043 C2 DE 19604043C2 DE 19604043 A DE19604043 A DE 19604043A DE 19604043 A DE19604043 A DE 19604043A DE 19604043 C2 DE19604043 C2 DE 19604043C2
Authority
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Germany
Prior art keywords
field effect
controllable
areas
drain zone
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE19604043A
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German (de)
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DE19604043A1 (en
Inventor
Jenoe Tihanyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
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Publication date
Priority to DE19604043A priority Critical patent/DE19604043C2/en
Application filed by Siemens AG filed Critical Siemens AG
Priority to EP00112818A priority patent/EP1039548B1/en
Priority to JP52803997A priority patent/JP4047384B2/en
Priority to PCT/DE1997/000182 priority patent/WO1997029518A1/en
Priority to DE59711481T priority patent/DE59711481D1/en
Priority to EP97907035A priority patent/EP0879481B1/en
Priority to EP03026265.3A priority patent/EP1408554B1/en
Priority to US09/117,636 priority patent/US6184555B1/en
Priority to DE59707158T priority patent/DE59707158D1/en
Publication of DE19604043A1 publication Critical patent/DE19604043A1/en
Application granted granted Critical
Publication of DE19604043C2 publication Critical patent/DE19604043C2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

Die Erfindung betrifft ein durch Feldeffekt steuerbares Halb­ leiterbauelement gemäß dem Oberbegriff des Anspruchs 1.The invention relates to a field controllable half Head component according to the preamble of claim 1.

Derartige durch Feldeffekt steuerbare Halbleiterbauelemente sind z. B. MOS-Feldeffekttransistoren. Diese Transistoren sind seit langem bekannt und z. B. im Siemens Datenbuch 1993/94 SIPMOS-Halbleiter, Leistungstransistoren und Dioden, auf Sei­ te 29ff beschrieben. Fig. 4 auf Seite 30 dieses Datenbuchs zeigt den prinzipiellen Aufbau eines derartigen Lei­ stungstransistors. Der dort gezeigte Transistor stellt einen vertikalen n-Kanal-SIPMOS-Transistor dar. Bei einem derarti­ gen Transistor dient das n+-Substrat als Träger mit der dar­ unterliegenden Drainmetallisierung. Über dem n+-Substrat schließt sich eine n--Epitaxieschicht an, die je nach Sperr­ spannung verschieden dick und entsprechend dotiert ist. Das darüberliegende Gate aus n+-Polysilizium ist in isolierendes Siliziumdioxid eingebettet und dient als Implantationsmaske für die p-Wanne und für die n+-Sourcezone. Die Sourcemetalli­ sierung überdeckt die gesamte Struktur und schaltet die ein­ zelnen Transistorzellen des Chips parallel. Weitere Einzel­ heiten dieses vertikal aufgebauten Leistungstransistors sind auf Seite 30ff des Datenbuchs zu entnehmen.Such controllable by field effect semiconductor devices are such. B. MOS field effect transistors. These transistors have been known for a long time and z. As the Siemens Data Book 1993/94 SIPMOS semiconductors, power transistors and diodes to Be te 29 et seq. Fig. 4 on page 30 of this data book shows the basic structure of such a power transistor. The transistor shown there represents a vertical n-channel SIPMOS transistor. In such a transistor, the n + substrate serves as a carrier with the underlying drain metallization. Above the n + substrate is an n - epitaxial layer, which, depending on the blocking voltage, has different thicknesses and is appropriately doped. The overlying gate made of n + polysilicon is embedded in insulating silicon dioxide and serves as an implantation mask for the p-well and for the n + source zone. The source metalization covers the entire structure and switches the individual transistor cells of the chip in parallel. Further details of this vertically constructed power transistor can be found on page 30ff of the data book.

Nachteil einer derartigen Anordnung ist, daß der Durchlaßwi­ derstand Ron der Drain-Source-Laststrecke mit zunehmender Spannungsfestigkeit des Halbleiterbauelements zunimmt, da die Dicke der Epitaxieschicht zunehmen muß. Bei 50 V liegt der flächenbezogene Durchlaßwiderstand Ron bei ungefähr 0,20 Ohm/m2 und steigt bei einer Sperrspannung von 1000 V bei­ spielsweise auf einen Wert von ca. 10 Ohm/m2 an.A disadvantage of such an arrangement is that the transmission resistance R on of the drain-source load path increases with increasing dielectric strength of the semiconductor component, since the thickness of the epitaxial layer must increase. At 50 V, the area-related forward resistance R on is approximately 0.20 ohm / m 2 and increases at a reverse voltage of 1000 V, for example, to a value of approximately 10 ohm / m 2 .

Aus der US 5,216,275 ist ein Halbleiterbauelement bekannt, bei dem die auf dem Substrat aufgebrachte Drainschicht aus vertikalen abwechselnd p- und n-dotierten Schichten besteht. Die US 5,216,275 zeigt diese Schichten beispielsweise in Fig. 4 der Beschreibung. Die p-Schichten sind mit 7 und die n- Schicht mit 6 bezeichnet. Aus der Beschreibung, insbesondere aus Spalte 2, Zeile 8 geht hervor das die abwechselnden p- und n-Schichten jeweils mit der p-Region 8 bzw. der n-Region 4 verbunden werden müssen. Dies führt jedoch zu einer starker Einschränkung im Design eines Halbleiterbauelementes, da die Randbereiche nicht mehr frei gestaltet werden können.A semiconductor component is known from US Pat. No. 5,216,275, in which the drain layer applied to the substrate consists of vertical, alternately p-doped and n-doped layers. US 5,216,275 shows these layers, for example in Fig. 4 of the description. The p-layers are denoted by 7 and the n-layer by 6. The description, in particular from column 2 , line 8 shows that the alternating p and n layers must be connected to the p region 8 and the n region 4 , respectively. However, this leads to a severe limitation in the design of a semiconductor component, since the edge regions can no longer be designed freely.

Aufgabe der vorliegenden Erfindung ist es, ein durch Feldef­ fekt steuerbares Halbleiterbauelement anzugeben, welches trotz hoher Sperrspannung einen niedrigen Durchlaßwiderstand bereitstellt und die aufgezeigten Nachteile nicht aufweist.The object of the present invention is a by Feldef Specifically controllable semiconductor device to specify which despite the high reverse voltage, a low forward resistance provides and does not have the disadvantages shown.

Diese Aufgabe wird durch ein Halbleiterbauelement nach dem Anspruch 1 gelöst. Weiterbildungen sind Kennzeichen der Un­ teransprüche.This object is achieved by a semiconductor component according to claim 1 solved. Further training is a hallmark of the Un claims.

Die Erfindung weist den Vorteil auf, daß durch einfaches Ein­ bringen von gepaarten n- bzw. p-Bereichen, insbesondere ent­ lang des Strompfads, zum einen durch die n-Schicht eine gute Leitfähigkeit gewährleistet wird und sich zum anderen bei Er­ höhung der Drainspannung die gepaarten Bereiche gegenseitig ausräumen, wodurch eine hohe Sperrspannung gesichert bleibt.The invention has the advantage that by a simple one bring paired n or p areas, especially ent long of the current path, on the one hand a good one due to the n-layer Conductivity is guaranteed and on the other hand at Er increasing the drain voltage, the paired areas mutually clear out, which ensures a high reverse voltage.

Eine besonders vorteilhafte Anordnung ergibt sich bei Verwen­ dung eines Graben(Trench)-Bereiches, dessen Randbereiche der­ artig dotiert werden, daß sich jeweils paarweise n- bzw. p- Bereiche ergeben.A particularly advantageous arrangement results from Verwen of a trench area, the edge areas of which be doped in such a way that n- or p- Areas result.

Ein weiterer Vorteil ergibt sich bei Verwendung von annähernd V-förmigen Isolationsgräben, da die Wände Ionenimplantation mit 0° Einfallswinkel bei gleichzeitig hoher Genauigkeit be­ legt werden können und somit die n- bzw. p-Bereiche in je­ weils einem Arbeitsgang hergestellt werden können. Another advantage arises when using approximately V-shaped isolation trenches because the walls ion implantation with 0 ° angle of incidence and high accuracy at the same time can be placed and thus the n or p ranges in each because it can be produced in one operation.  

Die Erfindung wird nachfolgend anhand der Figuren näher er­ läutert.The invention is based on the figures he he purifies.

Es zeigen:Show it:

Fig. 1 einen Teilschnitt durch einen erfindungsgemäßen ver­ tikalen MOSFET, der, in entsprechend mit A, B, C ge­ kennzeichneten Bereichen, verschiedene Realisierungs­ möglichkeiten aufzeigt, Fig. Possibilities 1 is a partial section through an inventive ver tical MOSFET, ge in accordance with A, B, C marked areas, different realization shows,

Fig. 2a bis 2d zeigen jeweils teilweise Schnitte anhand de­ rer die charakteristischen Verfahrensschritte zur Herstellung eines erfindungsgemäßen vertikalen MOSFET gezeigt werden, FIGS. 2a-2d respectively show partial sections based de rer the characteristic process steps for manufacturing a vertical MOSFET according to the invention are shown,

Fig. 3 zeigt einen Teilschnitt durch einen erfindungsgemäßen vertikalen MOSFET mit einer Grabenstruktur, Fig. 3 shows a partial section through a vertical MOSFET having a grave structure,

Fig. 4 zeigt einen Teilschnitt durch einen weiteren vertika­ len MOSFET mit Grabenstruktur, und Fig. 4 shows a partial section through a further vertical MOSFET with trench structure, and

Fig. 5 zeigt einen Teilschnitt durch einen vertikalen MOSFET mit V-förmiger Grabenstruktur. Fig. 5 shows a partial section through a vertical MOSFET having a V-shaped grave structure.

In Fig. 1 zeigt verschiedene Ausführungsformen einer erfin­ dungsgemäßen Anordnung, die der Übersichtlichkeit wegen in einer Figur dargestellt sind.In Fig. 1 shows various embodiments of an inventive arrangement, which are shown for clarity in a figure.

Diese Fig. 1 stellt einen vertikalen MOSFET dar. Das n+- dotierte Substrat 1 bildet einen Teil der Drainzone und wird rückseitig über eine übliche Metallisierung kontaktiert, die den Drainanschluß D bildet. über dieser Schicht 1 ist eine n- -dotierte Epitaxieschicht 2 abgeschieden, die ebenfalls einen Teil der Drainzone bildet, und in welcher p-dotierte Source­ bereiche 3 eingebracht sind. Diese p-dotierten Sourcebereiche 3 weisen eingebettete n+-Bereiche 4 auf. Die Sourcemetallisierung 5 bildet einen Kurzschluß zwischen diesem n+- und p- Sourcegebiet 3, 4. In der Figur sind mehrere Sourcebereiche 3, 4 dargestellt, die voneinander beabstandet sind und von denen jeweils zwei einen Zwischenbereich in Verbindung mit der Drainzone 1, 2 definieren, über dem, eingebettet in Ga­ teoxid 17, ein Gate 6 angeordnet ist. . This Figure 1 shows a vertical MOSFET is the n + -. Doped substrate 1 forms part of the drain region and is contacted by the rear via a common metallization which forms the drain terminal D. An n - -doped epitaxial layer 2 is deposited over this layer 1 , which likewise forms part of the drain zone and in which p-doped source regions 3 are introduced. These p-doped source regions 3 have embedded n + regions 4 . The source metallization 5 forms a short circuit between this n + and p source region 3 , 4 . In the figure, a plurality of source regions 3 , 4 are shown, which are spaced from one another and two of which each define an intermediate region in connection with the drain zone 1 , 2 , above which a gate 6 is arranged, embedded in gate oxide 17 .

Innerhalb der schwächer dotierten n--Drainzone 2 sind p- und n-dotierte Gebiete 7, 8 bzw. 9, 10 bzw. 11, 12 bzw. 13, 14 eingepflanzt. Diese müssen nicht, können aber einander berüh­ ren und einen pn-Übergang bilden.P- and n-doped regions 7 , 8 and 9 , 10 and 11 , 12 and 13 , 14 are planted within the less heavily doped n - -drain zone 2 . These do not have to, but can touch each other and form a pn junction.

Die p-/n-Gebiete 7, 8 können wie im Bereich A dargestellt ku­ gelförmig ausgebildet sein und sich entlang des Strompfades der Drain-Source-Laststrecke erstrecken. Im Bereich B bilden diese p-/n-Bereiche 10, 11 oder 11, 12 beispielsweise Fä­ den, Streifen oder vertikal verlaufende Ebenen. Diese Berei­ che können, wie durch die Bereiche 9 und 10 angedeutet inner­ halb der Epitaxiechicht 2 "floatend", d. h. frei schwebend, liegen und nur einen Teil der Epitaxiechicht 2 ausfüllen oder, wie durch 11, 12 angedeutet, von der oberen Oberfläche der Epitaxieschicht 2 bis zum Substrat 1 und/oder in das Substrat 1 hineinreichen. Wie im Bereich B gezeigt kann der Abstand d der Schichten 9, 10 bzw. 11, 12 größer gleich 0 sein.The p / n regions 7 , 8 can, as shown in the region A, be of spherical design and extend along the current path of the drain-source load path. In area B, these p / n areas 10 , 11 or 11 , 12 form, for example, threads, strips or vertically extending planes. These areas can, as indicated by the areas 9 and 10 within the epitaxial layer 2 "floating", ie floating, lie and fill only part of the epitaxial layer 2 or, as indicated by 11, 12, from the upper surface of the epitaxial layer 2 extend to substrate 1 and / or into substrate 1 . As shown in area B, the distance d between the layers 9 , 10 and 11 , 12 can be greater than or equal to 0.

Im Bereich C ist eine weitere Ausführungsform dargestellt bei der eine statistische Verteilung der p- und n-dotierten Ge­ biete 13, 14 vorgesehen ist. Dabei kann der Querschnitt die­ ser p-/n-Gebiete 13, 14 sowie auch die Dotierungsverteilung unregelmäßig sein.A further embodiment is shown in area C in which a statistical distribution of the p- and n-doped regions 13 , 14 is provided. The cross section of the water p / n regions 13 , 14 and also the doping distribution can be irregular.

Wesentlich ist, daß die Anzahl der eingebrachten p-Gebiete 7, 10, 12, 13 ungefähr gleich der Anzahl der eingebrachten n- Gebiete 8, 9, 11, 14 ist. Dabei ist des weiteren zu beachten, daß die Summe der Volumenausdehnungen der eingebrachten p- Gebiete 7, 10, 12, 13 ungefähr gleich oder kleiner der der n- Gebiete 8, 9, 11, 14 ist.It is essential that the number of p regions 7 , 10 , 12 , 13 introduced is approximately equal to the number of n regions 8 , 9 , 11 , 14 introduced . It should also be noted that the sum of the volume expansions of the introduced p-regions 7 , 10 , 12 , 13 is approximately equal to or less than that of the n-regions 8 , 9 , 11 , 14 .

Ebenso sollte im Fall der Anordnung gemäß dem Bereich C die durchschnittliche Konzentration der verteilten p-Gebiete in etwa gleich oder größer der der eingebrachten n-Gebiete sein.Likewise, in the case of the arrangement according to area C, the average concentration of the distributed p-areas in be approximately equal to or greater than that of the introduced n regions.

Der Abstand d zwischen den einzelnen p- und n-Gebieten, soll­ te vorzugsweise kleiner als die Breite der Raumladungszone zwischen den p-/n-Gebieten bei der Durchbruchsspannung zwi­ schen den benachbarten p-/n-Gebieten sein, kann aber wie er­ wähnt auch zu null werden.The distance d between the individual p and n areas should te is preferably smaller than the width of the space charge zone between the p / n areas at the breakdown voltage between the neighboring p / n areas, but can be like him also thinks to be zero.

Nachfolgend wird die Funktionsweise einer derartigen erfin­ dungsgemäßen Struktur näher erläutert.In the following, the mode of operation of such a device is invented structure according to the invention explained in more detail.

Bei kleiner Drainspannung ist die Leitfähigkeit gut, da die n-Zone 15, 25 bzw. die durch die n-dotierten Gebiete 8, 9, 11, 14 gebildeten Zonen niederohmig sind. Wird die Drainspan­ nung erhöht, werden bei moderater Spannung, z. B. einer Span­ nung kleiner 30 V, die p- bzw. n-dotierten Schichten 9, 10; 11, 12 bzw. Gebiete 7, 8; 13, 14 gegenseitig ausgeräumt. Bei einer weiteren Spannungserhöhung wird nun die vertikale Feld­ stärke weiter erhöht und die Epitaxieschicht 2 nimmt die Spannung auf.If the drain voltage is low, the conductivity is good since the n-zone 15 , 25 or the zones formed by the n-doped regions 8 , 9 , 11 , 14 have a low resistance. If the drain voltage is increased, at a moderate voltage, e.g. B. a voltage less than 30 V, the p- or n-doped layers 9 , 10 ; 11 , 12 or areas 7 , 8 ; 13 , 14 mutually cleared. With a further increase in voltage, the vertical field strength is now increased further and the epitaxial layer 2 absorbs the voltage.

Im einzelnen erfolgt dieser Vorgang folgendermaßen: Die Aus­ räumung startet von der Oberfläche unter der Gateelektrode 6 und den Sourcebereichen 3, 4. Sie schreitet dann in das Ge­ biet 9, 10; 11, 12 bzw. die Gebiete 7, 8; 13, 14 voran. Wenn die Raumladungszone die ersten p-Gebiete 7, 10, 12, 13 er­ reicht, bleiben diese Gebiete auf der Spannung, die das Po­ tential der Raumladungszone erreicht hat. Dann wird die näch­ ste Umgebung in Richtung des Drainanschlusses D ausgeräumt. Dieser Vorgang wiederholt sich von Schicht zu Schicht. In detail, this process takes place as follows: The evacuation starts from the surface under the gate electrode 6 and the source regions 3 , 4 . She then strides into Ge 9 , 10 ; 11 , 12 or areas 7 , 8 ; 13 , 14 ahead. If the space charge zone reaches the first p regions 7 , 10 , 12 , 13 , these regions remain at the voltage which has reached the potential of the space charge zone. Then the next environment is cleared in the direction of the drain connection D. This process is repeated from layer to layer.

Auf diese Weise schreitet die Raumladungszone voran, bis die Zone unterhalb der eingebrachten Dotierungen innerhalb der Epitaxieschicht 2 erreicht wird. Insgesamt wird dann die Raumladungszone so aufgebaut, als ob die zusätzlich einge­ brachten p-/n-Bereiche 7, 8, 9, 10, 11, 12, 13, 14 nicht vor­ handen wären.In this way, the space charge zone proceeds until the zone below the introduced dopings within the epitaxial layer 2 is reached. Overall, the space charge zone is then constructed as if the additionally introduced p / n regions 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 were not present.

Die Spannungsfestigkeit wird dabei nur durch die Dicke der Epitaxieschicht 2 bestimmt. Somit kann die erfindungsgemäße Anordnung beide Erfordernisse erfüllen, nämlich einen niede­ rohmigen Durchlaßwiderstand Ron bei gleichzeitiger hoher Spannungsfestigkeit.The dielectric strength is only determined by the thickness of the epitaxial layer 2 . Thus, the arrangement according to the invention can meet both requirements, namely a low, raw forward resistance R on with a high dielectric strength.

In einer Abwandlung ist eine derartige Struktur auch als IGBT funktionsfähig, wenn z. B. die untere n+-Zone 1 gemäß Fig. 1 auf p+ umgeschaltet wird.In a modification, such a structure is also functional as an IGBT if, for. B. the lower n + zone 1 according to FIG. 1 is switched to p + .

Die erfindungsgemäßen Strukturen können sowohl bei vertikal als auch bei lateral aufgebauten Halbleiterstrukturen verwen­ det werden. Bei lateralen Strukturen sollten streifenförmig ausgebildete p- und n-Bereiche dann in horizontalen Ebenen ausgerichtet werden. Diese können z. B. als buried layer in die n--Schicht 2 vergraben werden.The structures according to the invention can be used both with vertical and with laterally constructed semiconductor structures. In the case of lateral structures, p-shaped and n-shaped areas should then be aligned in horizontal planes. These can e.g. B. can be buried as buried layer in the n - layer 2 .

Die Fig. 2a bis 2d zeigen ein mögliches Herstellverfahren einer Anordnung gemäß Fig. 3. Auf einem n+-dotierten Substrat 1 wird eine erste dünne n--dotierte Epitaxieschicht 2 aufgewachsen. Diese wird beispielsweise durch entsprechende Maskierung und Ionenimplantation mit sich abwechselnden n- bzw. p-Bereichen 28 und 29 dotiert. Die Dotierung kann selbstverständlich auch durch andere bekannte Verfahren er­ folgen. FIGS. 2a to 2d show a possible production method for an arrangement according to FIG. 3. A first thin n - -doped epitaxial layer 2 is grown on an n + -doped substrate 1 . This is doped, for example, by appropriate masking and ion implantation with alternating n or p regions 28 and 29 . The doping can of course also be followed by other known methods.

Danach wird, wie in Fig. 2b zu sehen ist, eine weitere Epi­ taxieschicht aufgebracht, die in gleicher Weise wie zuvor do­ tiert wird. Then, as can be seen in Fig. 2b, another epi taxis layer is applied, which is doped in the same way as before.

Durch Wiederholen dieses Schrittes wird durch eine mehrstufi­ ge Epitaxieabscheidung schließlich die n--dotierte Zone 2 bis zu den noch einzubringenden Sourcebereichen 3, 4 vervollstän­ digt.By repeating this step, the n - -doped zone 2 is finally completed by a multi-stage epitaxial deposition up to the source regions 3 , 4 still to be introduced.

Je nach verwendeten Maske können pro Schicht die unterschied­ lichsten Strukteren gebildet werden. Die Dotierungen der Be­ reiche 28 und 29 können z. B. derart gewählt werden, daß sich die einzelnen dotierten Bereiche 28, 29 einer Schicht nach einer Hochtemperaturbehandlung mit denjenigen der darunter­ liegenden Schicht verbinden, so daß sich insgesamt, wie in Fig. 2c dargestellt, streifenförmige Bereiche 28 und 29 aus­ bilden. Die in den einzelnen Schichten dotierten Bereiche 28, 29 können jedoch auch voneinander getrennt sein, wie es in den Bereichen A und C in Fig. 1 dargestellt ist. Durch ent­ sprechende Wahl der Masken können auch statistische räumliche Verteilungen der einzelnen Gebiete erreicht werden.Depending on the mask used, the most diverse structures can be formed per layer. The doping of the Be rich 28 and 29 z. B. be chosen such that the individual doped regions 28 , 29 of a layer combine after high-temperature treatment with those of the layer below, so that overall, as shown in Fig. 2c, strip-shaped regions 28 and 29 form. The regions 28 , 29 doped in the individual layers can, however, also be separated from one another, as is shown in regions A and C in FIG. 1. Statistical spatial distributions of the individual areas can also be achieved by appropriate selection of the masks.

Schließlich werden die Sourcebereiche 3, 4 z. B. in eine wei­ tere aufgebrachte Epitaxieschicht eingebracht, und in den üb­ rigen Bereichen kann z. B. eine weitere Dotierung von n-/p- Bereichen 28, 29 erfolgen, so daß sich die streifenförmigen Bereiche 28, 29 in der Zone, in welcher kein Sourcebereich 3, 4 vorgesehen ist, bis zur Oberfläche der Epitaxieschicht 2 erstrecken.Finally, the source regions 3 , 4 z. B. introduced in a white tere applied epitaxial layer, and in the usual areas such. B. a further doping of n- / p-regions 28 , 29 take place, so that the strip-shaped regions 28 , 29 in the zone in which no source region 3 , 4 is provided extend to the surface of the epitaxial layer 2 .

Die am Randbereich eingbrachten p- und n-dotierten Gebiete, in Fig. 2d mit 30 und 31 bezeichnet, können vorzugsweise schwächer als die übrigen Bereiche 28, 29 dotiert sein.The p- and n-doped regions introduced at the edge region, designated 30 and 31 in FIG. 2d, can preferably be less doped than the other regions 28 , 29 .

Es folgen nun weitere Schritte zur Aufbringung der Gateelek­ troden 6 bzw. der Randgateelektrode 32 und der Metallisierung 5 in bekannter Weise.There now follow further steps for applying the gate electrodes 6 or the edge gate electrode 32 and the metallization 5 in a known manner.

Fig. 4 zeigt ein weiteres Ausführungsbeispiel eines erfin­ dungsgemäßen vertikalen MOSFET. Gleiche Bereiche sind gemäß den vorhergehenden Figuren mit den gleichen Bezugszeichen versehen. Fig. 4 shows another embodiment of an inventive vertical MOSFET. Identical areas are provided with the same reference symbols in accordance with the preceding figures.

Dieser MOSFET unterscheidet sich von dem in Fig. 1 bzw. Fig. 3 gezeigten in der Ausgestaltung der n--dotierten Drain­ zone 2. Unterhalb der Gateelektroden 6 erstreckt sich hier von der Oberfläche der Epitaxieschicht 2 bis in die Substratschicht 1 eine vertikale Grabenstruktur 24. Diese ist vollständig oder teilweise mit Isolatoren z. B. Oxid und/oder schwach dotiertem Polysilizium aufgefüllt. Auch eine Kombina­ tion von mehreren übereinanderliegenden Isolationsschichten mit dazwischenliegendem schwach dotierten Polysilizium ist möglich.This MOSFET is different from that shown in Figure 1 and Figure 3 in the configuration of the n -.. -Doped drain region 2. Below the gate electrodes 6 , a vertical trench structure 24 extends from the surface of the epitaxial layer 2 to the substrate layer 1 . This is completely or partially with isolators z. B. padded oxide and / or lightly doped polysilicon. A combination of several superimposed insulation layers with intervening weakly doped polysilicon is also possible.

Die Grabenwände sind mit einer n-Zone 25 umhüllt, welche rundum wiederum von einer p-Zone 26 umgeben ist. Die p- und n-Dotierung in der Grabenumhüllung ist so bemessen, daß bei einer UD-Spannung, welche kleiner als die Durchbruchspannung zwischen den Bereichen 25 und 26 ist, beide n- und p-Bereiche 25 und 26 nahezu vollkommen ausgeräumt werden.The trench walls are covered with an n-zone 25 , which in turn is surrounded by a p-zone 26 . The p- and n-doping in the trench cladding is dimensioned such that with a U D voltage which is less than the breakdown voltage between the regions 25 and 26 , both n and p regions 25 and 26 are almost completely cleared out.

Der Querschnitt der Gräben 24 kann rund, streifenförmig, d. h. beliebig sein. Der Graben muß sich dabei nicht bis in die Substratzone 1 erstrecken, vielmehr ist der Tiefenverlauf frei wählbar. Wird z. B. ein runder Grabenquerschnitt ge­ wählt, so erhalten die Schichten 25, 26 eine quasi zylindrige Form.The cross section of the trenches 24 can be round, strip-shaped, ie any. The trench does not have to extend into the substrate zone 1 , rather the depth profile can be freely selected. Is z. B. selects a round trench cross-section, the layers 25 , 26 receive a quasi cylindrical shape.

Selbstverständlich kann auch, wie in Fig. 3 durch Klammern angedeutet, der innere Wandbereich 25 p-dotiert und der ihn umgebende äußere Wandbereich 26 n-dotiert sein.Of course, as indicated by brackets in FIG. 3, the inner wall region 25 can also be p-doped and the outer wall region 26 surrounding it can be n-doped.

Es ist auch möglich, nur einen Teil der Grabenwände mit der n- und der p-Schicht zu belegen.It is also possible to use only part of the trench walls n and the p layer.

Nachfolgend wird ein mögliches Herstellverfahren beschrieben: Zuerst werden in die Epitaxieschicht 2 die Gräben eingesetzt. A possible production method is described below: First, the trenches are inserted into the epitaxial layer 2 .

Dann wird von den Gräbenwänden z. B. eine Dotierungsquelle für Bor (p) abgeschieden und eingetrieben. So entsteht die p- Schicht 26. Danach wird die n-Dotierstoffquelle abgeschieden. Diese Quelle ist eine beliebig z. B. durch Ionen-Implantation hergestellte, dünne Oberflächenschicht. Nach der Einbringung der n- und p-Dotierung wird der Graben mit Isolatoren aufge­ füllt. Dies kann z. B. durch Oxidation oder Abscheidung erfol­ gen. Nachdem die Gräben fertig sind kann die Zellenstruktur nach gängigem Verfahren erzeugt werden. Die p-Zonen 26 können mit den Zellen-p-Zonen stellenweise zusammenhängen, wobei dieser Fall in Fig. 3 nicht dargestellt ist.Then z. B. a doping source for boron (p) deposited and driven. This is how p-layer 26 is created . The n-dopant source is then deposited. This source is an arbitrary z. B. manufactured by ion implantation, thin surface layer. After the introduction of the n- and p-doping, the trench is filled with insulators. This can e.g. B. by oxidation or deposition. After the trenches are finished, the cell structure can be produced by the usual method. The p-zones 26 can be connected in places with the cell p-zones, this case not being shown in FIG. 3.

Fig. 4 zeigt ein weiteres Ausführungsbeispiel entsprechend der in Fig. 3 dargestellten Anordnung. Gleiche Elemente sind auch hier mit gleichen Bezugszeichen versehen. Der Unter­ schied zur Anordnung gemäß Fig. 3 besteht in der Ausgestal­ tung der Gatestruktur. Im Gegensatz zu der in Fig. 3 darge­ stellten Anordnung ist hier die Gatestruktur zweigeteilt bzw. weist eine zentrale Aussparung 29 auf, die das Gate in zwei Teilbereiche 27 und 28 aufteilt. Sinn dieser Anordnung ist, daß ein derartiges Poly-Gate den Grabenbereich 24 maskiert. Hierdurch kann eine vereinfachte Herstellung des Grabenbe­ reichs vorgesehen werden. Wie bei bekannten Strukturen, bei denen das Gate zur Maskierung bestimmter Bereiche während des Herstellverfahrens dient, wird hier die Form des Gates ausge­ nutzt, um die Ausbildung des Grabens 24 entsprechend der Formgebung der Aussparung 29 vorzusehen. FIG. 4 shows a further exemplary embodiment corresponding to the arrangement shown in FIG. 3. The same elements are also provided with the same reference symbols here. The difference to the arrangement according to FIG. 3 consists in the configuration of the gate structure. In contrast to the arrangement shown in FIG. 3, the gate structure here is divided into two or has a central recess 29 which divides the gate into two partial regions 27 and 28 . The purpose of this arrangement is that such a poly gate masks the trench region 24 . As a result, a simplified production of the Grabenbe area can be provided. As in known structures in which the gate is used to mask certain areas during the manufacturing process, the shape of the gate is used here to provide the formation of the trench 24 in accordance with the shape of the recess 29 .

Fig. 5 zeigt ein weiteres Ausführungsbeispiel eines vertika­ len MOSFETS. Gleiche Elemente sind auch hier mit gleichen Be­ zugszeichen versehen. Die dargestellte Struktur entspricht im wesentlichen der in Fig. 3 wiedergegebenen mit dem Unter­ schied, daß der Grabenbereich hier als annähernd V-förmiger Graben 31 ausgebildet ist. Dementsprechend sind auch die p- bzw. n-dotierten umhüllenden Randbereiche 30, 32 V-förmig ausgebildet. In dem in Fig. 5 dargestellten Beispiel ist au­ ßerdem die auf der Unterseite des Bauelements auf der Substratschicht 1 aufgebrachte Kontaktierungsschicht 32 dar­ gestellt. Fig. 5 shows a further embodiment of a vertical MOSFET. The same elements are also provided with the same reference symbols here. The structure shown corresponds essentially to that shown in Fig. 3 with the difference that the trench region is formed here as an approximately V-shaped trench 31 . Accordingly, the p- or n-doped enveloping edge regions 30 , 32 are also V-shaped. In the example shown in FIG. 5, the contacting layer 32 applied to the underside of the component on the substrate layer 1 is also shown .

Von besonderem Vorteil kann es sein, den Scheitel- bzw. Um­ kehrpunkt des Grabens eher u-förmig auszubilden.It can be particularly advantageous to use the crown or um to make the intersection of the trench more U-shaped.

Ein derartiger Trench(Graben)-Drain-MOSFET ist leicht her­ stellbar, wenn die Gräben 31 wie in Fig. 5 dargestellt V- förmig ausgebildet sind, wobei ein sehr kleiner Winkel (ϕ = ungefähr 5° bis 10°) verwendet wird. Dann können die Wände 30, 32 durch Ionenimplantation mit 0° Einfallswinkel mit ho­ her Genauigkeit und Gleichmäßigkeit belegt werden. Die n- und p-Dotierungen können aus der Grabenwand durch eine oder meh­ rere Hochtemperaturbehandlungen in das einkristalline Silizi­ um der Schichten 1 und 2 eingetrieben werden.Such a trench (trench) drain MOSFET is easy to manufacture if the trenches 31 are V-shaped, as shown in FIG. 5, using a very small angle (ϕ = approximately 5 ° to 10 °). Then the walls 30 , 32 can be covered with high accuracy and uniformity by ion implantation with 0 ° incidence angle. The n- and p-dopants can be driven from the trench wall by one or more high-temperature treatments into the single-crystalline silicon around layers 1 and 2 .

Wahlweise könnte auch nur jeweils eine Seitenwand, je nach Ausbildung der Gräben mit den Schichten 30 und 32 belegt werden.Optionally, only one side wall could be covered with layers 30 and 32 depending on the design of the trenches.

Die Herstellung der Gräben 31 kann als erster Schritt, aber auch nach der Polysiliziumabscheidung erfolgen. Im letzteren Fall wird das Maskieren der Gräben 31 durch Öffnungen im Po­ lysilizium und dem Gateoxid durchgeführt. Die Zellen können dabei als Säulen ausgebildet sein aber die V-förmigen Gräben können auch alleinstehend sein.The trenches 31 can be produced as a first step, but also after the polysilicon deposition. In the latter case, the masking of the trenches 31 is carried out through openings in the polysilicon and the gate oxide. The cells can be designed as columns, but the V-shaped trenches can also be isolated.

Die Gräben 24, 31 können streifenförmig verlaufen und so doe einzelnen Zellen eines MOSFET umgeben. Sie können aber auch keegelförmig ausgebildet sein und an den Kreuzungspunkten von in einer Matrix angeordneten Zellen eingebracht werden.The trenches 24 , 31 can run in strips and thus surround the individual cells of a MOSFET. However, they can also have a conical shape and be introduced at the crossing points of cells arranged in a matrix.

Selbstverständlich kann die Epitaxieschicht in allen Fällen sowohl vom n-- oder vom p--Typ sein.Of course, the epitaxial layer may in all cases, both the n - -type be - - or p.

Zusammenfassend ist zu bemerken, daß durch die vorliegende Erfindung sowohl vertikale wie auch laterale MOSFETS mit niedrigem Durchlaßwiderstand Ron bei gleichzeitig hoher Sperrspannung vorgesehen werden können. Wesentlich ist die Ausbildung von paarweisen p- bzw. n-dotierten Bereichen, wel­ che strukturiert oder statistisch verteilt eingebracht sind, wobei vorzugsweise streifenförmiger Bereiche vorgesehen sind, die entlang des Strompfads der Laststrecke ausgebildet sind. Die vorliegende Erfindung ist dabei sowohl bei MOSFETS vom p- Kanal wie auch bei MOSFETS vom n-Kanal oder auch bei entspre­ chenden IGBT's anwendbar.In summary, it should be noted that the present invention can provide both vertical and lateral MOSFETS with a low forward resistance R on and a high reverse voltage at the same time. What is essential is the formation of pairs of p-doped or n-doped regions, which are introduced in a structured or statistically distributed manner, preferably strip-shaped regions being provided which are formed along the current path of the load path. The present invention can be used both with MOSFETS from the p-channel and with MOSFETS from the n-channel or with corresponding IGBTs.

Claims (11)

1. Durch Feldeffekt steuerbares Halbleiterbauelement mit
einer Drainzone vom ersten Leitungstyp,
wenigstens einer aus polykristallinem Silizium bestehenden Gateelektrode, wobei diese gegenüber der Drainzone isoliert ist,
wenigstens einem in der Drainzone eingebrachten Sourcebe­ reich vom zweiten Leitungstyp,
dadurch gekennzeichnet, daß in der Drainzone (1, 2) Bereiche vom jeweils ersten und zweiten Lei­ tungstyp (7, 8; 9, 10; 11, 12; 13, 14; 28, 29) eingebracht sind, wobei Gesamtmenge der Dotierung der eingebrachten n- Bereiche (8, 9, 11, 14, 28) in etwa der Gesamtmenge der Do­ tierung der eingebrachten p-Bereiche (7, 10, 12, 13, 29) ent­ spricht.1. Semiconductor component controllable by field effect
a drain zone of the first conduction type,
at least one gate electrode made of polycrystalline silicon, which is insulated from the drain zone,
at least one source region of the second conduction type introduced in the drain zone,
characterized in that areas of the first and second line types ( 7 , 8 ; 9 , 10 ; 11 , 12 ; 13 , 14 ; 28 , 29 ) are introduced in the drain zone ( 1 , 2 ), the total amount of the doping being introduced n- areas ( 8 , 9 , 11 , 14 , 28 ) corresponds approximately to the total amount of the dosing of the introduced p-areas ( 7 , 10 , 12 , 13 , 29 ). 2. Durch Feldeffekt steuerbares Halbleiterbauelement nach An­ spruch 1, dadurch gekennzeichnet, daß die Be­ reiche vom ersten und zweiten Leitungstyp (7, 8; 9, 10; 11, 12; 13, 14; 28, 29) in der Drainzone (1, 2) jeweils paarweise angeordnet sind.2. Controllable by field effect semiconductor device according to claim 1, characterized in that the loading areas of the first and second conductivity type ( 7 , 8 ; 9 , 10 ; 11 , 12 ; 13 , 14 ; 28 , 29 ) in the drain zone ( 1 , 2 ) are arranged in pairs. 3. Durch Feldeffekt steuerbares Halbleiterbauelement nach An­ spruch 1 oder 2, dadurch gekennzeichnet, daß die paar­ weise eingebrachten Bereiche vom ersten und zweiten Leitung­ styp (7, 8; 9, 10; 11, 12; 13, 14; 28, 29) in der Drainzone (1, 2) einen Abstand voneinander größer gleich 0 und kleiner gleich der Breite der Raumladungszone haben.3. Controllable by field effect semiconductor device according to claim 1 or 2, characterized in that the few wise introduced areas of the first and second line type ( 7 , 8 ; 9 , 10 ; 11 , 12 ; 13 , 14 ; 28 , 29 ) in the drain zone ( 1 , 2 ) has a distance from one another of greater than or equal to 0 and less than or equal to the width of the space charge zone. 4. Durch Feldeffekt steuerbares Halbleiterbauelement gemäß einem der Ansprüche 2 bis 3, dadurch gekennzeichnet, daß die paar­ weise angeordneten Bereiche (9, 10; 11, 12; 28, 29) jeweils streifen- oder fadenförmig ausgebildet sind.4. Controllable by field effect semiconductor device according to one of claims 2 to 3, characterized in that the pair of wise arranged areas ( 9 , 10 ; 11 , 12 ; 28 , 29 ) are each strip or thread-shaped. 5. Durch Feldeffekt steuerbares Halbleiterbauelement gemäß einem der Ansprüche 2 bis 3, dadurch gekennzeichnet, daß die in der Drainzone eingebrachten Bereiche (7, 8; 13, 14; 28, 29) kugelförmig ausgebildet sind.5. The field effect controllable semiconductor component according to one of claims 2 to 3, characterized in that the areas introduced into the drain zone ( 7 , 8 ; 13 , 14 ; 28 , 29 ) are spherical. 6. Durch Feldeffekt steuerbares Halbleiterbauelement gemäß einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß innerhalb der Drainzone (1, 2) ein Graben (24, 31) vorgesehen ist, der sich von der Oberfläche in die Drainzone (1, 2) erstreckt, wobei der Graben (24, 31) mit wenigstens einem Isolator aus­ gefüllt ist und der Graben (24, 31) einen ersten vertikal verlaufenden Randbereich (25, 30) aufweist, welcher minde­ stens teilweise vom ersten bzw. zweiten Leitungstyp dotiert ist und welcher mindestens teilweise von einem zweiten verti­ kal parallel verlaufenden Randbereich (26, 32) umgeben ist, der vom jeweils anderen Leitungstyp ist.6. Field effect controllable semiconductor component according to one of claims 1 to 4, characterized in that within the drain zone ( 1 , 2 ) a trench ( 24 , 31 ) is provided which extends from the surface into the drain zone ( 1 , 2 ) , wherein the trench ( 24 , 31 ) is filled with at least one insulator and the trench ( 24 , 31 ) has a first vertically running edge region ( 25 , 30 ) which is at least partially doped by the first or second conductivity type and which is at least partially surrounded by a second vertically parallel edge region ( 26 , 32 ) which is of the other type of conduction. 7. Durch Feldeffekt steuerbares Halbleiterbauelement gemäß Anspruch 6, dadurch gekennzeichnet, daß die Grä­ ben (31) annähernd V-förmig ausgebildet sind.7. Controllable by field effect semiconductor device according to claim 6, characterized in that the trenches ( 31 ) are approximately V-shaped. 8. Durch Feldeffekt steuerbares Halbleiterbauelement gemäß Anspruch 7, dadurch gekennzeichnet, daß der Um­ kehrpunkt der Gräben (31) u-förmig ausgebildet ist. 8. Controllable by field effect semiconductor device according to claim 7, characterized in that the point around the trenches ( 31 ) is U-shaped. 9. Durch Feldeffekt steuerbares Halbleiterbauelement gemäß einem der Ansprüche 6 bis 8, dadurch gekennzeichnet, daß der Iso­ lator eine Kommbination aus Isolationsmaterial und Polysili­ zium ist.9. Semiconductor component controllable by field effect according to one of claims 6 to 8, characterized in that the Iso a combination of insulation material and polysili zium is. 10. Durch Feldeffekt steuerbares Halbleiterbauelement gemäß einem der Ansprüche 6 bis 9, dadurch gekennzeichnet, daß die Grä­ ben (24, 31) streifenförmig verlaufen.10. Controllable by field effect semiconductor device according to one of claims 6 to 9, characterized in that the trenches ben ( 24 , 31 ) extend in strip form. 11. Durch Feldeffekt steuerbares Halbleiterbauelement gemäß einem der Ansprüche 6 bis 9 dadurch gekennzeichnet, daß die Grä­ ben (24, 31) kegelförmig ausgebildet sind.11. Controllable by field effect semiconductor device according to one of claims 6 to 9, characterized in that the trenches ben ( 24 , 31 ) are conical.
DE19604043A 1996-02-05 1996-02-05 Semiconductor component controllable by field effect Expired - Lifetime DE19604043C2 (en)

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DE19604043A DE19604043C2 (en) 1996-02-05 1996-02-05 Semiconductor component controllable by field effect
JP52803997A JP4047384B2 (en) 1996-02-05 1997-01-30 Semiconductor devices that can be controlled by field effects
PCT/DE1997/000182 WO1997029518A1 (en) 1996-02-05 1997-01-30 Field effect controlled semiconductor component
DE59711481T DE59711481D1 (en) 1996-02-05 1997-01-30 Semiconductor component controllable by field effect
EP00112818A EP1039548B1 (en) 1996-02-05 1997-01-30 Field effect controlled semiconductor component
EP97907035A EP0879481B1 (en) 1996-02-05 1997-01-30 Field effect controlled semiconductor component
EP03026265.3A EP1408554B1 (en) 1996-02-05 1997-01-30 Field effect controlled semiconductor component
US09/117,636 US6184555B1 (en) 1996-02-05 1997-01-30 Field effect-controlled semiconductor component
DE59707158T DE59707158D1 (en) 1996-02-05 1997-01-30 CONTROLLABLE SEMICONDUCTOR COMPONENT THROUGH FIELD EFFECT

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