DE19942677C2 - Compensation component and method for its production - Google Patents
Compensation component and method for its productionInfo
- Publication number
- DE19942677C2 DE19942677C2 DE19942677A DE19942677A DE19942677C2 DE 19942677 C2 DE19942677 C2 DE 19942677C2 DE 19942677 A DE19942677 A DE 19942677A DE 19942677 A DE19942677 A DE 19942677A DE 19942677 C2 DE19942677 C2 DE 19942677C2
- Authority
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- Germany
- Prior art keywords
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- compensation component
- component according
- doping
- drift zone
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- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 title description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 9
- 229910052738 indium Inorganic materials 0.000 claims description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 7
- 229910052763 palladium Inorganic materials 0.000 claims description 7
- 229910052716 thallium Inorganic materials 0.000 claims description 7
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims description 2
- 239000000370 acceptor Substances 0.000 description 8
- 238000002513 implantation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 108090000623 proteins and genes Proteins 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Description
Die vorliegende Erfindung betrifft ein Kompensationsbauele ment sowie ein Verfahren zu dessen Herstellung.The present invention relates to a compensation component ment and a method for its production.
Die Durchlaßverluste bei MOS-Transistoren setzen sich be kanntlich aus Verlusten im Kanal zwischen Sourcezone und Drainzone und aus ohmschen Verlusten im Driftbereich, der zur Aufnahme einer Raumladungszone im Sperrfall des MOS- Transistors dient, zusammen. Bei Hochvolt-MOS-Transistoren ist gerade der durch den Driftbereich bedingte Anteil an den ohmschen Verlusten besonders hoch und dominant.The conduction losses in MOS transistors settle known from losses in the channel between the source zone and Drain zone and from ohmic losses in the drift area, which leads to Inclusion of a space charge zone when the MOS Transistor serves together. For high-voltage MOS transistors is precisely the proportion of the ohmic losses particularly high and dominant.
Zur Reduzierung der ohmschen Verluste im Driftbereich bei Hochvolt-MOS-Transistoren wurden die Kompensationsbauelemente entwickelt: bei diesen befinden sich hoch n-leitende Gebiete und hoch p-leitende Gebiete in vertikaler Richtung im Drift bereich nebeneinander. Hierzu sind beispielsweise in einen hoch n-dotierten Halbleiterkörper säulenförmige hoch p- dotierte Gebiete eingebracht. Dabei ist die Nettodotierung horizontal über dem Driftbereich gemittelt nahezu kompen siert. Das heißt, in dem obigen Beispiel gleicht die Dotie rung der p-dotierten säulenförmigen Gebiete praktisch die Do tierung des n-leitenden Halbleiterkörpers aus. Ein Beispiel eines solchen Kompensationsbauelementes ist in DE 196 04 043 A1 beschrieben.To reduce ohmic losses in the drift range High-voltage MOS transistors became the compensation components developed: these are highly n-conducting areas and high p-type regions in the vertical direction in the drift area side by side. For example, in one highly n-doped semiconductor body columnar high p endowed areas. Here is the net funding almost compensated horizontally over the drift range siert. That is, in the example above, the dotie is the same the p-doped columnar areas practically do tion of the n-type semiconductor body. An example of such a compensation component is in DE 196 04 043 A1 described.
Wird an ein solches Kompensationsbauelement eine Sperrspan nung angelegt, so befindet sich ein wesentlicher Teil der Ge genladung der ionisierten Dotierstoffatome in der gleichen horizontalen Ebene, so daß in vertikaler Richtung zwischen den beiden Hauptoberflächen des Halbleiterkörpers die elek trische Feldstärke noch wenig reduziert wird. Mit anderen Worten, es liegt hier in vertikaler Richtung nur ein geringer resultierender Gradient der elektrischen Feldstärke vor. Da her kann in vertikaler Richtung die Sperrspannung über einer geringeren Dicke des Driftbereiches des Kompensationsbauele mentes abgebaut werden.Is a blocking chip on such a compensation component a substantial part of the Ge gene charge of the ionized dopant atoms in the same horizontal plane, so that in the vertical direction between the two main surfaces of the semiconductor body, the elec trical field strength is still little reduced. With others Words, there is only a small amount here in the vertical direction resulting gradient of the electric field strength. There forth, the reverse voltage over a reduced thickness of the drift area of the compensation component mentes are reduced.
Da aber im Durchlaßfall eine höhere wirksame n-Dotierung im Driftbereich zur Verfügung steht, zeichnen sich Kompensati onsbauelemente im Vergleich zu herkömmlichen, flächengleichen MOS-Transistoren durch drastisch geringere Verluste im lei tenden Zustand aus. Kompensationsbauelemente haben so einen erheblich reduzierten Einschaltwiderstand Ron.But since a higher effective n-doping in Drift range is available, stand out compensation onsbauelemente compared to conventional, equal area MOS transistors due to drastically lower losses in the lei condition. Compensation components have one significantly reduced on-resistance Ron.
Die Herstellung von Kompensationsbauelementen ist aufwendig, was durch die alternierende Struktur der p-leitenden und n- leitenden Gebiete im Driftbereich bedingt ist, also durch ei ne in lateraler Richtung alternierende p/n/p/n. . .-Struktur.The production of compensation components is complex, which is due to the alternating structure of the p-type and n- conductive areas in the drift area is caused by egg ne p / n / p / n alternating in the lateral direction. . .-Structure.
Bisher gibt es zwei verschiedene Methoden zum Herstellen der artiger alternierender p/n/p/n. . .-Strukturen von Kompensati onsbauelementen:So far there are two different methods of making the like alternating p / n / p / n. . . Structures by Kompensati onsbauelemente:
Bei der bevorzugten Methode werden mehrstufige Epitaxiepro zesse mit zwischengeschalteten Implantationen angewandt. Kon kret werden hier n-leitende epitaktische Schichten auf ein n+-leitendes Siliziumsubstrat aufgetragen, und nach jedem Epitaxieprozeß wird eine Implantation von Boratomen an über einanderliegenden Stellen vorgenommen, so daß bei einer nach folgenden Wärmebehandlung die übereinanderliegenden Bor- Implantationen ein säulenförmiges p-leitendes Gebiet in einem n-leitenden Gebiet bilden.In the preferred method, multi-stage epitaxial processes with intermediate implantations are used. Specifically, n-type epitaxial layers are applied to an n + -conducting silicon substrate, and after each epitaxial process, boron atoms are implanted at mutually overlapping locations, so that, after a subsequent heat treatment, the superimposed boron implantations have a columnar p-type Form an area in an n-type area.
Bei der anderen üblichen Methode werden in einen Siliziumkör per des einen Leitungstyps tiefe Trenches eingebracht, die anschließend mit Silizium des anderen Leitungstyps aufgefüllt werden.In the other usual method, a silicon body introduced deep trenches of one line type, the then filled with silicon of the other conductivity type become.
Beiden bekannten Methoden ist gemeinsam, daß sie für jede Chipgröße in einer gewünschten Spannungsklasse einen exakt angepaßten Unterbau im Silizium des Driftbereiches erfordern und ihre Prozessierung äußerst aufwendig und damit teuer ist.Both known methods have in common that they are for each Chip size in a desired voltage class one exactly require adapted substructure in the silicon of the drift area and their processing is extremely complex and therefore expensive.
Trotz dieses erheblichen Nachteiles einer komplizierten Pro zessierung und eines großen Aufwandes wurde bisher nicht dar an gedacht, ein Kompensationsbauelement sowie ein Verfahren zu dessen Herstellung auf andere Weise so zu gestalten, daß diese Nachteile überwunden werden können. Der vorliegenden Erfindung liegt daher die neue Aufgabe zugrunde, ein Kompen sationsbauelement sowie ein Verfahren zu dessen Herstellung derart anzugeben, daß auf aufwendige und teure Prozessierung verzichtet werden kann.Despite this significant disadvantage of a complicated pro Cessation and a great deal of effort has so far not been shown thought of a compensation component and a method to manufacture it in a different way so that these disadvantages can be overcome. The present The invention is therefore based on the new object, a compen station component and a method for its production to indicate such that on complex and expensive processing can be dispensed with.
Zur Lösung dieser Aufgabe sind erfindungsgemäß ein Kompensa tionsbauelement sowie ein Verfahren zu dessen Herstellung mit den Merkmalen der Patentansprüche 1 und 6 vorgesehen. Vor teilhafte Weiterbildungen der Erfindung ergeben sich aus den Unteransprüchen.To solve this problem, a compensa according to the invention tion component and a method for its production with the features of claims 1 and 6 provided. Before partial developments of the invention result from the Dependent claims.
Wesentlich an der vorliegenden Erfindung ist der Grundgedan ke, in die üblicherweise n-leitende Grunddotierung der Driftzone homogen verteilte p-leitende Atome mit etwa der gleichen Dotierungskonzentration wie die n-leitende Grunddo tierung einzubringen.The basic idea of the present invention is essential ke, in the usually n-conducting basic doping in the drift zone homogeneously distributed p-type atoms with approximately that same doping concentration as the n-type basic do introduction.
Im folgenden soll auf die homogene Verteilung von Atomen des p-Leitungstyps in einer Grunddotierung des n-Leitungstyps des Driftbereiches eingegangen werden. In the following, the homogeneous distribution of atoms of the p-line type in a basic doping of the n-line type of Drift range.
Bei der Auswahl des Dotierstoffes für diese Methode, also für das Einbringen von p-dotierenden Atomen in eine übliche n- Dotierung einer Driftzone, sollte darauf geachtet werden, daß der Abstand zwischen dem Akzeptor-Energieniveau und der Va lenzbandkante von Silizium größer ist als etwa 150 meV, so daß bei Raumtemperatur im thermischen Gleichgewicht nur ein sehr geringer Anteil der Akzeptoratome ionisiert ist. In Durchlaßrichtung des Kompensationsbauelementes wird die n- leitende Dotierung des Driftbereiches damit nur zu einem ge ringen Anteil kompensiert, so daß das Kompensationsbauele ment, insbesondere ein Transistor, die gewünschten niedrigen Durchlaßverluste hat.When choosing the dopant for this method, i.e. for the introduction of p-doping atoms into a normal n- Doping a drift zone, care should be taken that the distance between the acceptor energy level and the Va lenzbandkante of silicon is greater than about 150 meV, so that at room temperature in thermal equilibrium only one very small proportion of the acceptor atoms is ionized. In The forward direction of the compensation component is the n- conductive doping of the drift region thus only to a ge wrestle compensated so that the compensation component ment, especially a transistor, the desired low Has leakage losses.
Es muss der Abstand zwischen dem Akzeptorniveau und der Va lenzbandkante größer als der Abstand zwischen dem Donatorni veau und der Leitungsbandkante des Siliziums sein. Im Sperr fall wird nämlich eine Raumladungszone aufgebaut, die dazu führt, daß die bei der Ionisation der Akzeptoren frei werden den Löcher sofort abfließen und nicht mit anderen Akzeptor rümpfen in Wechselwirkung treten können. Es werden dann also in kurzer Zeit alle Akzeptoren ionisiert, so daß die Donato ren im Volumen des Driftbereiches kompensiert sind. Das heißt, es liegen ähnliche Verhältnisse wie bei üblichen Kom pensationsbauelementen vor.The distance between the acceptance level and the Va bilge band edge greater than the distance between the donor ni veau and the conduction band edge of the silicon. In the lock In this case, a space charge zone is built up, which leads to the fact that they are released during the ionization of the acceptors drain the holes immediately and not with any other acceptor hulls can interact. So it will be all acceptors ionized in a short time, so that the Donato ren in the volume of the drift range are compensated. The means that there are similar conditions as with conventional com pension components.
Ein wesentlicher Vorteil dieser Methode liegt in einer beson ders einfachen und damit billigen Prozeßführung im Vergleich zum Stand der Technik mit Epitaxien und Implantationen bzw. tiefen Trenches. Der p-leitende Dotierstoff, also insbesonde re Indium, Thallium und Palladium, kann ohne weiteres gleich zeitig mit der n-Dotierung beim Abscheiden der epitaktischen Schicht erzeugt werden, so daß die Implantationen entfallen können. Auch kann ein auf diese Weise behandelter epitaktischer Wafer als Grundmaterial für alle Chipgrößen einer Spannungsklasse verwendet werden, was die Logistik erheblich vereinfacht und eine Verkürzung der Durchlauf Zeiten erlaubt. Während des Abscheideprozesses für die epitaktischen Schich ten ist es nämlich möglich, die Dotierstoff Zusammensetzung über die Dicke der epitaktischen Schichten zu verändern und damit die Bauelement-Eigenschaften entsprechend einzustellen.A major advantage of this method lies in a special the simple and therefore cheap process control in comparison state of the art with epitaxy and implantation or deep trenches. The p-type dopant, in particular re indium, thallium and palladium, can easily be the same in time with the n-doping when depositing the epitaxial Layer are generated so that the implantations are omitted can. An epitaxial treatment treated in this way can also Wafers as the basic material for all chip sizes of one Voltage class are used, which is the logistics significantly simplified and a shortening of the throughput times allowed. During the deposition process for the epitaxial layers It is namely possible, the dopant composition change over the thickness of the epitaxial layers and to set the component properties accordingly.
Alternativ zur Abscheidung einer mit Indium, Thallium oder Palladium dotierten epitaktischen Schicht ist es möglich, die p-Dotierung vor dem Start einer Vorder Seitenbearbeitung in üblicher Weise einzubringen oder während des Prozesses durch Öffnungen in entsprechenden Fenstern einzudiffundieren.As an alternative to depositing one with indium, thallium or Palladium doped epitaxial layer it is possible to p-doping before starting a front side processing in in the usual way or during the process Diffuse openings in appropriate windows.
Von Bedeutung ist dabei, daß der p-leitende Dotierstoff Clu ster bildet, die ortsverschieden von den Donatoren der n-lei tenden Dotierung des Driftbereiches sind. Damit soll ein di rekter Übergang von Elektronen aus dem Donatorniveau in das Akzeptorniveau verhindert werden, während in einer Ebene über eine größere Fläche immer noch eine Kompensation der Ladungs träger erreicht wird.It is important that the p-type dopant Clu ster forms, which are different from the donors of the n-lei tending doping of the drift range. So that a di right transfer of electrons from the donor level to the Acceptor levels can be prevented while in a level above a larger area still compensates for the charge carrier is reached.
Bei dem erfindungsgemäßen Kompensationsbauelement sollte der Randabschluß n-lastig sein, was durch eine entsprechende Do tierung mit beispielsweise Selen erreicht werden kann. Der Vorteil dieses Donatorstoffes liegt darin, daß er ebenfalls mehrere tiefe Energieniveaus, wie beispielsweise ein tiefes Energieniveau mit etwa 310 meV Abstand zur Leitungsbandkante besitzt. Damit wird eine ähnliche Zeitverzögerung beim Aufbau der Raumladungszone und Sperrspannung erreicht, wie in einem homogenen Halbleitermaterial, was sich günstig auf die Ab schalteigenschaften eines Transistors und die Stabilität von dessen Rand auswirkt. In the compensation component according to the invention, the Edge closure be n-heavy, which is indicated by a corresponding do can be achieved with selenium, for example. The The advantage of this donor substance is that it is also several low energy levels, such as one deep Energy level with about 310 meV distance to the conduction band edge owns. This will result in a similar time delay during setup the space charge zone and reverse voltage reached as in one homogeneous semiconductor material, which is favorable on the Ab switching characteristics of a transistor and the stability of whose edge affects.
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The invention will be described in more detail below with reference to the drawings explained. Show it:
Fig. 1 eine schematische Veranschaulichung einer durch Cluster gebildeten p-Dotierung aus bei spielsweise Indium, Thallium oder Palladium in einem n-leitenden Gebiet eines Driftberei ches, und Fig. 1 is a schematic illustration of a p-doping formed by clusters of, for example, indium, thallium or palladium in an n-type region of a drift region, and
Fig. 2 und 3 Banddarstellungen zur Erläuterung der Dotie rung nach dem Beispiel von Fig. 1. Fig. 2 and 3 band diagrams for explaining the Dotie tion according to the example of FIG. 1,.
Nach dem Ausführungsbeispiel der Fig. 1 sind in ein n-leiten des Gebiet 7 clusterartige p-leitende Gebiete 8 mit Akzeptoratomen aus Indium, Thallium und/oder Palladium eingela gert. Diese p-leitenden Gebiete 8 in dem n-leitenden Gebiet 7 mit beispielsweise Phosphor-Donatoratomen sind so hoch do tiert, daß horizontal über dem Driftbereich die Nettodotie rung gemittelt nahezu kompensiert ist.According to the embodiment of FIG. 1, cluster-like p-type regions 8 with acceptor atoms made of indium, thallium and / or palladium are embedded in an n-type region 7. These p-type regions 8 in the n-type region 7 , for example with phosphorus donor atoms, are so highly doped that the net doping is almost compensated for horizontally over the drift region.
Die p-Dotierung für die Gebiete 8 kann praktisch gleichzeitig mit der n-Dotierung des Gebietes 7 beim Abscheiden einer ent sprechenden epitaktischen Schicht erzeugt werden. Das heißt, wenn auf ein Siliziumsubstrat, wie beispielsweise das Silizi umsubstrat 1 der Fig. 1 eine epitaktische Schicht aufgetragen wird, dann wird diese Abscheidung so vorgenommen, daß die da durch gebildete epitaktische Schicht mit der n-leitenden Phosphor-Grunddotierung mit den darin eingelagerten cluste rartigen Gebieten 8, die mit Indium, Thallium oder Palladium dotiert sind, aufwächst.The p-doping for the regions 8 can be generated practically simultaneously with the n-doping of the region 7 when depositing a corresponding epitaxial layer. That is, if an epitaxial layer is applied to a silicon substrate, such as the silicon substrate 1 of FIG. 1, then this deposition is carried out in such a way that the epitaxial layer formed by the n-type basic phosphorus doping with those embedded therein cluster-like regions 8 , which are doped with indium, thallium or palladium, grows.
Anstelle von Indium, Thallium und Palladium können gegebenen falls auch andere Materialien gewählt werden. Wesentlich ist aber, daß der Abstand D (vgl. Fig. 2) zwischen dem Akzeptor- Energieniveau 9 und der Valenzbandkante 10 des Siliziums grö ßer ist als 150 meV und auch größer ist als der Abstand d zwischen dem Donatorniveau 11 und der Leitungsbandkante 12. Dabei ist darauf zu achten, daß die entsprechenden Energieni veaus örtlich versetzt voneinander sind, wie dies in Fig. 3 schematisch angedeutet ist, um einen direkten Übergang zwi schen den Niveaus zu vermeiden. Bei örtlich gleichzeitigem Vorkommen von n- und p-leitender Dotierung im mikroskopischen Maßstab liegt damit eine homogene Kompensation bei entspre chendem Fehlen von hoch n-leitenden Zonen mit erhöhter elekt rischer Leitfähigkeit vor. Mit anderen Worten, während mikro skopisch n- und p-leitende Gebiete getrennt sind, besteht makroskopisch, das heißt bezogen auf den Maßstab der Durch bruchsladung, eine homogene Ladungsverteilung mit einem even tuell überlagerten Gradienten im Sinne eines variablen Säu lenkonzepts.Instead of indium, thallium and palladium, other materials can optionally be selected. It is essential, however, that the distance D (cf. FIG. 2) between the acceptor energy level 9 and the valence band edge 10 of the silicon is greater than 150 meV and is also greater than the distance d between the donor level 11 and the conduction band edge 12 . It should be ensured that the corresponding Energiesi levels are spatially offset from one another, as indicated schematically in Fig. 3, in order to avoid a direct transition between the levels. In the case of local simultaneous occurrence of n- and p-type doping on a microscopic scale, there is therefore a homogeneous compensation in the absence of highly n-type zones with increased electrical conductivity. In other words, while microscopic n- and p-conducting regions are separated, macroscopically, i.e. based on the scale of the breakthrough charge, there is a homogeneous charge distribution with a possibly superimposed gradient in the sense of a variable column concept.
Claims (6)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19942677A DE19942677C2 (en) | 1999-09-07 | 1999-09-07 | Compensation component and method for its production |
| DE19964214A DE19964214C2 (en) | 1999-09-07 | 1999-09-07 | Method for producing a drift zone of a compensation component |
| PCT/EP2000/008707 WO2001018870A2 (en) | 1999-09-07 | 2000-09-06 | Charge compensating semiconductor device and method for the production thereof |
| US10/093,306 US6504230B2 (en) | 1999-09-07 | 2002-03-07 | Compensation component and method for fabricating the compensation component |
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| Application Number | Priority Date | Filing Date | Title |
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| DE19942677A DE19942677C2 (en) | 1999-09-07 | 1999-09-07 | Compensation component and method for its production |
| DE19964214A DE19964214C2 (en) | 1999-09-07 | 1999-09-07 | Method for producing a drift zone of a compensation component |
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| DE19942677A1 DE19942677A1 (en) | 2001-03-22 |
| DE19942677C2 true DE19942677C2 (en) | 2001-08-16 |
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| DE19948906C2 (en) * | 1999-10-11 | 2001-08-09 | Infineon Technologies Ag | Process for producing deeply diffused n-type regions in a p-doped silicon substrate |
| DE10122364B4 (en) | 2001-05-09 | 2006-10-19 | Infineon Technologies Ag | Compensation component, circuit arrangement and method |
| DE10122361C2 (en) * | 2001-05-09 | 2003-06-18 | Infineon Technologies Ag | Semiconductor component controllable by field effect |
| DE10217610B4 (en) | 2002-04-19 | 2005-11-03 | Infineon Technologies Ag | Metal-semiconductor contact, semiconductor device, integrated circuit and method |
| DE10262169B4 (en) * | 2002-04-19 | 2016-11-03 | Infineon Technologies Ag | Semiconductor device and integrated circuit arrangement so |
| DE10314596B3 (en) * | 2003-03-31 | 2004-11-25 | Infineon Technologies Ag | Metal oxide semiconductor-compensation transistor component has a semiconductor body with a rear side with deep macropores or trenches vertically aligned to source electrode structures on the front side and to the sink regions |
| DE102007027626B4 (en) * | 2007-06-12 | 2015-08-06 | Infineon Technologies Austria Ag | Semiconductor device and method of making the same |
| DE102007044414A1 (en) * | 2007-09-17 | 2009-03-19 | Infineon Technologies Austria Ag | Semiconductor component e.g. MOS field effect transistor, has intermediate zones arranged on ditch walls, where intermediate zones are high-impedance with respect to loading compensation zones and drift zones |
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| DE19604043A1 (en) * | 1996-02-05 | 1997-08-07 | Siemens Ag | Vertical MOS field effect transistor device |
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| DE19604043A1 (en) * | 1996-02-05 | 1997-08-07 | Siemens Ag | Vertical MOS field effect transistor device |
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