EP1065711A3 - Method of manufacturing a plated electronic termination - Google Patents

Method of manufacturing a plated electronic termination Download PDF

Info

Publication number
EP1065711A3
EP1065711A3 EP00109592A EP00109592A EP1065711A3 EP 1065711 A3 EP1065711 A3 EP 1065711A3 EP 00109592 A EP00109592 A EP 00109592A EP 00109592 A EP00109592 A EP 00109592A EP 1065711 A3 EP1065711 A3 EP 1065711A3
Authority
EP
European Patent Office
Prior art keywords
manufacturing
plated electronic
electronic termination
termination
plated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00109592A
Other languages
German (de)
French (fr)
Other versions
EP1065711A2 (en
Inventor
Mark Kwoka
Jack Linn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intersil Corp
Original Assignee
Intersil Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intersil Corp filed Critical Intersil Corp
Publication of EP1065711A2 publication Critical patent/EP1065711A2/en
Publication of EP1065711A3 publication Critical patent/EP1065711A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
    • Y10T29/4921—Contact or terminal manufacturing by assembling plural parts with bonding
    • Y10T29/49211—Contact or terminal manufacturing by assembling plural parts with bonding of fused material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
    • Y10T29/49218—Contact or terminal manufacturing by assembling plural parts with deforming
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y10T29/49224—Contact or terminal manufacturing with coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Coating With Molten Metal (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
  • Shaping Metal By Deep-Drawing, Or The Like (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Wire Bonding (AREA)

Abstract

A method of making a lead finish incorporating mechanically flattening the plated coating of metal leads. This may be accomplished by mechanical means such as rolling, stamping, peening, coining, forging.
EP00109592A 1999-06-30 2000-05-05 Method of manufacturing a plated electronic termination Withdrawn EP1065711A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US343845 1999-06-30
US09/343,845 US7174626B2 (en) 1999-06-30 1999-06-30 Method of manufacturing a plated electronic termination

Publications (2)

Publication Number Publication Date
EP1065711A2 EP1065711A2 (en) 2001-01-03
EP1065711A3 true EP1065711A3 (en) 2001-11-07

Family

ID=23347929

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00109592A Withdrawn EP1065711A3 (en) 1999-06-30 2000-05-05 Method of manufacturing a plated electronic termination

Country Status (5)

Country Link
US (1) US7174626B2 (en)
EP (1) EP1065711A3 (en)
JP (1) JP2001060649A (en)
KR (1) KR20010049673A (en)
TW (1) TW469544B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7174626B2 (en) * 1999-06-30 2007-02-13 Intersil Americas, Inc. Method of manufacturing a plated electronic termination
JPWO2002005609A1 (en) * 2000-07-12 2004-03-18 ローム株式会社 Connection structure and connection method between conductors
US7309909B2 (en) * 2005-09-21 2007-12-18 Texas Instruments Incorporated Leadframes for improved moisture reliability of semiconductor devices
CN101295695A (en) * 2007-04-29 2008-10-29 飞思卡尔半导体（中国）有限公司 Lead frame with welding flux flow control
JP5079605B2 (en) * 2008-06-30 2012-11-21 株式会社オートネットワーク技術研究所 Crimp terminal, electric wire with terminal, and manufacturing method thereof
DE102018213639A1 (en) * 2018-08-14 2020-02-20 Te Connectivity Germany Gmbh Method for attaching at least one, in particular pin-shaped, contact element to a conductor track of a circuit board, pin strip for attachment to a circuit board, connection arrangement
EP4312250A1 (en) * 2022-07-28 2024-01-31 STMicroelectronics S.r.l. Method of manufacturing semiconductor devices, corresponding substrate and semiconductor device

Citations (10)

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Publication number Priority date Publication date Assignee Title
US4055062A (en) * 1975-07-15 1977-10-25 Allegheny Ludlum Industries, Inc. Process for manufacturing strip lead frames
JPS60225455A (en) * 1984-04-24 1985-11-09 Kobe Steel Ltd Lead frame
JPS6148951A (en) * 1984-08-16 1986-03-10 Toshiba Corp Semiconductor device
JPS61234554A (en) * 1985-04-11 1986-10-18 Mitsubishi Electric Corp Manufacture of leadframe
JPS6372895A (en) * 1986-09-17 1988-04-02 Nippon Mining Co Ltd Production of parts for electronic and electrical equipment
JPS63306648A (en) * 1987-06-08 1988-12-14 Shinko Electric Ind Co Ltd Lead frame for semiconductor device and manufacture thereof
JPH05315511A (en) * 1991-12-25 1993-11-26 Nikko Kinzoku Kk Lead frame material and manufacture thereof
JPH06302938A (en) * 1993-04-09 1994-10-28 Ibiden Co Ltd Printed wiring board and its manufacture
US5360991A (en) * 1993-07-29 1994-11-01 At&T Bell Laboratories Integrated circuit devices with solderable lead frame
US5522133A (en) * 1993-05-25 1996-06-04 Rohm Co., Ltd Coining method for bonding pad surface

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DE2444892C3 (en) * 1974-09-19 1982-03-18 Siemens AG, 1000 Berlin und 8000 München Process for the production of strip-shaped connection elements
US4089733A (en) * 1975-09-12 1978-05-16 Amp Incorporated Method of forming complex shaped metal-plastic composite lead frames for IC packaging
US4214120A (en) * 1978-10-27 1980-07-22 Western Electric Company, Inc. Electronic device package having solder leads and methods of assembling the package
JPS57133655A (en) * 1981-02-10 1982-08-18 Pioneer Electronic Corp Lead frame
JPS59172253A (en) * 1983-03-18 1984-09-28 Mitsubishi Electric Corp Semiconductor device
US5059455A (en) * 1988-03-08 1991-10-22 Cyclops Corporation Method for galvanizing perforated steel sheet
US5258331A (en) * 1989-10-20 1993-11-02 Texas Instruments Incorporated Method of manufacturing resin-encapsulated semiconductor device package using photoresist or pre-peg lead frame dam bars
JPH03230556A (en) * 1990-02-06 1991-10-14 Matsushita Electron Corp Lead frame for semiconductor device
JP2580059B2 (en) * 1990-03-23 1997-02-12 シャープ株式会社 Solid-state imaging device and method of manufacturing the same
US5235743A (en) * 1990-07-11 1993-08-17 Yazaki Corporation Method of manufacturing a pair of terminals having a low friction material on a mating surface to facilitate connection of the terminals
JPH04268055A (en) * 1991-02-22 1992-09-24 Yamaha Corp Manufacture of copper alloy for lead frame
US5151846A (en) * 1991-08-23 1992-09-29 General Instrument Corp. Surface mountable rectifier and method for fabricating same
US5218229A (en) * 1991-08-30 1993-06-08 Micron Technology, Inc. Inset die lead frame configuration lead frame for a semiconductor device having means for improved busing and die-lead frame attachment
US5274911A (en) * 1991-10-21 1994-01-04 American Shizuki Corporation Electronic components with leads partly solder coated
JPH05121142A (en) * 1991-10-31 1993-05-18 Yazaki Corp Manufacture of board terminal
US5256598A (en) * 1992-04-15 1993-10-26 Micron Technology, Inc. Shrink accommodating lead frame
US5307562A (en) * 1992-11-06 1994-05-03 The Whitaker Corporation Method for making contact
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US5548160A (en) * 1994-11-14 1996-08-20 Micron Technology, Inc. Method and structure for attaching a semiconductor die to a lead frame
JP3097470B2 (en) * 1994-11-15 2000-10-10 日立電線株式会社 Method and apparatus for manufacturing lead frame for semiconductor device
JPH0992763A (en) * 1995-09-22 1997-04-04 Hitachi Cable Ltd Punching process method for lead frame
EP0795918A3 (en) * 1996-03-12 2000-08-23 Lucent Technologies Inc. lead-acid battery with electrode structure, and method of making same
US6336973B1 (en) * 1997-08-05 2002-01-08 Micron Technology, Inc. Apparatus and method for modifying the configuration of an exposed surface of a viscous fluid
US5840598A (en) * 1997-08-14 1998-11-24 Micron Technology, Inc. LOC semiconductor assembled with room temperature adhesive
US6194777B1 (en) * 1998-06-27 2001-02-27 Texas Instruments Incorporated Leadframes with selective palladium plating
US7174626B2 (en) * 1999-06-30 2007-02-13 Intersil Americas, Inc. Method of manufacturing a plated electronic termination

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4055062A (en) * 1975-07-15 1977-10-25 Allegheny Ludlum Industries, Inc. Process for manufacturing strip lead frames
JPS60225455A (en) * 1984-04-24 1985-11-09 Kobe Steel Ltd Lead frame
JPS6148951A (en) * 1984-08-16 1986-03-10 Toshiba Corp Semiconductor device
JPS61234554A (en) * 1985-04-11 1986-10-18 Mitsubishi Electric Corp Manufacture of leadframe
JPS6372895A (en) * 1986-09-17 1988-04-02 Nippon Mining Co Ltd Production of parts for electronic and electrical equipment
JPS63306648A (en) * 1987-06-08 1988-12-14 Shinko Electric Ind Co Ltd Lead frame for semiconductor device and manufacture thereof
JPH05315511A (en) * 1991-12-25 1993-11-26 Nikko Kinzoku Kk Lead frame material and manufacture thereof
JPH06302938A (en) * 1993-04-09 1994-10-28 Ibiden Co Ltd Printed wiring board and its manufacture
US5522133A (en) * 1993-05-25 1996-06-04 Rohm Co., Ltd Coining method for bonding pad surface
US5360991A (en) * 1993-07-29 1994-11-01 At&T Bell Laboratories Integrated circuit devices with solderable lead frame

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 010, no. 079 (E - 391) 28 March 1986 (1986-03-28) *
PATENT ABSTRACTS OF JAPAN vol. 010, no. 209 (E - 421) 22 July 1986 (1986-07-22) *
PATENT ABSTRACTS OF JAPAN vol. 011, no. 081 (E - 488) 12 March 1987 (1987-03-12) *
PATENT ABSTRACTS OF JAPAN vol. 012, no. 301 (C - 521) 16 August 1988 (1988-08-16) *
PATENT ABSTRACTS OF JAPAN vol. 013, no. 144 (E - 740) 10 April 1989 (1989-04-10) *
PATENT ABSTRACTS OF JAPAN vol. 018, no. 120 (E - 1516) 25 February 1994 (1994-02-25) *
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 01 28 February 1995 (1995-02-28) *

Also Published As

Publication number Publication date
TW469544B (en) 2001-12-21
KR20010049673A (en) 2001-06-15
EP1065711A2 (en) 2001-01-03
US20020029473A1 (en) 2002-03-14
US7174626B2 (en) 2007-02-13
JP2001060649A (en) 2001-03-06

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