EP1033668A1 - Operational electronic unit for generating a current representing a rational power of another current - Google Patents

Abstract

The electronic block consists of a number of identical stages, each stage consisting of a pseudo conductance (Gj) whose value is made proportional to the current in the preceding stage conductance by a control transistor (Tj) supplied from the preceding stage current mirror corresponding to (T3,T5,T6). The current in any stage Ij may be made equal to the Input current Iin to produce a fractional power of Iin on another stage

Description

The present invention relates to a block electronic operator allowing to generate a current having a predetermined relationship with another current.

More specifically, the invention aims to provide an operator block capable of implementing the relationship: y = x K J in which x is representative of a first current, y is representative of a second current and k and j are two integers whose ratio defines the exponent of the value x. Consequently, the operator block according to the invention will be able to generate from a first current x, another current y which may be any rational power of the first current.

An operator block of this type has been described in a article by X. Arreguit, E. A. Vittoz and M. Merz, published in IEEE Journal of Solid State Circuits, Vol SC-22, N0.3, June 1987, this operator block being, in the context described, intended in particular to be incorporated into a data compressor applied to a hearing aid.

Figure 4 of this article shows an example of realization of such an operator block in which uses compatible bipolar transistors, (or lateral bipolar transistors compatible with a CMOS technology), to establish the relationship between two streams. Exponent of the value of the first current is determined by a resistive component which suggests varying the value to allow obtaining a variable exponent value. More specifically, a series resistance bench is provided, resistors can selectively be set circuit using selection MOS transistors.

This known operator block has the drawback of not only require bipolar transistors compatible but above all resistive components, little compatible with recent production techniques exclusively CMOS circuits devoid of any resistive component. In addition, the applications of such block are limited due, on the one hand, to the fact that the value of the variable exponent must be between 0 and 1 and, on the other hand, various precautions which must be taken to account for characteristics of compatible bipolar transistors. The object of the invention is to provide an operator unit for the kind briefly mentioned above but that either devoid of the drawbacks of the prior art. In particular, the operator block according to the invention adapts perfectly to modern techniques of realization of CMOS circuits and does not include any component other than MOS transistors.

• une pseudo-conductance G*_j connectée entre une tension d'alimentation (V*_in) et une pseudo-masse (7) et engendrant un courant de sortie (I_j);
• un transistor de contrôle (T_j) traversé par le courant de sortie I_j-1 de la cellule précédente C_j-1 et capable de contrôler ladite pseudo-conductance G*_j de telle sorte que ledit courant de sortie I_j soit proportionnel au courant I_j-1 de la cellule précédente C_j; et
• un convoyeur de courant (T₃, T₅, T₆) pour convoyer ledit courant de sortie I_j vers, d'une part, ledit transistor de contrôle de la cellule suivante C_j+1 et, d'autre part, une sortie de la cellule C_j;

   et en ce que le courant traversant le transistor de contrôle de la première cellule C₁ de ladite rangée est un courant fixe (I₀), de sorte que le courant de sortie I_j d'une cellule quelconque C_j de la rangée est proportionnel à I₀ ^j.The subject of the invention is therefore an electronic operator unit comprising a row of cells (C ₁ , C ₂ , ..., C _j , ...) and making it possible to generate a second current which has a relationship, with respect to at least a first current, of the type y = x ⁱ , where x represents the value of the first current, y the value of the second current and i is the row of the cell in said row, said operator block being characterized in that each cell Cj includes:

• a pseudo-conductance G * _j connected between a supply voltage (V * _in ) and a pseudo-ground (7) and generating an output current (I _j );
• a control transistor (T _j ) crossed by the output current I _j-1 of the previous cell C _j-1 and capable of controlling said pseudo-conductance G * _j so that said output current I _j is proportional to the current I _j-1 of the previous cell C _j ; and
• a current conveyor (T ₃ , T ₅ , T ₆ ) for conveying said output current I _j to, on the one hand, said control transistor of the next cell C _{j + 1} and, on the other hand, an output cell C _j ;

and in that the current passing through the control transistor of the first cell C ₁ of said row is a fixed current (I ₀ ), so that the output current I _j of any cell C _j of the row is proportional at I ₀ ^d .

Another object of the invention is an operator unit comprising a row of cells, the characteristics of which are as mentioned above, and making it possible to generate a second current which has a relation, with respect to a first current, of the type y = x ^{k / j} , where x represents the value of the first current, y the value of the second current and k and j the rank of cells C _k and C _j , respectively, said block being characterized in that it further comprises a control circuit (T ₁ ) delivering, from an arbitrarily chosen input current (I _in ) and the output current (I _j ) from any cell C _j of said row, said voltage d ' power supply (V * _in ) such that the currents I _in and I ₁ remain equal, so that the output current I _k of a cell C _k is such that I _k = I _in ^{k / j} .

Thanks to these characteristics, it becomes possible to take from said network on a given cell a current y which is a given rational power of current sent to another cell, the power being determined by the ratio of ranks occupied these cells in the network.

The operator block according to the invention has thus a large choice, easily obtainable by simple connections, of current values which have between them the desired power relationship.

In addition, it turns out that this operator block can be produced entirely using CMOS technology without require no resistive components.

• le circuit d'asservissement est constitué d'un seul transistor MOS qui délivre une tension d'alimentation des pseudo-conductances à une valeur telle qu'elle assure l'égalité en un courant de sortie d'une cellule choisie et un courant d'entrée donné;
• les pseudo-conductances sont constituées, chacune, par un transistor MOS polarisé de manière à travailler dans un régime de faible inversion;
• les convoyeurs de courant sont réalisés à l'aide de miroirs de courant à deux sorties.

The operator unit according to the invention can also have one or more of the following characteristics:

• the servo circuit consists of a single MOS transistor which delivers a supply voltage of the pseudo-conductances to a value such that it ensures equality in an output current of a chosen cell and a current of input given;
• the pseudo-conductances are each constituted by a MOS transistor polarized so as to work in a regime of low inversion;
• the current conveyors are made using current mirrors with two outputs.

• la figure 1 est un premier schéma de principe d'un bloc opérateur selon l'invention;
• la figure 2 montre une variante du schéma de la figure 1;
• la figure 3 est un exemple de réalisation en technologie CMOS d'une pseudo-conductance variable;
• la figure 4 représente une cellule du circuit de l'invention; et
• la figure 5 montre une réalisation d'un bloc opérateur selon l'invention.

Other characteristics and advantages of the invention will become apparent during the description which follows, given solely by way of example and made with reference to the appended drawings in which:

• Figure 1 is a first block diagram of an operator unit according to the invention;
• Figure 2 shows a variant of the diagram in Figure 1;
• FIG. 3 is an exemplary embodiment in CMOS technology of a variable pseudo-conductance;
• FIG. 4 represents a cell of the circuit of the invention; and
• FIG. 5 shows an embodiment of an operator unit according to the invention.

Figure 1 shows a first block diagram of the invention. This includes a network of conductances G * ₁ to G * _N , connected in parallel between a supply line 2, brought to the voltage V * _in , and ground 3. The reason for the asterisk affecting certain references will be explained in relation to the following figures of the description. The conductance G * ₁ is a fixed conductance, while the conductances G * ₂ to G * _N of the network are variable conductances (as indicated by the arrow which crosses them), each variable conductance being controlled so that its value is proportional to the current flowing through the conductance preceding it. Thus, G * ₂ is proportional to I ₁ , G * ₃ is proportional to I ₂ , ..., G * _N is proportional to I _N1 . For the network in Figure 1, we can therefore write: I 1 = G * 1 V * in G * 2 = (G * 1 .V * in ) / V * 0 , where 1 / V * ₀ represents a proportionality constant I 2 = G * 2 .V * in = G * 1 . (V * in ) 2 / V * 0 G * 3 = (G * 2 .V * in ) / V * 0 = G * 1 . (V * in ) 2 / V * 0 2 I 3 = G * 3 .V * in = G * 1 . (V * in ) 3 / V * 0 2 etc.

From the above, we can deduce that I ₂ is proportional to I ₁ ² , that I ₃ is proportional to I ₁ ³ , ..., I _N is proportional to I ₁ ^N. Thus, for the network of FIG. 1, each branch k is traversed by a current I _k , which is proportional to the k ^th power of I ₁ . The input voltage V * _in can be adjusted so that the current I ₁ is equal to a reference value. The currents I _j , ..., I _k can be extracted from the network by current conveyors. With the proposed use, as will be seen below, of pseudo-conductances in CMOS technology, the extraction of the output currents can be done by means of simple current mirrors.

I₁ est proportionnel à V*_in

I₂ est proportionnel à I₁ ²

I₃ est proportionnel à I₁ ³

D'où l'on déduit, I₁ est proportionnel à (I_in)^1/3.The diagram in Figure 2 shows a variant of that in Figure 1, according to which the input voltage V * _in is such that the current in a given branch j (here, j = 3) is equal to a fixed current d 'entry I _in . For this, a current generator 4, delivering the current I _in , is connected in series, between the power supply 2 and the ground 3, with the conductance G * ₃ which is traversed by the current I ₃ . The node 6, common to the current generator 4 and to the conductance G * ₃ , is connected to the inverting input (-) of an operational amplifier 5, the other input of which (+) is grounded. The voltage V * _in , at the output of the amplifier 5, is applied to the supply terminal 2 of the network and is such that it ensures equality between the currents I ₃ and I _in . According to the arrangement of Figure 2, it is then possible to set the value of the current in any branch of the network and we have the following relationships:

I ₁ is proportional to V * _in

I ₂ is proportional to I ₁ ²

I ₃ is proportional to I ₁ ³

From which we deduce, I ₁ is proportional to (I _in ) ^1/3 .

Thus, by ensuring that the current I _j is equal to a given input current I _in , we obtain, for the current I _k in the branch k:
I _k is proportional to (I _in ) ^{k / j} .

For the rest of the description, reference will be made to the article by E. A. Vittoz and X. Arreguit, entitled "Linear Networks Based on Transistors", published in Electronics Letters of February 4, 1993, Vol. 29, No. 3, pp. 297-298. This article describes, in particular, the principle of pseudo-conductances and defines pseudo-voltages. As in the article, the use in the present description of an asterisk affecting a reference allows to recognize pseudo-conductances G * and the pseudo-voltages V *.

FIG. 3 shows an example of variable pseudo-conductance in a CMOS type technology. The variable conductance G * is constituted by a MOS transistor of type P, working in low inversion, the gate of which is connected to the gate of a control transistor T, itself also of type P and working in weak inversion, having its drain at a fixed voltage V _F , its source connected to its gate and whose channel current is I.

A description of the characteristics of MOS transistors working in low inversion can be found in the article by E. A. Vittoz and J. Fellrath, titled "CMOS Analog Integrated Circuits Based on Weak Inversion Operation "and published in Journal of Solid State Circuits, Vol. SC-12, June 1977, pp. 224-231.

If the voltage at terminal 7 of transistor G * is sufficiently low compared to its gate voltage, then transistor G * is in saturated state and terminal 7 can be considered as a pseudo-mass (see article by EA Vittoz and X. Arreguit cited above). The transistor G * behaves, then, like a conductance to the earth and one can write: G * = I / V * 0 , where V * ₀ represents an arbitrary coefficient of value.

FIG. 4 shows the complete diagram of a cell J of a network, or operator block, according to the invention. We recognize the transistor acting as a variable pseudo-conductance G _j *, connected between the input voltage V * _in and the pseudo-mass 7, and the control transistor T _j , connected to a fixed voltage V _F and powered by a current I _j-1 . This current I _j-1 is extracted from the previous cell by means of a current mirror formed by the transistors M ₁ and M ₂ , both of type N; the transistor M ₂ being connected in series with the transistor T _j between the fixed voltage V _F and the ground 3 and the transistor M ₁ , mounted as a diode, being connected between the terminal 8 and the ground and having its gate connected to that of M ₂ . The current mirror in MOS technology is well known in the literature. If the transistors M ₁ and M ₂ have identical dimensions (same value of the ratio of the width W to the length L of their channel) and are arranged very close to each other on the same substrate, then they are traversed by the same channel current. It should be noted, however, that the current ratio can be made different from unity by modifying the dimensional ratio W / L of one of the two transistors of the mirror with respect to the other. The output terminal 7 of cell j constitutes the input terminal of the next cell J + 1. Likewise, the input terminal 8 of cell j constitutes the output terminal of the previous cell j-1.

The complete diagram of the network, or operator block, of the invention is represented in FIG. 5. It is composed of a set of cells C ₁ , C ₂ , ..., C _j , .... The cells are all identical; they include, if we refer to cell C _j , a P type transistor which constitutes the variable pseudo-conductance G * _j , a transistor T _j for controlling this pseudo-conductance and a current mirror formed of a first transistor, of type N diode-mounted, T ₅ and of two output transistors T ₃ and T ₆ , also of type N. The first transistor T ₃ makes it possible to apply the current I _j , crossing the pseudo-conductance G * _j , to the control transistor (analogous to the transistor Tj) of the next cell C _{j + 1} In the same way, the control transistor T _j of the cell C _j receives the current I _j-1 of the previous cell by l intermediary of an output transistor (analogous to transistor T ₆ ) of the current mirror of the previous cell C _j-1 The output transistor T ₃ makes it possible to extract the current I _j from cell C _j , if it must be used in the control loop described below. The transistor T _j is connected, in series with the output transistor (analogous to T ₆ ) of the current mirror of the previous cell C _j-1 , between a positive fixed voltage V + and a negative fixed voltage (or ground) V- . The transistor constituting the variable conductance G * _j is connected, in series with the transistor T ₅ , between the input voltage V * _in and the ground. This input voltage V * _in is generated by the transistor T _1, the N-type channel connected between a supply voltage V _{power supply} and the line 1 power V * _in. The gate 5 of the transistor T ₁ receives an input current I _{in as} well as the output current I _j of the chosen cell. The transistor T ₁ operates as a voltage follower; it supplies, on line 1, a voltage V * _in , which is such that it ensures equality between the input current I _in and the current I _j of the chosen cell. The voltage V _{power supply} is a fixed supply voltage, whose value must be sufficiently greater than the voltage V + for proper network operation. Connection means (not shown) make it possible to connect to the gate 5 of the transistor T ₁ any output current I _j . Cell C ₁ differs from other cells of the network only in that the current I ₀ supplied to the control transistor (analogous to the transistor T _j of cell C _j ) is generated by a current source 4, connected in series with said control transistor.

It should be noted that, despite the fact that the CMOS technology is preferred for the realization of operator block according to the invention, specialists will know that the latter can also be carried out at using bipolar transistors.

Claims (7)

Electronic operator unit comprising a row of cells (C ₁ , C ₂ , ..., C _j , ...) and making it possible to generate a second current which has a relation, with respect to at least a first current, of the type y = x ⁱ , where x represents the value of the first current, y the value of the second current and i is the rank of the cell in said row, characterized in that each cell Cj comprises: a pseudo-conductance G * _j connected between a supply voltage (V * _in ) and a pseudo-ground (7) and generating an output current (I _j ); a control transistor (T _j ) crossed by the output current I _j-1 of the previous cell C _j-1 and capable of controlling said pseudo-conductance G * _j so that said output current I _j is proportional to the current I _j-1 from the previous cell C _j-1 ; and a current conveyor (T ₃ , T ₅ , T ₆ ) for conveying said output current I _j to, on the one hand, said control transistor of the next cell C _{j + 1} and, on the other hand, an output cell C _j ; and in that the current passing through the control transistor of the first cell C ₁ of said row is a fixed current (I ₀ ), so that the output current I _j of any cell C _j of the row is proportional at I ₀ ^d . Operator block comprising a row of cells according to claim 1 and making it possible to generate a second current which has a relation, with respect to a first current, of the type y = x ^{k / j} , where x represents the value of the first current, y the value of the second current and k and j the rank of cells C _k and C _j , respectively, characterized in that it further comprises a servo circuit (T ₁ ) delivering, from an input current arbitrarily chosen (I _in ) and the output current (I _j ) of any cell C _j of said row, said supply voltage (V * _in ) such that the currents I _in and I ₁ remain equal, so that the output current I _k of a cell C _k is such that I _k = I _in ^{k / j} . Operator unit according to claim 2, characterized in that said servo circuit consists of a MOS transistor (T ₁ ), the gate of which is connected to a node (5) receiving said input current (I _in ) and which is extracted one said output current (I _j) and whose channel is connected between a fixed supply voltage (V _alim) and the supply node (V * _in) of all pseudo-conductances; said MOS transistor acting as a voltage follower. Operator unit according to one of claims 1 to 3, characterized in that said pseudo-conductances each consist of an MOS transistor (G * _j ), the gate of which is connected to the gate of its control transistor, the control transistor has its gate connected to its source and its drain connected to a fixed supply voltage and in that the control transistors and pseudo-conductances are polarized so as to work in a regime of low inversion. Operator unit according to claim 4, characterized in that the transistors forming said pseudo-conductances (G * _j ) are in saturated state. Operator block according to any one of claims 1 to 5, characterized in that said current conveyors are made using mirrors current at two outputs; the current mirror of each cell being connected in series with said pseudo-conductance. Operator block according to claim 6, characterized in that said control transistors and pseudo-conductances are P-channel MOS transistors and said current mirrors and follower transistor are N channel MOS transistors

Images