Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
  • G11C11/5628—Programming or writing circuits; Data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
  • G11C11/5642—Sensing or reading circuits; Data output circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
  • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/32—Timing circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
  • G11C2211/563—Multilevel memory reading aspects
  • G11C2211/5634—Reference cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
  • G11C2211/564—Miscellaneous aspects
  • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output

Definitions

• MEMORY APPARATUS INCLUDING PROGRAMMABLE NON-VOLATILE MULTI-BIT MEMORY CELL, AND APPARATUS AND METHOD FOR DEMARCATING MEMORY STATES OF THE CELL
• This invention relates to non-volatile memory devices and is more particularly concerned with certain apparatus and methods based on new concepts of memory state demarcation and programming reference signal generation for multi-bit electrically alterable non-volatile memory (EANVM) cells .
• EANVM electrically alterable non-volatile memory
• the memory cell assumes one of two information storage states, either an "on” state or an “off” state. This combination of either "on” or “off” defines one bit of information.
• a memory device using such single-bit cells to store n bits of data thus requires n separate memory cells.
• Increasing the number of bits which can be stored in a single-bit per cell memory device involves increasing the number of memory cells on a one-for-one basis with the number of bits of data to be stored.
• Methods for increasing the number of memory cells in a single memory device have relied upon advanced manufacturing techniques that produce larger chips containing more memory cells or that produce smaller memory cells (e.g., by high resolution lithography) to allow more memory cells to be placed in a given area on a single chip.
• ROMs mask-programmable read only memories
• the channel width and/or length of the memory cell is varied such that 2 n different conductivity values are obtained which correspond to 2 n different states, whereby n bits of data can be stored by a single memory cell.
• the ion implant for the threshold voltage is varied such that the memory cell will have 2 n different voltage thresholds (Vt) corresponding to 2 n different conductivity levels corresponding to 2 n different states, whereby n bits of data can be stored by a single memory cell.
• Examples of memory devices of these types are described in U.S. Patent No. 4,192,014 to Craycraft, U.S. Patent No. 4,586,163 to Koike, U.S. Patent No. 4,287,570 to Stark, U.S. Patent No. 4,327,424 to u, and U.S. Patent No. 4,847,808 to Koba ake.
• EANVM Electrically alterable non-volatile memory
• the multiple memory states of the cell are demarcated by predetermined reference signal levels that define boundaries between adjacent memory states.
• the memory cell is read out by comparing a signal from the cell with the reference signals to determine the relative levels of the cell signal and the reference signals .
• the comparison results indicate whether the cell signal level is above or below the respective memory state boundaries, and thus collectively indicate the programmed state of the cell corresponding to the stored data.
• the comparison results are encoded to reproduce the stored data and complete the cell readout operation.
• the number of reference levels required to demarcate n memory states for storing n bits of data is 2 n -l.
• the number may be greater if, for example, the uppermost or lowermost memory state is to be bounded on both sides .
• Previous approaches to programming multi-bit EANVM cells are based on a repeated cycle of programming and readout of the cell.
• the cell is programmed incrementally, by the application of programming pulses, and the programmed status of the cell is checked repeatedly during the programming process by reading out the memory state of the cell as described above to verify the attained level of programming. Programming is continued until the target memory state has been reached, as indicated by the readout of the cell.
• the programming level of a multi-bit EANVM cell should be set with a margin relative to the reference signal level or levels that demarcate the target memory state.
• the programming margin should be sufficient to avoid readout errors that might occur due to variations in operating characteristics of the cell with changing conditions such a ⁇ temperature, system voltages, or mere passage of time. More particularly, if the cell is programmed too close to a memory state boundary, slight variations in the operating characteristics could shift the cell signal level relative to the state boundary level, resulting in an error upon subsequent readout of the cell.
• Program margining is not particularly problematical in single-bit per cell memory devices, since there are only two memory states, and thus no intermediate memory states. Because it is impossible to overshoot the target state by overprogramming the cell, the cell may simply be programmed to set the cell signal level as far as possible from the reference level bounding the two memory states. By contrast, the presence of one or more intermediate memory states makes program margining a significant concern in the case of multi-bit per cell devices, because an intermediate memory state requires a programming margin that provides adequate separation from two boundary levels—that i ⁇ , the boundaries of the intermediate memory state with both the state above and the state below. Programming the cell too close to either level can result in a readout error. Also, both overprogramming and under programming must be avoided to prevent overshooting and undershooting the target intermediate state.
• Previous program margining techniques include techniques that, for programming purposes, shift the cell signal level or the reference signal levels relative to their values during normal memory readout. The effect in either case is that, for a given programming amount of the cell, the cell will read differently during programming than during a normal readout operation. The difference corresponds to the shift amount of cell signal or the reference signals and provides a programming margin.
• Another margining technique involve ⁇ the provision of additional reference signals having levels intermediate those of the state-demarcating reference levels.
• the intermediate reference levels define program margin ranges in conjunction with the state-demarcating levels.
• the predecessor applications underlying the present application disclose a completely different approach to multi-bit per cell EANVM programming (the approach is also described in detail herein) .
• the programming control scheme uses a programming reference signal corresponding to the target memory state to program the memory cell, and does not require reading out the memory ⁇ tate of the cell during programming.
• the invention claimed in the present application is based on new concepts of memory state demarcation and programming reference signal generation that can be applied with great advantage to the aforementioned approach. According to a first of these concepts, a plurality of programming reference signals (or signals set in substantial correspondence therewith) are used to generate the state- demarcating reference signals .
• each programming reference signal (or correspondingly set ⁇ ignal) has a level unique to its corresponding memory state.
• each programming reference signal or correspondingly set ⁇ ignal
• each programming reference signal has a level unique to its corresponding memory state.
• the present invention thus provides an apparatus for demarcating memory states of an EANVM cell having more than two memory states.
• the apparatus comprises a reference signal generating circuit which generates a plurality of signals corresponding to memory states of the cell, each signal having a level unique to its corresponding memory state and substantially the same as a programming reference level for controlling programming of the cell to the corresponding memory ⁇ tate.
• the reference signal generating circuit uses the plurality of signals to generate reference signals having levels that constitute boundaries of memory states of the cell.
• the invention also provides a programmable multi-level memory apparatus, which comprises an EANVM cell having more than two memory states, a programming circuit for programming the EANVM cell, and a reference signal generating circuit as described above.
• the present invention provides an apparatus for demarcating memory states of an EANVM cell having more than two memory ⁇ tate ⁇ , the apparatu ⁇ compri ⁇ ing a reference signal generating circuit which generates reference signals having levels that constitute boundaries of memory states of the cell .
• the reference signals are generated dependent upon a plurality of signal levels that are set in substantial correspondence with programming reference levels for controlling programming of the cell, with each programming reference level being unique to a different memory state of the cell.
• the invention also provides a programmable multi-level memory apparatus, which comprises an EANVM cell having more than two memory states, a programming circuit for programming the cell, and a reference signal generating circuit a ⁇ just described.
• the plurality of signals used to generate ⁇ tate-bounding the reference ⁇ ignal ⁇ are them ⁇ elve ⁇ generated by reference cells that substantially track changes in operating characteristics of the EANVM cell with change ⁇ in conditions that affect the operating characteri ⁇ tic ⁇ .
• the reference cells may have substantially the same construction a ⁇ the EANVM cell, and be manufactured concurrently with the EANVM cell, by the same fabrication process, as elements of the same integrated circuit with the EANVM cell. Thu ⁇ , the signals that are used to generate the state-bounding reference ⁇ ignal ⁇ can track changes in the operating characteristic ⁇ of the EANVM cell with high accuracy. This makes it possible to maintain optimum programming margins throughout variations in operating characteristics of the EANVM cell.
• the present invention relates to programming reference signal generation, and in particular the use of reference cells for thi ⁇ purpo ⁇ e.
• the programming reference signals are generated by corresponding reference cells which substantially track changes in operating characteristics of the EANVM cell with changes in conditions that affect the characteristic ⁇ . This assure ⁇ a ⁇ table relationship between the cell signal level and the programming reference signal levels and leads to better programming con ⁇ i ⁇ tency.
• the present invention provides a programmable multi-level memory apparatus which comprises an EANVM cell having more than two memory states, a programming reference signal generating circuit, and a programming circuit.
• the programming reference signal generating circuit includes a plurality of reference cells which substantially track changes in operating characteri ⁇ tics in the EANVM cell with changes in conditions that affect the operating characteristics.
• the reference cells include a corresponding reference cell for each memory state, with each reference cell being programmed such that the programming reference ⁇ ignal generating circuit generates a programming reference ⁇ ignal having a level uni «que to the corre ⁇ ponding memory state.
• the programming circuit selectively pro-grams the EANVM cell in accordance with the level of each programming reference cell. Still further a ⁇ pect ⁇ of the invention relate to the methodology of demarcating memory ⁇ tate ⁇ of a multi-level EANVM cell based on the principles discus ⁇ ed above.
• Fig. 1 is a generic schematic representation of a non-volatile floating gate memory cell.
• Fig. 2 i ⁇ a block diagram of a prior art ⁇ ingle-bit memory system.
• Fig. 3 i ⁇ a timing diagram of the voltage threshold of a prior art single-bit per cell EANVM sy ⁇ tem being programmed from an erased "1" state to a programmed "0" state.
• Fig. 4 is a timing diagram of the bit line voltage of a prior single-bit per cell EANVM during a read operation. It illustrates VOLTAGE signals for both the programmed and erased conditions.
• Fig. 5 is a block diagram of an M x N memory array implementing a multi-bit per cell EANVM system.
• Fig. 6 is a block diagram of a circuit for reading a multi-bit EANVM cell.
• Fig. 7 shows the bit line voltage as a function of time during a read cycle for a 2-bit per cell EANVM which has been programmed to one of four possible states, (0,0), (1,0), (0,1) and a fully erased condition (1,1).
• Four ⁇ eparate voltage levels are represented in this figure, each representing one of the four possible states. Only one of these would be present for any given read operation.
• Fig. 8 is a block diagram of a multi-bit per cell system combining program/verify and read circuitry.
• Fig. 9 is a timing diagram for the voltage threshold of a 2-bit EANVM cell being programmed from a fully erased (1,1) state to one of the other three possible state ⁇ .
• Fig. 10 is a timing diagram which illu ⁇ trate ⁇ the voltage thre ⁇ hold of a 2-bit EANVM cell being era ⁇ ed from a fully programmed (0,0) state to one of the other three possible states.
• Fig. 11 is a timing diagram illustrating the voltage threshold of a 2-bit EANVM cell during a program/verify cycle using fixed width program pulses .
• Fig. 12 is a timing diagram illustrating the bit line voltage of a 2 -bit EANVM cell during a program/verify process which uses fixed width program pulses .
• Fig. 13 is a timing diagram illustrating the voltage threshold of a 2-bit EANVM cell during a program/verify cycle using variable width program pulses.
• Fig. 14 is a timing diagram illustrating the bit line voltage of a 2-bit EANVM cell during a program/verify process which uses variable width program pulses.
• Fig. 15 is a simplified diagram of a circuit for generating read reference voltages for demarcating memory states in a 2-bit per cell EANVM in accordance with the present invention.
• Fig. 16 is a diagram showing the relation ⁇ hip between the read and programming reference voltage ⁇ in a memory system using the circuit of Fig. 15.
• Fig. 17 illustrates a modification to the circuit of Fig. 15.
• Fig. 18 illu ⁇ trate ⁇ another circuit for generating read reference voltages.
• Fig. 19 is a more generalized diagram illustrating how the circuit of Fig. 16 can be applied to a 2-bit per cell EANVM array.
• Fig. 20 is a simplified diagram of a circuit for generating programming reference voltages in accordance with the present invention.
• the circuit is shown coupled to a verify reference select circuit for selecting among the programming reference voltages.
• Figs. 21A-21D are timing diagrams of the bit line voltage during readout of a 2-bit EANVM cell programmed according to programming reference signals for each of the four pos ⁇ ible memory ⁇ tate ⁇ .
• Fig. 22 is a simplified diagram illustrating a combined circuit for generating both read and programming reference voltages in accordance with the present invention.
• Fig. 23 is a diagram similar to Fig. 22, but in which the reference cells are in the form of ROM cells.
• the conductivity range i ⁇ then sensed and encoded based on reference signal levels corresponding to boundaries of the conductivity ranges to read out the memory cell .
• the floating gate FET conductivity is electrically modified using programming hardware and algorithms which supply appropriate signals to the EANVM memory device in a program/verify control cycle which incrementally stores electrons on the floating gate until the desired conductivity level is achieved.
• the systems described herein will assume a binary system which stores 2-bits per memory cell.
• Fig. 1 is a generic schematic representation of a non-volatile floating gate FET memory cell 10.
• the FET memory cell 10 includes a control gate 12 which is used either to select the memory cell for reading or i ⁇ used to cause electrons to be injected onto a floating gate 14 during the programming process.
• Floating gate 14 is an electrically isolated structure which can indefinitely store electrons .
• a drain region 16 of the FET i ⁇ coupled to a source region 18 by a channel region 19.
• the presence or absence of electrons on floating gate 14 alters the voltage threshold of the memory cell 10 and, as a result, alters the conductivity of its channel region.
• the channel region 19 is in the fully "on", or high conductivity, state.
• FIG. 2 is a block diagram of a conventional single-bit EANVM memory system 30.
• the memory system 30 stores a single bit of information in an EANVM cell (FET) 32.
• FET EANVM cell
• the cell 32 which has the same construction as FET 10 in Fig. 1, is selected for reading or writing when a row, or word, select signal i ⁇ applied to a control gate terminal 34.
• a source terminal 36 for the cell 32 is connected to a reference ground potential.
• a drain terminal 38 is connected through a pull-up device (resistor) 39 to a voltage Vpull-up at a terminal 40. Terminal 38 serves as the output terminal of the cell 32.
• the channel of the FET When the cell 32 store ⁇ a "0" bit, the channel of the FET is in a low conductivity, or high impedance, state so that the voltage at terminal 38 is pulled up to the voltage level Vpull-up on terminal 40.
• the cell 32 stores a "1" bit, the channel of the FET i ⁇ in a high conductivity, or low impedance, state so that the voltage at terminal 38 i ⁇ pulled-down by the ground potential at terminal 36.
• a sense amplifier 42 For reading the value of the single bit stored in the cell 32, a sense amplifier 42 compares the voltage at terminal 38 with a reference voltage Ref at terminal 43. If a "0" i ⁇ ⁇ tored on the EANVM cell 32, the cell i ⁇ in a low conductivity state and, as a result, the voltage at terminal 38 is above the reference voltage at terminal 43.
• the output terminal 44 of the sense amplifier 42 will be at a low voltage, which will be transmitted through an output buffer 46 to a terminal 48 and then coupled to an I/O terminal 50 as a logical "0". If a "1" is stored in the
• the EANVM cell 32 the cell i ⁇ in a high conductivity state and, a ⁇ a result, the voltage at terminal 38 is below the reference voltage at terminal 43.
• the output of the sense amplifier 42 will be a high voltage which will be transmitted to the I/O terminal 50 as a logical "1".
• the I/O terminal 50 i ⁇ connected to the input terminal of an input latch/bu fer 52.
• the output of the input latch/buffer 52 is connected to an enable/disable terminal 54 of a program voltage switch 56.
• the program voltage switch 56 provides a bit-line program voltage on a signal line 58 connected to terminal 38.
• Another output from the program voltage switch 56 is the word line program voltage on a signal line 62, which is connected to the control gate terminal 34 of the EANVM cell 32.
• the program voltage switch 56 When a logical "0" i ⁇ present at terminal 54 of the program voltage switch 56 from the output of input latch/buffer 52 and the program voltage switch 56 i ⁇ activated by a program pulse on a ⁇ ignal line 64 from a program pulse generator 66, activated by a PGM/Write (Program/Write) signal, the program voltage switch 56 provides the program voltage Vpp (typically 12 volts) from a terminal 68 to the control gate terminal 34 of the EANVM cell 32 via signal line 62. The program voltage switch 56 also biases the drain of the EANVM cell 32 to a voltage somewhat less that Vpp, typically about 8 to 9 volts. Under these conditions, electrons are injected into the floating gate by a phenomenon known as hot electron injection.
• Vpp typically 12 volts
• Fig. 3 is a timing diagram showing the change in voltage threshold of the EANVM cell 32 under control of the word line and bit line programming voltages as the memory cell is being programmed from the fully erased "1" state to the fully programmed "0" state.
• the word line and bit line programming voltages which are controlled by the PGM/Write signal, are shown as a single pulse.
• the bit and word line program voltages are respectively applied to the drain of the memory cell 32 via the bit line terminal 38 and to the control gate via the control gate terminal 34 of the memory cell 32.
• the voltage thre ⁇ hold of the memory cell begins to increase.
• the memory cell 32 is programmed to a "0" state.
• Fowler-Nordheim tunneling can also be used instead of hot electron injection to place electrons on the floating gate.
• the multi-bit EANVM device described herein functions with either memory cell programming technique.
• the conventional programming algorithms and circuits for either type of programming are designed to program a ⁇ ingle-bit cell with a ⁇ much margin as possible in a ⁇ ⁇ hort a time as pos ⁇ ible.
• margin is defined as the additional voltage threshold needed to in ⁇ ure that the programmed cell will retain its stored value over time.
• Fig. 4 i ⁇ a timing diagram showing the bit line voltage at terminal 38 as a function of time during a memory read operation. In this example, prior to time tl the bit line i ⁇ charged to the Vpull-up condition. Note that it i ⁇ also possible that the bit line may start at any other voltage level prior to time tl.
• the EANVM cell 32 is selected and, if the cell 32 is in the era ⁇ ed or "1" ⁇ tate, the cell 32 provides a low impedance path to ground. As a re ⁇ ult, the bit line is pulled-down to near the ground potential provided at terminal 36 in Fig. 2. If the EANVM cell 32 were in the "0" or fully programmed state, the bit line voltage would remain at the Vpull-up voltage after time tl.
• the voltage on the bit-line terminal 38 and the reference voltage Ref at terminal 43 are compared by the ⁇ en ⁇ e amplifier 42, whose buffered output drives I/O terminal 50. When the reference voltage is greater than the bit line voltage, the output on I/O terminal 50 is a logical "1". When the reference voltage is lower than the bit line voltage, the output on I/O terminal 50 is a logical "0".
• Fig. 5 is a block diagram of a multi-bit per cell EANVM system 100 in accordance with the present invention, which includes an M x N array of EANVM cell ⁇ .
• the cells are shown as floating gate FET cell ⁇ 102, having the ⁇ ame con ⁇ truction a ⁇ de ⁇ cribed in connection with Fig. 1.
• the general arrangement of the ⁇ y ⁇ te is similar to that used for conventional single-bit per cell memory devices, although on a detailed level there are significant differences related to the multi-bit per cell implementation as will be apparent later.
• Each cell 102 in Fig. 5 belongs to a row and a column of the array and has its ⁇ ource connected to a ground reference potential and it ⁇ drain connected to a corresponding column bit line 106.
• the column bit lines are connected to corresponding pull-up devices indicated collectively by the block 105. All control gates of a row of cell ⁇ are connected to a corresponding row select, or word, line 104. Rows are selected with a row select circuit 108 and columns are selected with a column select circuit 110 in the u ⁇ ual manner. Row and column address signals are provided over corresponding address busses 103A and 103B. Sen ⁇ e amplifier ⁇ 112 are provided for each of the column ⁇ of the array.
• a PGM/Write ⁇ ignal i ⁇ provided at an input terminal 118 for activating a mode control circuit 120 and a timing circuit 122.
• Fig. 6 show ⁇ a binary ⁇ y ⁇ tem 150 for reading the state of multi-bit floating gate memory cell 102.
• the number of bits per cell (n) is assumed to be 2 , so that one of four states of the memory cell must be detected, the four pos ⁇ ible ⁇ tate ⁇ being (0,0), (0,1), (1,0), and (1,1).
• a 4-level ⁇ en ⁇ e amplifier 152 is provided. This amplifier includes three sense amplifiers 154, 156, and 158, each of which has its negative input terminal connected to the output terminal 138 of the memory cell 102.
• Sense amplifier 154 has a reference voltage Ref3 connected to its positive input terminal
• sense amplifier 156 has a reference voltage Ref2 connected to its positive input terminal
• sense amplifier 158 has a reference voltage Refl connected to its positive input terminal.
• These reference voltages demarcate the four memory states of the cell 102 and are set so as to ⁇ ati ⁇ fy the relation ⁇ hip Vpull-up > Ref3 > Ref2 > Refl (preferred techniques for generating the ⁇ e reference voltage ⁇ will be de ⁇ cribed later) .
• the re ⁇ pective output signals S3, S2, SI of the three sen ⁇ e amplifier ⁇ drive an encode logic circuit 160, which encode ⁇ the sensed signal ⁇ S3, S2, SI into an appropriate 2-bit data format. Bit 0 is provided at an I/O terminal 162, and Bit 1 is provided at an I/O terminal 164.
• a truth table for the encode logic circuit 160 is as follow ⁇ :
• the level ⁇ of the respective output signals S3, S2, SI of the sense amplifiers 154, 156, 158 are determined by the conductivity value to which the memory cell has been set during a programming operation (to be described later) .
• EANVM cell 102 When fully erased, EANVM cell 102 will be in its lowest thre ⁇ hold voltage ⁇ tate—that i ⁇ , the highe ⁇ t conductivity ⁇ tate. Conse-quently, all of the reference voltages will be higher than the bit line voltage at terminal 138, indicating a (1,1) state. When fully programmed, EANVM cell 102 will be in its highest threshold voltage state, that is, its lowest conductivity state.
• Fig. 7 shows the bit line voltage at terminal 138 as a function of time during a read cycle for the memory cell 102. For purposes of illustration, each of the four pos ⁇ ible voltage ⁇ ignal ⁇ corre ⁇ ponding to the four po ⁇ ible programmed ⁇ tate ⁇ of the memory cell are shown. During a read cycle, only the signal corresponding to the actual programmed state of the EANVM cell would occur. For example, assume the EANVM memory cell 102 has been programmed to a (1,0) state.
• the bit line 106 Prior to time tl, because the EANVM cell 102 has not yet been selected or activated, the bit line 106 is pulled up to Vpull-up. At time tl, the EANVM cell is selected using standard memory addres ⁇ decoding techniques. Because the EANVM cell has been programmed to a specific conductivity level by the charge on the floating gate, the bit line is pulled down to a specific voltage level corresponding to the amount of current that the cell can sink at this specific conductivity level . When this point is reached at time t2, the bit line voltage stabilizes at a voltage level Vref3 between reference voltages Ref 3 and Ref 2 which bound the (1,0) state. When the EANVM cell 102 is de- ⁇ elected, the bit line voltage will return to its pulled-up condition. Similarly, the bit-line voltage stabilize ⁇ at Vref2 for the (0,1) state or at 0 volts for the (1,1) state.
• Fig. 8 is a block diagram of circuitry 200 for programming and reading memory cell 102. Although a binary 2-bit per cell system is shown for purposes of illu ⁇ tration, it i ⁇ to be understood that the principles of the invention are similarly applicable to any system where the EANVM cell has more than two state ⁇ . For example, in a non-binary ⁇ y ⁇ tem, the memory states can be three or some other multiple of a non-binary base.
• the sy ⁇ tem 200 includes a memory cell 102 with a bit line output terminal 138.
• the 4-level sen ⁇ e amplifier 152 supplied with read reference voltages Refl, Ref2, and Ref3, and the encoder 160 are provided.
• Read data is provided at the Bit 0 I/O terminal 162 and at the Bit 1 1/0 terminal 164.
• a verify reference select circuit 222 provides an analog programming voltage reference level ⁇ ignal X to one input terminal of an analog comparator 202.
• the programming reference voltage ⁇ are cho ⁇ en so that as soon as the bit line voltage on bit line 106 has reached the programming reference voltage level corresponding to a target memory state, the EANVM cell 102 is set to a proper threshold corresponding to the target memory state.
• the programming reference voltages Vrefl, Vref2, Vref3, and Vref4 are set such that Vref4 i ⁇ above
• the verify reference select circuit 222 is controlled by the two output bits from a 2 -bit input latch/buffer circuit 224, which receive ⁇ binary input bit ⁇ from the I/O terminal ⁇ 162 and 164.
• the Y ⁇ ignal input terminal of the analog comparator 202 i ⁇ connected to the bit line output terminal 138 of the multi-level memory cell 102.
• the output ⁇ ignal from the analog comparator i ⁇ provided on a signal line 204 as an enable/disable ⁇ ignal for a program voltage ⁇ witch 220.
• An output signal line 206 from the program voltage switch 220 provides the word line program voltage to the control gate of the EANVM cell 102.
• Another output signal line 106 provides the bit line programming voltage to the bit line terminal 138 of EANVM cell 102.
• the timing circuit 208 After the program/verify timing circuit 208 is enabled by a PGM/Write ⁇ ignal provided on ⁇ ignal line 212 from a PGM/Write terminal 214, the timing circuit 208 provides a ⁇ erie ⁇ of program/verify timing pul ⁇ es to the program voltage switch 220 on a signal line 210.
• the pulse widths are set to control the programming process so that the voltage threshold of the EANVM cell 102 is incrementally altered by controlling the injection of charge onto the floating gate of the EANVM cell . Each programming cycle changes the voltage threshold and, as a result, the conductivity of the memory cell 102.
• the program voltages provided by the program voltage switch 220 are removed, and a verify cycle begins.
• the voltage threshold of memory cell 102 is then determined by using the comparator 202 to compare the bit line voltage at terminal 138 with the selected programming reference voltage from the verify reference select circuit 222.
• the output signal from the comparator on line 204 will disable the program voltage switch 220, ending the programming cycle.
• the analog comparator 202 For this embodiment of the invention, during a write operation, comparison of the current memory cell analog contents with the analog information to be programmed on the memory cell 102 is performed by the analog comparator 202.
• the verify reference select circuit 222 analog output voltage X is determined by decoding the output of the 2-bit input latch/buffer 224.
• the Y input ⁇ ignal to the analog comparator 202 is taken directly from the bit line terminal 138.
• the 4-level sense/encode circuit ⁇ 152, 160, and verify reference ⁇ elect circuit 222 may be completely independent, as indicated in the drawing. Alternatively, they may be coupled together to alternately time share common circuit components. This is possible because the 4-level sense/encode circuits 152 and 160 are used in the read mode of operation while the verify reference select circuit 222 is used only in the write/verify mode of operation.
• n the number of bits per cell
• a first such threshold i ⁇ determined so that, in the read mode, the bit line voltage will fall between Refl and Ref2.
• Another such threshold is determined so that, in the read mode, the bit line voltage will fall between Ref2 and Ref3.
• Fig. 9 illustrates the change in voltage threshold of a 4-level, or 2-bit, EANVM cell as the floating gate is being charged from an erased (1,1) threshold state to any one of the three other pos ⁇ ible states (the charging being shown a ⁇ continuous for simplicity) .
• Vtl, Vt2, and Vt3 in Fig. 9 are thresholds corresponding to the read reference levels Refl, Ref2, and Ref3, respectively.
• the plots labeled (0,1), (1,0), and (0,0) correspond to the programming thresholds for those state ⁇ , which are the three non-erased state ⁇ .
• the memory cell in a multi-bit per cell system, the memory cell must be charged to a point so that the voltage threshold is within a specific voltage threshold range.
• the proper thre ⁇ hold range i ⁇ defined a ⁇ being above a thre ⁇ hold level Vt2 and a ⁇ being below a thre ⁇ hold level Vt3.
• the prior art EANVM circuitry is modified to the arrangement shown in Fig. 8.
• the comparator in Fig. 8, incidentally, is preferably analog as shown. However, a digital comparator could be used.
• Fig. 8 The comparator in Fig. 8, incidentally, is preferably analog as shown. However, a digital comparator could be used.
• EANVM 10 illu ⁇ trates the voltage threshold of a 4-level, or 2 -bit, EANVM cell as the floating gate is being erased from a (0,0) ⁇ tate (the era ⁇ ing being shown as continuous for simplicity) .
• the EANVM programming operating procedure may call for a memory cell to be erased prior to being programmed. This erasure can be performed at the byte, block, or chip level and can be performed by electrical, UV, or other means. In this type of sy ⁇ tem, the cell would be completely erased to a (1,1) state prior to initiating a programming cycle. If a system has the capability to erase an individual memory cell, then it i ⁇ not necessary to erase all of the cells of a group prior to initiating a programming operation. It is then possible to incrementally erase an individual memory cell as necessary to program the cell to the appropriate one of the voltage thresholds indicated by the plots labeled (1,0), (0,1), and (1,1).
• Fig. 11 is a voltage threshold timing diagram which illustrates how the system of Fig. 8 program ⁇ the 2-bit EANVM cell 102 from an erased (1,1) state to a (1,0) state using the timing circuitry 208 to generate fixed-width timing pulses.
• a low logic level state of the PGM/Write signal on signal line 212 enables the timing circuit 208.
• the timing circuit 208 After being enabled at time tl, the timing circuit 208 provides an internal fixed-width low-level internal PGM timing pulse on signal line 210 to the program voltage switch 220. This pulse is output following an initial verify cycle which will be discus ⁇ ed in connection with Fig. 12.
• the bit line and word line program voltage outputs on lines 106 and 206 will be raised to their respective programming voltage level ⁇ as indicated in Fig. 11.
• charge i ⁇ added to the floating gate of the memory cell 102.
• verify reference voltage Vref3 is compared with the bit line voltage. This internally controlled program/verify cycle repeats itself until the bit line voltage on terminal 138 has reached Vref3.
• the EANVM cell 102 is verified to have been programmed to a (1,0) ⁇ tate, and programming i ⁇ halted by the comparator 222 providing a di ⁇ able signal on signal line 204 to the program voltage switch 220.
• Fig. 12 illu ⁇ trate ⁇ the bit line voltage of the 2-bit EANVM cell 102 as it is being programmed from the fully erased, or fully “on”, state (1,1) to the partially “off” state (1,0) using fixed-width program pulses.
• the program/verify timing circuit 208 first initiates a verify cycle to determine the current status of the memory cell 102. This i ⁇ indicated by the bit line voltage being pulled to a ground condition (corresponding to the erased state) from, in this example, Vpull-up, although prior to time tl, the bit line voltage could be pre-set to any voltage level.
• the first program cycle is initiated. Thi ⁇ i ⁇ repre ⁇ ented by the bit line voltage being pulled up to Vprogram. After the fir ⁇ t fixed-width programming pulse ends, a verify cycle begin ⁇ . This is repre ⁇ ented by the bit line voltage being pulled down to a point midway between ground potential and Refl. During each successive verify cycle, the bit line voltage is observed to incrementally increase. This program/verify cycle continues until the bit line voltage has reached the selected programming reference voltage, in thi ⁇ case Vref3, which indicates a memory state of (1,0), at time t2.
• Fig. 13 illustrates how the 2-bit EANVM cell 102 i ⁇ programmed from the era ⁇ ed (1,1) state to the (1,0) state using a timing circuit 208 that generates variable-width programming pulses.
• the low state pulse widths grow progressively shorter as the memory cell approaches the target voltage threshold. This approach requires more precise control than the fixed-width approach. However, programming times can be greatly reduced on average .
• Fig. 14 illustrate ⁇ the bit line voltage of cell 102 a ⁇ it i ⁇ being programmed from the fully era ⁇ ed, or fully “on", ⁇ tate (1,1) to the partially “off” ⁇ tate (1,0) using variable length program pulse ⁇ .
• the program/verify timing circuit 208 first initiate ⁇ a verify cycle to determine the current ⁇ tatu ⁇ of the memory cell 102.
• the fir ⁇ t program cycle is initiated. This is represented by the bit line voltage being pulled up to Vprogram. After the fir ⁇ t variable length programming pulse is over, another verify cycle begin ⁇ . This i ⁇ repre ⁇ ented by the bit line voltage being pulled down to a point midway between Refl and Ref2. During each successive verify cycle, the bit line voltage is observed to have increased. This program/verify cycle continues until the bit line voltage has reached the selected programming reference voltage, in thi ⁇ ca ⁇ e Vref3, which indicate ⁇ a memory ⁇ tate of (1,0), at time t2.
• the programming process for the multi-bit per cell EANVM uses program/verify cycle ⁇ , to incrementally program the cell.
• the durations of these cycles are determined by the timing circuit 208.
• a key element of the system is to provide a programming scheme which provides for accurate programming of the memory cell 102. This is accomplished by matching the pulse widths of the timing pulses of the timing circuitry 208 to the program time of the EANVM cell being used. As seen from Figs. 11 and 13, a desired voltage threshold actually falls within a range of threshold voltages. If the program pulses are too long, then too much charge may be added to the floating gate of the memory cell 102. This may re ⁇ ult in an overshoot of the target voltage threshold, resulting in incorrect data being stored in the memory cell.
• the programming pulse width is set such that if the voltage threshold of the cell 102 after the (N-l)Th programming pulse is at a point just below the target voltage threshold, then the (N)Th, or final, program pulse will not cause an overshoot re ⁇ ulting in an over programmed condition for a memory cell.
• the program and read circuitry in Fig. 8 uses selectable programming reference voltage signals supplied to a bit line comparator to control programming of the ulti- bit memory cell. Programming is accomplished without reading out the cell. This allows for a significant reduction in programming time relative to previous systems that require repeated readout of the memory state of the cell during the programming process.
• the sy ⁇ tem of Fig. 8 is not limited as to the manner in which the programming and read reference signals are established.
• the embodiments described in this section implement important new concepts in memory state demarcation and programming control to enhance the reliability of the sy ⁇ tem.
• the embodiment ⁇ for memory state demarcation are based on a new concept whereby the read reference signal ⁇ are generated u ⁇ ing the programming reference ⁇ ignal ⁇ , or ⁇ ignal ⁇ set in sub ⁇ tantial corre ⁇ pondence with the programming reference ⁇ ignal ⁇ .
• the read reference signal ⁇ are thu ⁇ effectively dependent upon the programming reference ⁇ ignal ⁇ .
• the ⁇ ystem design can guarantee that the two set ⁇ of ⁇ ignal ⁇ will clo ⁇ ely conform with a predetermined relationship for program margining.
• the programming reference voltages of two adjacent memory states may be subjected to voltage division to generate the intervening read reference voltage. The read reference voltage will then fall midway between the two programming reference voltages. As a result, the two programming reference voltages are equally marginate from the read reference voltage.
• the embodiments related to programming control particularly addres ⁇ programming reference voltage generation.
• the ⁇ e embodiment ⁇ employ reference cell ⁇ which ⁇ ub ⁇ tantially track change ⁇ in operating characteri ⁇ tics of the memory cell (and thus its bit line signal) with changing conditions that affect the operating characteristic ⁇ , ⁇ uch as temperature, system voltages, or mere passage of time.
• the use of such reference cells which preferably have the same (or at least in large part the same) con ⁇ truction a ⁇ the memory cell, a ⁇ ure ⁇ a stable relationship between the programming reference voltages and the operating characteristics of the memory cell.
• the read reference voltages will also closely track the changes in operating characteristic ⁇ of the memory cell.
• Fig. 15 is a simplified diagram illustrating a circuit for generating the read reference voltages Refl, Ref2, and Ref3.
• the read reference voltages are generated by corre ⁇ ponding column ⁇ 1210, 1211, and 1212 of the circuit, each compri ⁇ ing a pair of reference cell ⁇ connected in a voltage divider arrangement to generate the corre ⁇ ponding read reference ⁇ ignal.
• Column 1210 include ⁇ a fir ⁇ t pair of reference cell ⁇ 1203, 1204 for generating voltage Refl.
• Column 1211 include ⁇ a ⁇ econd pair of reference cells 1205, 1206 for generating voltage Ref2.
• Column 1212 include ⁇ a third pair of reference cells 1207, 1208 for generating voltage Ref3.
• a bit line column 1209 The bit line column constitute ⁇ a portion of the main memory cell array and include ⁇ a memory cell 1202.
• reference cells 1203-1208 of the reference voltage generating circuit may, in one preferred mode, be of the same type and con ⁇ truction a ⁇ their associated memory cells (e.g., cell 1202) of the main array.
• all of the cell ⁇ 1202-1208 in Fig. 15 are assumed to be floating-gate-FET EANVM cells as previously described, all having the same construction.
• the reference cells, and indeed the reference columns, are preferably fabricated simultaneou ⁇ ly with and by the same method as the columns of the main array, a ⁇ part of the same integrated circuit with the array.
• the reference columns may be fabricated by way of the same method as the main memory cell array, but at a different time and/or a ⁇ part ⁇ of a different integrated circuit.
• Each of the reference cells 1203-1208 in Fig. 15 share ⁇ a common word (row select) line 1243 with the memory cell 1202.
• Each reference cell is also coupled, at its bit line, to a column pull-up voltage Vpull-up and the associated column output terminal via as ⁇ ociated ⁇ elect transi ⁇ tors (FET ⁇ ) 1201 and 1213, which may be NMOS or PMOS devices, for example.
• the select transi ⁇ tor ⁇ 1201 are controlled via respective select lines 1214', and the ⁇ elect tran ⁇ i ⁇ tors 1213 are controlled via respective select lines 1215' .
• each pair of reference cells are connected together, as shown, to form the respective voltage divider arrangements.
• the memory cell 1202 i ⁇ al ⁇ o coupled to a column pull-up voltage and the a ⁇ ociated column bit line output via a pair of ⁇ elect transistors 1201, 1213 controlled respectively by select line ⁇ 1214, 1215.
• the reference cell ⁇ 1203-1208 are pre-programmed at the factory to voltage thre ⁇ hold ⁇ corresponding to the programming reference voltages Vrefl-Vref4. Specifically, reference cells 1203 and 1204 are programmed respectively to voltage thresholds VI and V2 to produce voltage ⁇ equal to programming reference voltages Vrefl and Vref2 on their respective bit lines. Reference cell ⁇ 1205 and 1206 are re ⁇ pectively programmed to voltage thre ⁇ hold ⁇ V2 and V3 to produce voltage ⁇ equal to programming reference voltage ⁇ Vref2 and Vref3. Reference cell ⁇ 1207 and 1208 are respectively programmed to voltage threshold ⁇ V3 and V4 to produce voltages equal to programming references Vref3 and Vref4. The programming of the reference cells may be accomplished in any suitable manner.
• the memory device may be provided with dedicated pins for external application of ⁇ tandard reference voltage ⁇ to charge the cell ⁇ .
• the memory device may incorporate an on-board set of ROM cells having implant dosages for providing bit line voltages corresponding to the desired programming reference voltages .
• the ROM bit line voltages would be used as programming reference voltages for initially programming the EANVM reference cells .
• the EANVM reference cell ⁇ could be selectively coupled to the program verification comparator 202 (Fig. 8) to provide signal Y, and the ROM bit line voltages could be selectively applied to the comparator as signal X to program the EANVM reference cells by a programming operation as previously described.
• programming pulses of small width ( ⁇ ) the reference cell ⁇ would be programmed with good accuracy.
• the ROM cell ⁇ could al ⁇ o be u ⁇ ed to reprogram the EANVM reference cell ⁇ (under predetermined ⁇ tandard condition ⁇ ) to restore the voltage thresholds of the reference cells to design values, if necessary.
• the reference signal generating circuit shown in Fig. 15 establi ⁇ he ⁇ relationships between the programming reference voltages and the read reference voltages as shown in Fig. 16. It should be noted that the assignment of particular memory ⁇ tate ⁇ to the programming reference voltages Vrefl-Vref4 is not a critical matter, although good design practice dictates that the assignments should be consi ⁇ tent throughout the memory system. In a system employing error correction, it may be advantageous to as ⁇ ign the memory ⁇ tate ⁇ out of binary sequence to facilitate optimization of error detection and correction algorithms.
• each read reference voltage is e ⁇ tabli ⁇ hed so that the programming reference voltages for the memory state ⁇ immediately above and below are equally margined relative to the read reference voltage. More particularly, the read reference voltage ⁇ are defined a ⁇ follow ⁇ :
• Refl (Vrefl + Vref2) /2
• Ref2 (Vref2 + Vref3)/2
• Ref3 (Vref3 + Vref4)/2
• each read reference level will alway ⁇ be optimally margined relative to the adjacent programming reference level ⁇ at a po ⁇ ition midway between the programming reference level ⁇ .
• the operating characteristics of the reference cells track variations in the operating characteristics of the memory cell with changing conditions that affect the operating characteristics, the relationships shown in Fig. 16 are maintained throughout such variations. This en ⁇ ures that data stored in the memory cell over a long period of time can be read out accurately de ⁇ pite differences in temperature, system voltages, etc. at the time of readout relative to the time of data storage.
• the curve shown in Fig. 16 indicates the bit line voltage of the memory cell during readout, assuming the cell is programmed to programming reference voltage Vrefl.
• Deviation ⁇ may occur, for example, due to asymmetries in the physical arrangement of the circuit components, which are ordinarily laid out to maximize the compactness of the integrated circuit. Such asymmetries may result in differing line lengths and capacitance effects, for example, relative to the individual reference cells of a given pair.
• the deviations can be determined in advance by computer simulation of the circuit using standard computer simulation techniques. It is then pos ⁇ ible to compensate for the deviations by adding appropriate signal pulling devices on the read reference lines to pull the divided outputs of the reference cells to the design values. Such devices may al ⁇ o be provided for similar reasons on the memory cell bit lines of the main array.
• Fig. 17 shows a read-re erence ⁇ ignal generating circuit a ⁇ ju ⁇ t de ⁇ cribed.
• the circuit i ⁇ identical to that of Fig. 15, except for the addition of the aforementioned ⁇ ignal pulling devices. These devices may be constituted by field effect tran ⁇ i ⁇ tor ⁇ 1220-1223, a ⁇ shown, or by any other ⁇ uitable type of device for thi ⁇ purpo ⁇ e, ⁇ uch as capacitor and resistor combinations, etc.
• the signal pulling devices are preferably connected as closely a ⁇ po ⁇ ible to the point ⁇ where the read reference signals (and memory bit line signal ⁇ ) feed into the multi-level sen ⁇ e amplifier for reading out the memory cell. Such an arrangement will optimize the accuracy of the voltage values supplied to the sen ⁇ e amplifier relative to the design values. This i ⁇ , of course, desirable from the standpoint of high accuracy program margining and memory readout.
• Fig. 18 is a simplified diagram showing another embodiment of a circuit 1200" for generating the read reference signal ⁇ Refl, Ref2, and Ref3
• This circuit is based on the design of the circuit in Fig. 17, but the higher-value reference cell and signal puller of each reference column are replaced by a corresponding single pull-up device 1321, 1322, or 1323 to provide the voltage divider arrangements, as shown.
• the pull-up devices on the individual read reference line ⁇ in Fig. 18 have their respective signal-pulling capacities ⁇ et so that the read reference voltages will assume the same relationship ⁇ relative to the programming reference voltage ⁇ a ⁇ shown in Fig. 16. It should be noted that this embodiment is le ⁇ preferred than the arrangement of Fig. 17 from the ⁇ tandpoint of tracking the memory cell, since the pull-up devices 1321, 1322, and 1323 on the read reference lines will not track the memory cell 1202 as closely as the reference cells with changing operating conditions.
• Fig. 19 i ⁇ a more generalized diagram illu ⁇ trating how the reference ⁇ ignal generating circuit of Fig. 15 can be applied to a memory array.
• the select line 1214 and select transi ⁇ tor ⁇ 1201 which are not required but may be de ⁇ irable to reduce energy consumption, for example, have been replaced by a generic network of column pull-up ⁇ (so designated) .
• each row of memory cells in the array is provided with a corresponding set of reference cell ⁇ 1203-1208 connected to form voltage divider arrangements as previou ⁇ ly described.
• Each set (row) of reference cell ⁇ would be ⁇ elected individually for providing ⁇ ignal ⁇ on the reference column bit line ⁇ for readout of a memory cell of the corre ⁇ ponding row of the main array.
• the use of dedicated sets of reference cell ⁇ for each row of the array is preferred for accuracy.
• a reference cell for row M of the memory array in Fig. 20 will have the same number and type of component ⁇ connected between it ⁇ bit line terminal and the reference column output a ⁇ does each corresponding memory cell 1202 between its bit line terminal and the column bit line output.
• the line length from the bit line terminal of the reference cell to the reference column output can made clo ⁇ e to or the ⁇ ame as the line length from the bit line terminal of each corresponding memory cell to it ⁇ a ⁇ sociated column bit line output.
• Signal pulling devices may be added on the bit and read reference lines in a manner similar to Fig. 17.
• the ⁇ ignal pulling capacity of each device would be determined by suitable calculation during the computer simulation process to provide the best overall accuracy of the signal levels provided by the different cell ⁇ within each column of the ⁇ ystem.
• Fig. 20 is a simplified diagram showing a circuit 1500 (above the dashed line) for generating programming references Vrefl-Vref4 and an as ⁇ ociated verify reference ⁇ elect circuit 222 (below the da ⁇ hed line) for outputting the ⁇ elected ⁇ ignal X for program verification.
• the reference cells need not be part of the same integrated circuit as the memory array, but they are preferably fabricated simultaneously with and by the ⁇ ame proce ⁇ as the array, as part of the same integrated circuit, for the reasons previously explained.
• the reference cells for producing the programming reference signals Vrefl-Vref4 are arranged in corresponding column ⁇ 1511-1514, with their bit line terminals commonly connected to a corre ⁇ ponding bit line and a network of column pull-up ⁇ (so de ⁇ ignated) .
• Each ⁇ et (row) of reference cell ⁇ would be individually ⁇ elected, via an a ⁇ ociated word line 1543, for providing ⁇ ignal ⁇ on the corresponding column bit lines for programming verification of a memory cell of the corresponding row of the main memory array.
• Each reference cell 1503 in column 1511 is pre- programmed at the factory (for example, as previously described in connection with Fig. 15) to the voltage thre ⁇ hold VI to produce voltage Vrefl on the column bit line.
• Each reference cell 1504 in column 1512 i ⁇ preprogrammed to the voltage thre ⁇ hold V2 to produce voltage Vref2 on the column bit line.
• Each reference cell in column 1513 i ⁇ pre-programmed to the voltage thre ⁇ hold V3 to produce voltage Vref3 on the column bit line.
• Each reference cell in column 1514 is pre-programmed to the voltage threshold V4 to produce voltage Vref4 on the column bit line.
• Signal pulling devices may be added on the column bit lines as previou ⁇ ly explained if nece ⁇ sary to compensate for deviations of the column bit line voltage ⁇ due to effect ⁇ of layout asymmetries and the like.
• the bit line ⁇ of columns 1511-1514 are coupled to corresponding select transistors (e.g., FETs) 271-274 of verify reference select circuit 222.
• the select transi ⁇ tors which may be NMOS or PMOS devices, for example, can be controlled by a simple logic circuit, such as the logic circuit LC shown in Fig. 20.
• the circuit LC in Fig. 20 operates in accordance with the following truth table. Note that the signal ⁇ I/O0 and 1/01 are provided a ⁇ input ⁇ from the input latch/buffer 224 (see Fig. 8) .
• Fig ⁇ . 21A-21D are readout timing diagram ⁇ showing the bit line voltage level of a ⁇ elected memory cell in Fig. 20 after programming to each of the four memory ⁇ tate ⁇ .
• the bit line voltage i ⁇ at it ⁇ pre-charged value of Vpull-up, which i ⁇ at or very near the value of Vref4.
• the voltage level ha ⁇ dropped to the range indicated by the two closely ⁇ paced line ⁇ which are centered around the Vref level for the programmed state.
• the two lines indicate that there is a slight range of tolerance for the bit line voltage level relative to the programming voltage reference level during read out of the memory cell.
• FIG. 21A illustrates the bit line voltage when the memory cell has been programmed to the voltage threshold VI corresponding to the programming reference level Vrefl.
• Fig. 21B illustrates the bit line voltage when the memory cell has been programmed to the voltage threshold V2 corresponding to the programming reference level Vref2.
• Fig. 21C illustrate ⁇ the bit line voltage when the memory cell ha ⁇ been programmed to the voltage threshold V3 corresponding to the programming reference level Vref3.
• Fig. 2ID illustrate ⁇ the bit line voltage when the memory cell ha ⁇ been programmed to the voltage threshold V4 corresponding to the programming reference level Vref4.
• the read reference and programming reference generating circuits have been shown and described as separate circuits above, the circuits may readily be combined to share components as shown in Fig. 22. Thi ⁇ i ⁇ possible because the programming reference signal ⁇ and the read reference signals need not be used at the same time. More particularly, the programming reference signal ⁇ need only be used during the memory cell programming operation, whereas the read reference signal ⁇ need only be used during the memory cell readout operation.
• bit line of reference cells 1203 is connected to provide programming reference voltage Vrefl
• bit line of reference cells 1204 is connected to provide programming reference voltage Vref2
• bit line of reference cells 1207 is connected to provide programming reference voltage Vref3
• bit line of reference cells 1208 is connected to provide programming reference voltage Vref4.
• Select transistors 271-274 correspond to the ⁇ elect tran ⁇ istors shown in Fig. 20.
• Fig. 23 shows a modification of the circuit in Fig. 22, in which the EANVM reference cells 1203-1208 are replaced by ROM cells 2203-2208, respectively.
• the use of ROM cell ⁇ a ⁇ reference cells is advantageou ⁇ because it avoid ⁇ the initial programming requirement of EANVM reference cell ⁇ , although the tracking effect of the reference ⁇ ignal ⁇ relative to the EANVM cell ⁇ of the main array may be reduced ⁇ omewhat.
• corre ⁇ ponding portion ⁇ of the ROM cell ⁇ and the EANVM cell ⁇ can be fabricated by the ⁇ ame process steps.
• the sources, drain ⁇ , channel regions, and control gates of the EANVM cells and the ROM cell ⁇ may be fabricated in this manner, with separate process steps being used to provide the EANVM floating gates and the ROM threshold implants.
• the illustrative embodiments described herein are merely exemplary, and numerous changes and modifications can be made consi ⁇ tent with the principles of the invention.
• the invention has been explained in terms of voltage-based memory sy ⁇ tem ⁇ which utilize voltage ⁇ ignal ⁇ from the memory and reference cell ⁇ , the principles of the invention are equally applicable to current-based memory systems in which current levels rather than voltage levels are utilized.

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