Classifications

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  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/12—Replacement control
  • G06F12/121—Replacement control using replacement algorithms
  • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
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  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30003—Arrangements for executing specific machine instructions
  • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30003—Arrangements for executing specific machine instructions
  • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
  • G06F9/30043—LOAD or STORE instructions; Clear instruction
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30003—Arrangements for executing specific machine instructions
  • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
  • G06F9/30087—Synchronisation or serialisation instructions
• • G—PHYSICS
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  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3818—Decoding for concurrent execution
  • G06F9/382—Pipelined decoding, e.g. using predecoding
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3824—Operand accessing
• • G—PHYSICS
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  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
  • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
  • G06F9/384—Register renaming
• • G—PHYSICS
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  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
  • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
• • G—PHYSICS
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  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
  • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Definitions

• TITLE A DATA MEMORY UNIT CONFIGURED TO STORE DATA IN ONE CLOCK CYCLE AND METHOD FOR OPERATING SAME
• This invention relates to the field of superscalar microprocessors, and more particularly to a load/store unit and a data cache in a superscalar microprocessor.
• clock cycle refers to an interval of time during which the pipeline stages of a microprocessor preform their intended functions. At the end of a clock cycle, the resulting values are moved to the next pipeline stage.
• superscalar microprocessors execute multiple instructions per clock cycle and the clock cycle is short, a high bandwidth memory system is required to provide instructions and data to the superscalar microprocessor (i.e. a memory system that can provide a large number of bytes in a short period of time). Without a high bandwidth memory system, the microprocessor would spend a large number of clock cycles waiting for instructions or data to be provided, then would execute the received instructions and/or the instructions dependent upon the received data in a relatively small number of clock cycles. Overall performance would be degraded by the large number of idle clock cycles.
• superscalar microprocessors are ordinarily configured into computer systems with a large main memory composed of dynamic random access memory (DRAM) cells. DRAM cells are characterized by access times which are significantly longer than the clock cycle of modern superscalar microprocessors. Also, DRAM cells typically provide a relatively narrow output bus to convey the stored bytes to the superscalar microprocessor.
• DRAM dynamic random access memory
• DRAM cells provide a memory system that provides a relatively small number of bytes in a relatively long period of time, and do not form a high bandwidth memory system.
• superscalar microprocessors are typically not configured into a computer system with a memory system having sufficient bandwidth to continuously provide instructions and data
• superscalar microprocessors are often configured with caches.
• Caches are multiple blocks of storage locations, configured on the same silicon substrate as the microprocessor or coupled nearby. The blocks of storage locations are used to hold previously fetched instruction or data bytes. The bytes can be transferred from the cache to the destination (a register or an instruction processing pipeline) quickly; commonly one or two clock cycles are required as opposed to a large number of clock cycles to transfer bytes from a DRAM main memory.
• Caches may be organized into an "associative" structure
• an associative structure the blocks of storage locations are accessed as a two-dimensional array having rows and columns
• a number of bits from the address are used as an "index" into the cache
• the index selects a particular row within the two-dimensional array, and therefore the number of address bits required for the index is determined by the number of rows configured into the cache
• the addresses associated with bytes stored in the multiple blocks of a row are examined to determine if any of the addresses stored in the row match the requested address If a match is found, the access is said to be a "hit", and the cache provides the associated bytes If a match is not found, the access is said to be a "miss” When a miss is detected, the bytes are transferred from the memory system into the cache
• the addresses associated with bytes stored in the cache are also stored These stored addresses are referred to as "tags” or "tag addresses"
• the blocks of memory configured into a row form the columns of the row
• Each block of memory is referred to as a "way"
• multiple ways comprise a row
• the way is selected by providing a way value to the cache
• the way value is determined by examining the tags for a row and finding a match between one of the tags and the requested address
• a cache designed with one way per row is referred to as a "direct-mapped cache"
• direct-mapped cache In a direct-mapped cache, the tag must be examined to determine if an access is a hit, but the tag examination is not required to select the which bytes are transferred to the outputs of the cache
• Both direct-mapped and associative caches are employed in high frequency (l e short clock cycle) superscalar microprocessors
• one read or one write may be performed in a clock cycle when the cache is configured with a single port
• Caches are large structures which typically require most (if not all) of a clock cycle to perform a read or a write due to the large capacitances involved and other well-known properties with respect to cache arrays
• reading and writing the same memory location in a clock cycle involves making the array significantly larger and slower, thus impacting the clock cycle time and the silicon area of a superscalar microprocessor
• the problems outlined above are in large part solved by a data memory unit employing a load/store unit and a data cache according to the present invention
• the load/store unit is configured with a load/store buffer having a checked bit and a way field for each buffer storage location
• the checked bit of the storage location storing the store portion of the instruction is set when the load portion of the instruction accesses and hits the data cache
• the way field of the storage location is set to the way of the data cache in which the load portion hits
• the data cache is configured with a locking mechanism for each cache line stored in the data cache When the load portion of a load-op-store instruction is executed, the associated line is locked such that the line will remain in the data cache until a store instruction executes In this way, the store portion of the load-op-store instruction is guaranteed to hit the data cache in the way indicated by the way field associated with the store portion
• the load/store unit and data cache allow the advantageous reduction of the store portion of load-op- store instructions from two clock cycles of data cache access to one clock cycle of data cache access Performance of a superscalar microprocessor employing such a data memory unit may be increased by allowing more data cache accesses in a given set of clock cycles in which load-op-store instructions arc executed
• the present invention contemplates a data memory unit comprising a load/store unit and a data cache
• the load/store unit is configured to execute load and store instructions and includes a first plurality of storage locations configured to store outstanding store instructions and associated store data Each one of said plurality of storage locations is configured to store a checked bit
• the data cache is coupled to the load/store unit and includes a second plurality of storage locations configured to store cache lines 1 he data cache is configured to lock a cache line stored within the second plurality of storage locations such that the cache line remains stored within the plurality of storage locations at least until a clock cycle in which the lock is released
• the present invention further contemplates a method for storing store data into a data cache without first having to check the data cache for a hit on an address associated with the store data
• the method comprises storing the store data into the data cache during a first clock cycle in which a checked bit associated with the store data is set
• FIG. 1 is a block diagram of a superscalar microprocessor including a load/store unit and a data cache in accordance with the present invention
• FIG. 2 is a diagram showing certain internal components of the load/store unit including a load/store buffer in accordance with the present invention
• Figure 3 is a diagram of the bit fields of a storage location of the load/store buffer shown in Figure 2
• Figure 4A is a diagram of a tag entry for the data cache in accordance with the present invention.
• Figure 4B is a diagram of a data cache tag array including tag entries shown in Figure 4 A, including a clearing mechanism for the lock bit of the tag entry
• superscalar microprocessor 200 includes a prefetch/predecode unit 202 and a branch prediction unit 220 coupled to an instruction cache 204
• Instruction alignment unit 206 is coupled between instruction cache 204 and a plurality of decode units 208A-208F (referred to collectively as decode units 208)
• Each decode unit 208A-208F is coupled to respective reservation station units 210A-21 OF (referred to collectively as reservation stations 210), and each reservation station 21 OA-21 OF is coupled to a respective functional unit 212A-212F (referred to collectively as functional units 212)
• Decode units 208, reservation stations 210, and functional units 212 are further coupled to a reorder buffer 216, a register file 218 and a load/store unit 222
• a data cache 224 is finally shown coupled to load/store
• instruction cache 204 is a high speed cache memory provided to temporarily store instructions prior to their dispatch to decode units 208
• instruction cache 204 is configured to cache up to 32 kilobytes of instruction code organized in lines of 16 bytes each (where each byte consists of 8 bits)
• instruction code is provided to instruction cache 204 by prefetching code from a main memory (not shown) through prefetch/predecode unit 202
• instruction cache 204 could be implemented in a set-associative, a fully-associative, or a direct-mapped configuration
• Prefetch/predecode unit 202 is provided to prefetch instruction code from the mam memory for storage within instruction cache 204 In one embodiment, prefetch/predecode unit 202 is configured to burst 64-bit wide code from the mam memory into instruction cache 204 It is understood that a variety of specific code prefetching techniques and algorithms may be employed by prefetch/predecode unit 202
• prefetch/predecode unit 202 fetches instructions from the main memory, it generates three predecode bits associated with each byte of instruction code a start bit, an end bit, and a "functional" bit
• the predecode bits form tags indicative of the boundaries of each instruction
• the predecode tags may also convey additional information such as whether a given instruction can be decoded directly by decode units 208 or whether the instruction must be executed by invoking a microcode procedure controlled by MROM unit 209, as will be described in greater detail below
• Table 1 indicates one encoding of the predecode tags As indicated within the table, if a given byte is the first byte of an instruction, the start bit for that byte is set If the byte is the last byte of an instruction, the end bit for that byte is set If a particular instruction cannot be directly decoded by decode units 208, the functional bit associated with the first byte of the instruction is set On the other hand, if the instruction can be directly decoded by the decode units 208, the functional bit associated with the first byte of the instruction is cleared The functional bit for the second byte of a particular instruction is cleared if the opcode is the first byte, and is set if the opcode is the second byte It is noted that in situations where the opcode is the second byte, the first byte is a prefix byte The functional bit values for instruction byte numbers 3-8 indicate whether the byte is a MODRM or an SIB byte, or whether the byte contains displacement or immediate data
• MROM instructions MROM instructions
• fast path instructions instructions within the x86 instruction set
• MROM instructions MROM instructions
• MROM instructions are executed by invoking MROM unit 209 More specifically, when an MROM instruction is encountered, MROM unit 209 parses and serializes the instruction into a subset of defined fast path instructions to effectuate a desired operation
• a listing of exemplary x86 instructions categorized as fast path instructions as well as a description of the manner of handling both fast path and MROM instructions will be provided further below
• Instruction alignment unit 206 is provided to channel variable byte length instructions from instruction cache 204 to fixed issue positions formed by decode units 208A-208F Instruction alignment unit 206 independently and in parallel selects instructions from three groups of instruction bytes provided by instruction cache 204 and arranges these bytes into three groups of preliminary issue positions Each group of issue positions is associated with one of the three groups of instruction bytes The preliminary issue positions are then merged together to form the final issue positions, each of which is coupled to one of decode units 208
• each of the decode units 208 includes decoding circuitry for decoding the predetermined fast path instructions referred to above
• each decode unit 208A-208F routes displacement and immediate data to a corresponding reservation station unit 210A- 21 OF Output signals from the decode units 208 include bit-encoded execution instructions for the functional units 212 as well as operand address information, immediate data and/or displacement data
• the superscalar microprocessor of Figure I supports out of order execution, and thus employs reorder buffer 216 to keep track of the original program sequence for register read and write operations, to implement register renaming, to allow for speculative instruction execution and branch misprediction recovery, and to facilitate precise exceptions
• a temporary storage location within reorder buffer 216 is reserved upon decode of an instruction that
• instructions aligned and dispatched to decode unit 208B are passed to reservation station unit 21 OB and into functional unit 212B, and so on
• Reorder buffer 216 contains temporary storage locations for results which change the contents of these registers to thereby allow out of order execution
• a temporary storage location of reorder buffer 216 is reserved for each instruction which, upon decode, is determined to modify the contents of one of the real registers Therefore, at various points during execution of a particular program, reorder buffer 216 may have one or more locations which contain the speculatively executed contents of a given register If following decode of a given instruction it is determined that reorder buffer 216 has a previous location or locations assigned to a register used as an operand in the given instruction, the reorder buffer 216
• Reservation station units 21 OA-21 OF are provided to temporarily store instruction information to be speculatively executed by the corresponding functional units 212A-212F As stated previously, each reservation station unit 21 OA-21 OF may store instruction information for up to three pending instructions Each of the six reservation stations 21 OA-21 OF contain locations to store bit-encoded execution instructions to be speculatively executed by the corresponding functional unit and the values of operands If a particular operand is not available, a tag for that operand is provided from reorder buffer 216 and is stored within the corresponding reservation station until the result has been generated (i e , by completion of the execution of a previous instruction) It is noted that when an instruction is executed by one of the functional units 212A- 212F, the result of that instruction is passed directly to any reservation station units 21 OA-210r that are waiting for that result at the same time the result is passed to update reorder buffer 216 (this technique is commonly referred to as "result forwarding") Instructions are issued to functional units for execution after the values of
• each of the functional units 212 is configured to perform integer arithmetic operations of addition and subtraction, as well as shifts, rotates, logical operations, and branch operations It is noted that a floating point unit (not shown) may also be employed to accommodate floating point operations
• Each of the functional units 212 also provides information regarding the execution of conditional branch instructions to the branch prediction unit 220 If a branch prediction was incorrect, branch prediction unit 220 flushes instructions subsequent to the mispredicted branch that have entered the instruction processing pipeline, and causes prefetch/predecode unit 202 to fetch the required instructions from instruction cache 204 or main memory It is noted that in such situations, results of instructions in the original program sequence which occur after the mispredicted branch instruction are discarded, including those which were speculatively executed and temporarily stored in load/store unit 222 and reorder buffer 216 Exemplary configurations of suitable branch prediction mechanisms are well known
• Results produced by functional units 212 are sent to the reorder buffer 216 if a register value is being updated, and to the load/store unit 222 if the contents of a memory location is changed If the result is to be stored in a register, the reorder buffer 216 stores the result in the location reserved for the value of the register when the instruction was decoded As stated previously, results are also broadcast to reservation station units 210A-210F where pending instructions may be waiting for the results of previous instruction executions to obtain the required operand values
• load/store unit 222 provides an interface between functional units 212A-212F and data cache 224
• load/store unit 222 is configured with a load/store buffer with sixteen storage locations for data and address information for pending loads or stores
• Decode units 208 arbitrate for access to the load/store unit 222 When the buffer is full, a decode unit must wait until the load/store unit 222 has room for the pending load or store request information
• Functional units 212 provide the load/store instruction and associated address and data information to load/store unit 222
• Load/store unit 222 executes the load/store instructions by accessing data cache 224 and causing data cache 224 to fetch a line from mam memory when a non-speculative load/store instruction misses the cache Load/store unit 222 returns the requested data for load instructions to reorder buffer 216 as well as any reservation stations 210 that may be waiting for the data Store data is stored into data cache 224 by load/store unit 222
• the load/store unit 222 also performs dependency
• Data cache 224 is a high speed cache memory provided to temporarily store data being transferred between load/store unit 222 and the main memory subsystem
• data cache 224 has a capacity of storing up to thirty-two kilobytes of data in an eight way set associative structure with thirty-two byte lines It is understood that data cache 224 may be implemented in a variety of specific memory configurations, including a set associative configuration
• Load/store unit 222 has an input bus 250 coupled to functional units 212 for providing load/store instructions, address and data information Input bus 250 conveys information to a load/store buffer 251
• Load/store buffer 251 stores information pertaining to outstanding load and store instructions
• Request bus 253 conveys a load/store request to data cache 224 as selected by multiplexor circuit 254 under the control of output control circuit 255
• Returning from the data cache is a hit/way bus 256 which is coupled to load/store buffer 251
• load/store unit 222 receives hit/miss information and the way value of data cache 224 in which the hit is detected for requests conveyed on request bus 253
• Clear signal line 257 from reorder buffer 216 is coupled to control circuits related to load/store buffer 251
• load/store unit 222 selects a load or store memory request to convey to data cache 224 on request bus 253
• a "checked bit" in the associated buffer storage location will be set if the current request hits data cache 224 The checked bit remains set as long as the instruction is valid and the clear signal on clear signal line 257 is not asserted
• Load-op-store instructions are x86 instructions that use a memory location as both
• load/store buffer 251 is a linear array of storage locations containing a reorder buffer tag (indicated by the TAG field in Figure 2), a checked bit (the C field), and a way field (the W field) associated with load/store instructions
• load/store buffer 251 is configured with sixteen storage locations Other information is stored in each load/store buffer entry as will be described in more detail below Associated with each storage location is a block of logic circuits to update the checked bit each clock cycle
• Multiplexor 254 and output control unit 255 are used to select requests for access to data cache 224 in a given clock cycle In one embodiment, up to two requests are selected each clock cycle
• output control unit 255 implements a priority scheme for selecting operations from load/store buffer 251, in which store instructions that are no longer speculative and load instructions that are no longer speculative and have missed the data cache are given a high priority, and load instructions that are speculative are given a low priority
• multiplexor circuit 254 may be implemented as multiple multiplexor circuits which produce the requests transferred on request bus 253
• Request bus 253 conveys at least the address associated with the request, whether the request is a load or a store type request, and the way value, checked bit, and store data for store requests
• Data cache 224 is configured to store data into the cache line indexed by the request address and selected by the associated way value if the checked bit is set If the checked bit is not set, data cache 224 reads the indexed lines of the cache to check for a cache hit for the
• load/store buffer 251 may vary in number of entries from embodiment to embodiment Furthermore, load/store buffer 251 may be configured as a separate load buffer and store buffer, in which the load buffer stores all load instructions and the store buffer stores all store instructions It is further noted that more than one request may be transferred per clock cycle on request bus 253
• the addresses accessing data cache 224 are compared to the addresses stored with load/store buffer 251
• This embodiment is more general than the previous embodiment in that the store instructions that may eliminate the two cycle access need not be the store portion of a load-op-store instruction
• the locking of the cache is more complicated
• the lock bit associated with an accessed cache line would need to be set if a checked bit is set due to the cache access, instead of locking based on the fact that the load is a part of a load-op-store instruction
• This embodiment would generally lock the cache line in a clock cycle subsequent to the clock cycle in which the access occurs
• FIG. 3 a diagram of the bit fields in a load/store buffer storage location is shown for one embodiment of load/store buffer 251
• Field 300 includes the reorder buffer tag for the storage location as well as a valid bit indicating when set that the storage location is currently storing a valid load or store instruction
• Field 301 stores the address associated with the load or store instruction, as provided by functional units 212
• a valid bit is also included in field 301 indicating when set that the address is valid
• Output control unit 255 does not select a load/store instruction for access to data cache 224 until the address valid bit is set
• Field 302 stores the data associated with store instructions, as well as a valid bit indicating when set that the data field is valid
• Bit 303 is the checked bit discussed above, and field 304 is the way field discussed above
• Bit 305 is a bit used for load instructions which indicates when set that the load instruction is the load portion of a load-op-store instruction This bit is used to determine whether or not to set the lock bit for an associated cache line,
• the tag entry is configured with a state field 401 indicating the state of the associated cache line.
• state field 401 is two bits wide to encode an MESI state for the cache line.
• an MESI state encodes a modified or "dirty" state in which the cache line has been modified with respect to the contents stored at the associated address in main memory and therefore the cache line must be written back to main memory when removed from data cache 224; an exclusive state in which the cache line is stored in data cache 224 and no other copies of the cache line exist in other superscalar microprocessors configured into a system with superscalar microprocessor 200; a shared state in which the cache line is stored in data cache 224 and other copies of the cache line may be stored in other superscalar microprocessors configured into a system with superscalar microprocessor 200; and an invalid state indicating the associated cache line is not valid and the bytes stored therein should not be used.
• Field 402 of the tag entry contains the tag of the entry.
• a tag is the portion of the address which uniquely identifies which bytes from main memory are stored in the cache line.
• field 402 is 20 bits wide and contains the 20 highest order bits of the address associated with the bytes stored in the cache line.
• Bit 403 is the aforementioned lock bit. If bit 403 is set, then the associated cache line may not be removed from data cache 224 when a new cache line is fetched from main memory. Instead, another cache line within the row must be removed. Lock bit 403 is set when a load instruction with its corresponding load-op-store bit set accesses the associated cache line and is found to hit.
• Lock bit 403 is cleared when a store instruction is executed to the associated cache line, or when the clear signal conveyed on clear signal line 257 is asserted from reorder buffer 216 (as will be discussed in more detail below).
• a scenario requiring special attention is the case where the load portion of a load-op-store instruction accesses a cache line in which the lock bit is already set.
• the lock bit being set indicates that a previous load-op-store instruction has accessed the cache line with its load portion but the store portion has not executed yet.
• the store portion of the previous load-op-store instruction stores into the cache line, it will clear the lock bit, as noted above. Therefore, the lock bit will be cleared before the store portion of the current load-op-store instruction accesses data cache 224, and the associated line may be removed from the cache.
• Dependency checking within load/store unit 222 prevents the load portion from accessing the cache (as will be described in more detail below with respect to Figures 5-70).
• the load data is provided by the load/store buffer 251.
• the checked bit is not set for the associated store portion. Therefore, the store portion of the load-op-store instruction will require two data cache accesses to complete for this scenario.
• the checked bit for the associated store portion is set, and a bit is set for the store instruction providing the data for the load portion indicating that it should not reset the lock bit when it accesses data cache 224. In this embodiment, both stores complete in a single access to the cache.
• FIG. 4B a block diagram of a data cache tag array 404 associated with data cache 224 is shown.
• data cache 224 is eight way set associative and so each row of data cache tag array 404 contains eight entries of the type shown in Figure 4
• a Cache tag array 404 is also coupled to clear signal line 257 such that during a clock cycle in which the clear signal is asserted, each lock bit within data cache tag array 404 is cleared
• the clear signal allows lock bits to be cleared when reorder buffer 216 detects that a load-op-store instruction is cancelled Exemplary cancellation reasons include a branch misprediction for a branch instruction prior to the load-op-store instruction and an exception associated with an instruction prior to the load-op-store instruction Such cancellations may occur in a clock cycle between the execution of the load portion of a load-op-store instruction and the store portion of the instruction If a lock bit which was set by a load-op-store instruction that was later cancelled is not cleared then the line would remain in data cache 224 indefinite
• data cache tag array 404 may be implemented as part of the data cache array 224 which stores the data bytes, or may be implemented as a physically separate array
• the associativity of data cache 224 may vary from embodiment to embodiment In a direct-mapped embodiment of data cache 224, the way field in the storage locations of load/store buffer 25 1 may not be used
• a load/store unit and a data cache for a superscalar microprocessor have been described
• the combination of the load/store unit and the data cache allow for the store portion of load-op-store instructions to be executed in a single clock cycle of access to the data cache, as opposed to the two clock cycles typically used by stores to search for the associated cache line and store the data, respectively Therefore, higher performance may be achieved through the removal of a data cache access cycle from most load-op-store instructions

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