EP0978199A2 - Architecture compatible systemes mpeg-4 - Google Patents

Architecture compatible systemes mpeg-4

Info

Publication number
EP0978199A2
EP0978199A2 EP99900029A EP99900029A EP0978199A2 EP 0978199 A2 EP0978199 A2 EP 0978199A2 EP 99900029 A EP99900029 A EP 99900029A EP 99900029 A EP99900029 A EP 99900029A EP 0978199 A2 EP0978199 A2 EP 0978199A2
Authority
EP
European Patent Office
Prior art keywords
mpeg
operating system
architecture
buffer
packet data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99900029A
Other languages
German (de)
English (en)
Inventor
Philippe Gentric
Laurent Herrmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP99900029A priority Critical patent/EP0978199A2/fr
Publication of EP0978199A2 publication Critical patent/EP0978199A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Definitions

  • the present invention relates to an MPEG-4 Systems compliant architecture.
  • This invention has applications in relation with the MPEG-4 standard, for the streaming of MPEG-4 multimedia data.
  • MPEG-4 Systems The Systems part of the MPEG-4 standard defines the architecture to access MPEG-4 multimedia data (video, audio, 2D and 3D graphics).
  • MPEG-4 Systems is, more precisely, described in the following document "MPEG-4 Systems", ISO/TEC JTC1/3C29/WG11 N 1901, 21 November 1997.
  • Such an architecture is complex, since it provides access to an arbitrary number of streams, such as audio and video streams for instance, originated from a large number of sources (networks, broadcasting, storage,).
  • the standard specifies, for the synchronization of audio and video data, a mechanism allowing to introduce, by means of time-stamps, a temporal information into said different streams.
  • bitrate for instance, mobile networks, Internet.
  • bitrate variations occur (for Internet, depending on the time in the day ; for mobile networks, depending on the distance to the nearest base station).
  • MPEG-4 compliant architecture the topology of which has to be handled with respect to a so- called “configuration” that may be fixed but generally evolves dynamically during the session
  • an optimal architecture implementation has to ensure an appropriate buffer management.
  • the problems to be solved in this context then concern the exchange of information between the different modules of said architecture, in order to avoid drawbacks such as :
  • the invention relates to an architecture characterized in that it is subdivided into key modules, a specific task managed by a multi-threading operating system being assigned to each part of said architecture, and the strategy for the buffer management being optimally based on specific synchronization primitives provided by the multi-threading operating system.
  • An implementation of MPEG-4 Systems has to be able to instantiate dynamically the differents components of a configuration, whatever this one is very simple (for instance, a movie composed of an audio flow and a video flow) or very complex (for example, for an application of interactive multi-user virtual reality with teleconferencing).
  • the technical solution according to the invention that defines a generic architecture for every implementation of MPEG-4 Systems based on microprocessor(s) with a multi-threading operating system, is a reply to this problem.
  • the proposed architecture that uses basic primitives present in all multi-threading environments, is indeed modular, flexible, dynamic, extensible, and easy to implement and to manage.
  • multi-threading operating systems are optimized for the target processor and are built to be able to efficiently manage the synchronization of numerous tasks.
  • - Fig.l depicts an implementation of an MPEG-4 Systems buffer partitioning model (on the so-called Win32 operating system);
  • Fig.2 illustrates the control management with semaphores, used to keep the different threads efficient.
  • the proposed solution addresses the following issues.
  • key modules for an optimal buffer management are defined, which implies a specific generic partitioning of MPEG-4 Systems.
  • Each of these modules is then implemented as a task that is managed by a multi-threading operating system (with the use, in order to manage the filling of the buffers in an optimal way, of specific synchronization primitives provided by said multi -threading operating system).
  • the strategy for the buffer management is defined.
  • Fig.l TransMux, FlexMux, Elementary Stream.
  • a decoder buffer (audio, video,...) is also defined (and represented in Fig.l), in order to read Access Units (AUs) and produce frames that can be played (images, sounds), but this task is not part of the one carried out by the demultiplexer.
  • FMX FlexMux thread
  • DEC Decoder thread
  • AUs Access Units
  • FIFO First-In, First-Out
  • synchronization primitives which is done by means of semaphores (or : counters) that keep the different threads efficient.
  • Each of these semaphores controls each respective buffer (FM-PDU, AL-PDU, AU) in the demultiplexer.
  • For each decoder there is also one semaphore controlling the decoder buffer, and one more for signalling to the TransMux to have to stop if the AU buffer becomes too large.
  • the first operation is done by the TransMux TMX that reads data on the local disk DK or on the network NW ;
  • the regulation of the TransMux TMX is made by the AU feedback semaphore controlling that the AU buffer is not in a critical state.
  • the principle of this buffer management strategy is to keep the buffer sizes as small as possible. When the number of AL-PDUs is sufficient to reconstruct an AU, it has to be done immediately. Thus there is always data present for decoding.
  • TransMux Two types of TransMuxes can be differentiated : slow ones (network access), and fast ones (disk access).
  • the disk accesses are quick and stable in terms of latency, and, with such types of accesses, it is then not needed to store many data in the different buffers, since no loss would occur and the maximal critical value could be rather low.
  • network accesses can introduce some latency (Internet, for example), so that it is important to store more data in the buffers in order not to let the decoder starve. In the case of more than one decoder, it must however be indicated that the
  • TransMux has to be stopped only when all the AU buffers have reached the critical maximum value in order not to have starving decoding threads (it is therefore assumed that the multiplexing strategy has been adapted for that purpose on the sending side).

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

L'invention concerne une architecture compatible systèmes MPEG-4 rassemblant des modules clé chargés d'une tâche spécifique gérée par un système d'exploitation de traitement multitransactionnel. Le démultiplexeur MPEG-4 est segmenté en trois niveaux de traitement. Les différents traitements sont indépendants les uns des autres, mais des primitives de synchronisation sont prévues par le système d'exploitation, sous la forme de sémaphores commandant les mémoires tampon de manière que leurs tailles soient maintenues aussi petites que possible. Cette invention trouve des applications dans tout type d'équipement industriel MPEG-4 (bureau, coffrets d'abonné).
EP99900029A 1998-01-27 1999-01-14 Architecture compatible systemes mpeg-4 Withdrawn EP0978199A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP99900029A EP0978199A2 (fr) 1998-01-27 1999-01-14 Architecture compatible systemes mpeg-4

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP98400160 1998-01-27
EP98400160 1998-01-27
PCT/IB1999/000038 WO1999038329A2 (fr) 1998-01-27 1999-01-14 Architecture compatible systemes mpeg-4
EP99900029A EP0978199A2 (fr) 1998-01-27 1999-01-14 Architecture compatible systemes mpeg-4

Publications (1)

Publication Number Publication Date
EP0978199A2 true EP0978199A2 (fr) 2000-02-09

Family

ID=8235248

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99900029A Withdrawn EP0978199A2 (fr) 1998-01-27 1999-01-14 Architecture compatible systemes mpeg-4

Country Status (5)

Country Link
EP (1) EP0978199A2 (fr)
JP (1) JP2001518272A (fr)
KR (1) KR100639894B1 (fr)
CN (1) CN1150768C (fr)
WO (1) WO1999038329A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6606329B1 (en) 1998-07-17 2003-08-12 Koninklijke Philips Electronics N.V. Device for demultiplexing coded data

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668599A (en) * 1996-03-19 1997-09-16 International Business Machines Corporation Memory management for an MPEG2 compliant decoder
GB9704027D0 (en) * 1997-02-26 1997-04-16 Discovision Ass Memory manager for mpeg decoder
EP0909091A1 (fr) * 1997-10-07 1999-04-14 CANAL+ Société Anonyme Gestionnaire de mémoire

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9938329A2 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6606329B1 (en) 1998-07-17 2003-08-12 Koninklijke Philips Electronics N.V. Device for demultiplexing coded data

Also Published As

Publication number Publication date
WO1999038329A2 (fr) 1999-07-29
JP2001518272A (ja) 2001-10-09
KR100639894B1 (ko) 2006-10-31
KR20010005738A (ko) 2001-01-15
CN1150768C (zh) 2004-05-19
CN1256047A (zh) 2000-06-07
WO1999038329A3 (fr) 1999-09-30

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