EP0978042A2 - Verfahren zur übertragung eines betriebssystems in datenverarbeitungsanlagen - Google Patents

Verfahren zur übertragung eines betriebssystems in datenverarbeitungsanlagen

Info

Publication number
EP0978042A2
EP0978042A2 EP98931931A EP98931931A EP0978042A2 EP 0978042 A2 EP0978042 A2 EP 0978042A2 EP 98931931 A EP98931931 A EP 98931931A EP 98931931 A EP98931931 A EP 98931931A EP 0978042 A2 EP0978042 A2 EP 0978042A2
Authority
EP
European Patent Office
Prior art keywords
addresses
operating system
target hardware
reserved
hardware
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98931931A
Other languages
German (de)
English (en)
French (fr)
Inventor
Alfred Isele
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Technology Solutions GmbH
Original Assignee
Wincor Nixdorf International GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wincor Nixdorf International GmbH filed Critical Wincor Nixdorf International GmbH
Publication of EP0978042A2 publication Critical patent/EP0978042A2/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation

Definitions

  • the invention relates to a method for data processing systems for controlling the transmission of an operating system for original hardware that supports a real addressing mode to target hardware that processes only virtual addresses.
  • microprocessors in mainframe computer systems e.g. B. in IBM / 390 systems, differentiate in the addressing of the main memory between a "real" and a "virtual" addressing mode.
  • real mode the entire main memory available to the operating system can be addressed directly and independently of the process. This is e.g. B. required when booting the system, interrupt handling and communication with the input / output processors.
  • processors e.g. B. RISC processors R4000 from MIPS
  • memory addressing takes place at least in part via so-called “virtual” addresses which (usually with the aid of conversion tables) are mapped to physical memory addresses. This mapping is often dependent on the process currently running on the system.
  • FIG. 1 shows a schematic illustration to explain the address assignments and FIG. 2 shows an associated mapping diagram
  • FIG. 1 shows the schematic representation of the main memory HS1 of an original hardware Ml in the left part of the figure and the main memory HS2 of a target hardware M2 in the right part of the figure, PSA denoting the address space of the physical memory and DAR the superimposed real address space for the original hardware Ml.
  • the latter is also the start address of the operating system OS1 to be ported with the addresses EV1 for accepting exceptional conditions.
  • the address space for the operating system OSl extends to the address Bl-1, and the address Bl is z.
  • the start addresses EV2 for accepting the exception bindings at the beginning of the address space PSA for the physical memory are provided with a separate control Program GSP coupled, which forms a bridge to the porting operating system 0S2 so that it can react to the exceptional conditions of the M2 system.
  • the scope of the separate control program GSP depends, among other things, on the configuration of the target hardware M2, so that the start of the address space available to the operating system in physical memory cannot be determined from the outset.
  • FIG 2 illustrates this relationship.
  • the reserved address space RADR with real addressing is shown along the abscissa axis and the address space PSA for the physical memory along the ordinate axis.
  • the real address space corresponds to 0 to B2-A2 for the ported
  • Operating system OS2 with the physical address space A2 is B2. The same applies to the ported user program AWP2.
  • one of the virtual address spaces is reserved for the real addressing mode.
  • the currently valid address space identifier shows which addressing mode applies, and the control for address management and translation as well as for the reloading processes can react accordingly.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
EP98931931A 1997-04-23 1998-04-16 Verfahren zur übertragung eines betriebssystems in datenverarbeitungsanlagen Withdrawn EP0978042A2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19717102A DE19717102A1 (de) 1997-04-23 1997-04-23 Verfahren zur Übertragung eines Betriebssystems in Datenverarbeitungsanlagen
DE19717102 1997-04-23
PCT/DE1998/001071 WO1998048355A2 (de) 1997-04-23 1998-04-16 Verfahren zur übertragung eines betriebssystems in datenverarbeitungsanlagen

Publications (1)

Publication Number Publication Date
EP0978042A2 true EP0978042A2 (de) 2000-02-09

Family

ID=7827471

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98931931A Withdrawn EP0978042A2 (de) 1997-04-23 1998-04-16 Verfahren zur übertragung eines betriebssystems in datenverarbeitungsanlagen

Country Status (4)

Country Link
EP (1) EP0978042A2 (ja)
JP (1) JP2000513128A (ja)
DE (1) DE19717102A1 (ja)
WO (1) WO1998048355A2 (ja)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58102380A (ja) * 1981-12-11 1983-06-17 Hitachi Ltd 仮想記憶管理方法
US5038281A (en) * 1986-09-19 1991-08-06 International Business Machines Corporation Acceleration of system interrupts between operating systems in guest-host relationship
JP2510605B2 (ja) * 1987-07-24 1996-06-26 株式会社日立製作所 仮想計算機システム
JP2839201B2 (ja) * 1990-07-30 1998-12-16 株式会社日立製作所 仮想計算機システム
US5479631A (en) * 1992-11-19 1995-12-26 International Business Machines Corporation System for designating real main storage addresses in instructions while dynamic address translation is on
US5515525A (en) * 1993-09-28 1996-05-07 Bull Hn Information Systems Inc. Emulating the memory functions of a first system on a second system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9848355A2 *

Also Published As

Publication number Publication date
WO1998048355A2 (de) 1998-10-29
DE19717102A1 (de) 1998-10-29
WO1998048355A3 (de) 1999-01-28
JP2000513128A (ja) 2000-10-03

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