Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/90—Buffering arrangements
  • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L47/00—Traffic control in data switching networks
  • H04L47/50—Queue scheduling
  • H04L47/62—Queue scheduling characterised by scheduling criteria
  • H04L47/6215—Individual queue per QOS, rate or priority
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/90—Buffering arrangements
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/90—Buffering arrangements
  • H04L49/9057—Arrangements for supporting packet reassembly or resequencing
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/90—Buffering arrangements
  • H04L49/9084—Reactions to storage capacity overflow
  • H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
  • H04L49/9094—Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
  • H04L69/12—Protocol engines

Definitions

• the present invention relates generally to integrated circuit devices used for processing data through communication networks, and more particularly, to methods and apparatuses for high speed packet processing within the media access control level to reduce host central processing unit processing loads.
• the Ethernet local area network is one of the most popular and widely used computer networks in the world. Since the Ethernet's beginnings in the early 1970's, computer networking companies and engineering professionals have continually worked to improve Ethernet product versatility, reliability and transmission speeds. To ensure that new Ethernet products were compatible, interoperable and reliable, the Institute of Electrical and Electronic Engineers (LEEE) formed a standards group to define and promote industry LAN standards. Today, the LEEE 802.3 standards group is responsible for standardizing the development of new Ethernet protocols and products under an internationally well known LAN standard called the "LEEE 802.3 standard.”
• Ethernet products used for receiving, processing and transmitting data over Ethernet networks.
• these networking products are typically integrated into networked computers, network interface cards (NICs), SNMP/RMON probes, routers, switching hubs, bridges and repeaters.
• NICs network interface cards
• SNMP/RMON probes routers
• switching hubs switching hubs
• bridges bridges and repeaters.
• common data transmission speeds over Ethernet networks were 10 mega bits per second (Mbps).
• Mbps mega bits per second
• LEEE 802.3 standards committee officially introduced the "IEEE 802.3u standard” in May of 1995. This standard is also referred to as the "100 BASE T Fast Ethernet” standard because of its ability to perform data transmissions up to about 100 Mbps.
• FIG. IA is a diagrammatic representation of an open systems interconnection (OSI) layered model 10 developed by the International Organization for Standards (ISO) for describing the exchange of information between layers.
• the OSI layered model 10 is particularly useful for separating the technological functions of each layer, and thereby facilitating the modification or update of a given layer without detrimentally impacting on the functions of neighboring layers.
• the OSI model 10 has a physical layer 12 that is responsible for encoding and decoding data into signals that are transmitted across a particular medium .
• physical layer 12 is also known as the "PHY layer.”
• a data link layer 14 is defined for providing reliable transmission of data over a network while performing appropriate interfacing with physical layer 12 and a network layer 16.
• data link layer 14 generally includes a logical link layer (LLC) 14a and a media access control layer (MAC) 14b.
• LLC layer 14a is generally a software function that is responsible for attaching control information to the data being transmitted from network layer 16 to MAC layer 14b.
• MAC layer 14b is responsible for scheduling, transmitting and receiving data over a link.
• MAC layer 14b is primarily responsible for controlling the flow of data over a network, ensuring that transmission errors are detected, and ensuring that transmissions are appropriately synchronized.
• MAC layer 14b generally schedules and controls the access of data to physical layer 12 using a well known carrier sense multiple access with collision detection (CSMA/CD) algorithm.
• CSMA/CD carrier sense multiple access with collision detection
• Network layer 16 is responsible for routing data between nodes in a network, and for initiating, maintaining and terminating a communication link between users connected to the nodes.
• Transport layer 18 is responsible for performing data transfers within a particular level of service quality.
• a typical software protocol used for performing transport layer 18 functions may be TCP/IP, Novell IPX and NetBeui.
• Session layer 20 is generally concerned with controlling when users are able to transmit and receive data depending on whether the user is capable of full-duplex or half-duplex transmission, and also co-ordinates between user applications needing access to the network.
• Presentation layer 22 is responsible for translating, converting, compressing and decompressing data being transmitted across a medium. As an example, presentation layer 22 functions are typically performed by computer operating systems like Unix, DOS, Microsoft Windows 95, Windows NT and Macintosh OS.
• Application layer 24 provides users with suitable interfaces for accessing and connecting to a network.
• FIG. IB is a diagrammatic representation of typical Ethernet packets used for transferring data across a network.
• a packet generally includes a preamble 30 which is 8 bytes long. The last byte (or octet) in the preamble is a start frame delimiter (not shown). After the start frame delimiter octet, a destination address (DA) 32 which is 6 bytes is used to identify the node that is to receive the Ethernet packet. Following DA 32, is a source address (SA) 34 which is 6 bytes long, SA 34 is used to identify the transmitting node directly on the transmitted packet. After the SA 34, a length/type field (L/T) 36 (typically 2 bytes) is generally used to indicate the length and type of the data field that follows. As is well known in the art, if a length is provided, the packet is classified as an 802.3 packet, and if the type field is provided, the packet is classified as an Ethernet packet.
• L/T length/type field
• the following data field is identified as LLC data 38 since the data field also includes information that may have been encoded by the LLC layer 14a.
• a pad 40 is also shown following LLC data 38.
• a 4 byte cyclic redundancy check (CRC) field is appended to the end of a packet in order to check for corrupted packets at a receiving end.
• CRC cyclic redundancy check
• MAC layer 14b is responsible for controlling the flow of data over a network
• MAC layer 14b is generally responsible for encapsulating received LLC data 38 with an appropriate preamble 30, DA 32, SA 34, L/T 36, Pad 40 and CRC 42.
• an inter-packet gap is shown identifying a time span between transmitted Ethernet packets.
• the IPG is a fixed value that is defined by the 802.3 standard, and imposed by a suitable MAC layer 14b.
• Ethernet network speeds are accelerated to gigabit levels, the host CPU will generally be required to spend more time processing packet data and less time performing other CPU processing tasks. As a result, the host CPU will tend to experience many more processing interrupts which may hamper packet transmission and receiving operations.
• the CPU when packet data is received by the MAC layer 14b from the lower physical layer 12, the CPU is conventionally required to scan through each and every bit of data in the order received to locate the byte location of headers and data that may be of interest to upper layer protocols. Once the CPU has laboriously searched the entire packet and ascertained the particular byte locations of interest in each packet, all of this information is made available to upper layers, such as the network layer 16, transport layer 18, session layer 20, presentation layer 22 or the application layer 24. Once these upper layers have the information they need regarding the received packet, these upper layers will be able to complete their assigned tasks.
• upper layers such as the network layer 16, transport layer 18, session layer 20, presentation layer 22 or the application layer 24.
• the host CPU In addition to the CPU processing performed during the receiving of packet data, the host CPU is also charged with the responsibility of analyzing each byte of an outgoing packet.
• the switch or router CPU when the host is a switch or a router, the switch or router CPU is generally responsible for managing routing tables, and analyzing flow congestion. In addition, the switch or router CPU is also responsible for building and aging routing tables in an effort to constantly update the status of each and every node in the network. Other host CPU tasks may include performing management tasks, replying to queries from management hosts, building RMON data bases, etc. Accordingly, when a network host is asked to transmit data at increased speeds, the host CPU will unfortunately be more prone to CPU interrupt related delays.
• the present invention fills these needs by providing methods and apparatuses for a media access controller having programmable micro-rise stream processors for processing receive and transmit data over a high speed network. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
• a method for processing packet data received from a physical layer is disclosed.
• the processing is performed in-line while streaming packets to an upper layer.
• the method includes loading an instruction set for custom programming the processing of packet data received from the physical layer. Determining a type of packet data received from the physical layer. Identifying a first word location in the packet data based on the contents of the instruction set. Examining the packet data received from the physical layer at the first identified word location.
• the method further includes storing an element indicative of information contained in the first identified word location into a data structure, and appending the data structure to the packet data before the packet is streamed to the upper layer.
• a method for processing packet data received from a lower layer includes receiving a packet from the lower layer, and examining packet data contained in the received packet at a first word location. Then, the methods stores an element indicative of information contained in the first word location into a data structure. The data structure is then appended to the received packet before the packet is streamed to the upper layer. The media access layer pre-processes the received packet in-line while streaming packets to an upper layer.
• a packet data processor for parsing received packet data inline with streaming the packet data to an upper layer.
• the packet data processor includes a memory configured to receive executable microcode defining a type of data structure to be built from the received packet data.
• a pipeline register stage having a plurality of registers for sequentially receiving and temporarily storing words of the received packet data and, each of the plurality of registers in the pipeline register stage are coupled to a pipeline multiplexor that is capable of reading a portion of the words that are temporarily stored in the pipeline register stage.
• the packet data processor further includes an analyzing computer that is configured to examine the received packet data output from the pipeline multiplexor, and store a element of the received packet data generated by the analyzing computer into a register file.
• the packet data processor includes an execution logic unit that is configured to receive the executable microcode from the memory. The execution logic unit is preferably designed to control the examination of the received packet by the analyzing computer.
• One particular advantage of the present invention is that host CPU interrupts are minimized because each transferred packet is pre-processed by a micro-rise processor that is programmed to build and appended custom data structures to each transferred packet.
• a micro-rise processor that is programmed to build and appended custom data structures to each transferred packet.
• the host CPU is off loaded from having to parse each and every byte of transferred packet data to locate the particular information that may of interest to a host CPU. It is important to realize that this processing is performed on-the-fly at line rate as packet data is streamed between layers, thereby reducing transmission delays that are typically attributed to host CPU interrupts.
• Figure IA is a diagrammatic representation of an open systems interconnection (OSI) layered model developed by the International Organization for Standards (ISO) for describing the exchange of information between layers.
• OSI open systems interconnection
• ISO International Organization for Standards
• Figure IB is a diagrammatic representation of an exemplary Ethernet packet that is conventionally used for transferring data across a network.
• Figure 2A is an architectural diagram of a flow based media access controller (MAC) for high speed transmissions in accordance with one embodiment of the present invention.
• MAC media access controller
• FIG. 2B is a more detailed architectural diagram of a receive micro-RISC stream processor in accordance with one embodiment of the present invention.
• FIG. 2C illustrates an alternative embodiment for the micro-RISC stream processor of Figure 2B in accordance with one embodiment of the present invention.
• Figure 3A is a high level block diagram illustrating the preferred interactions between a host CPU and the micro-RISC stream processor of Figures 2B and 2C in accordance with one embodiment of the present invention.
• Figure 3B is an architectural diagram of the preferred hardware units contained within the micro-RISC stream processor of Figures 2B and 2C in accordance with one embodiment of the present invention.
• Figure 4A is an overview flowchart diagram of the preferred processing steps performed within the micro-RISC stream processor of Figures 2B and 2C in accordance with one embodiment of the present invention.
• Figure 4B is a more detailed flowchart diagram illustrating the method steps performed in loading the desired software instructions set for programming the receiving of packet data in accordance with one embodiment of the present invention.
• Figure 4C is a more detailed flowchart diagram illustrating the method steps associated with examining a received packet in accordance with one embodiment of the present invention.
• Figure 4D is a more detailed flowchart describing the processing performed during a skip through the received packet data as described in Figure 4A in accordance with one embodiment of the present invention.
• Figures 5A through 5E show exemplary data structures which may be programmably created for packets being received by the micro-RISC stream processor of Figures 2B and 2C in accordance with one embodiment of the present invention.
• Figures 6A and 6B show a data structure for a packet F which has been programmed by a user to include a plurality of flags in accordance with one embodiment of the present invention.
• Figures 7 A and 7B show yet another type of data structure that may be defined by the user in accordance with one embodiment of the present invention.
• Figure 8 is a block diagram pictorially illustrating packet processing occurring in the flow based MAC of Figure 2A during a receive and a transmit operation in accordance with one embodiment of the present invention.
• Figure 9 illustrates a number of functionalities that may be performed within a transmit micro-RISC stream processor in accordance with one embodiment of the present invention.
• Figure 10 is a block diagram of an exemplary computer system for carrying out the processing according to the invention.
• An invention is described for a high speed media access control layer micro-Rise engine that is user programmable to process packet data in-line while streaming packets in or out of the media access control layer core. Also disclosed are methods for user programmable in-line processing (e.g., parsing) of receive and transmit packet data while performing high speed streaming of packet data in or out of the media access control layer.
• user programmable in-line processing e.g., parsing
• FIG 2A is an architectural diagram of a flow based media access controller (MAC) 150 for high speed transmissions in accordance with one embodiment of the present invention.
• MAC media access controller
• FIG. 2 is a parallel data and control processing architecture.
• the flow based MAC 150 interfaces with a network data system bus 101 where both data and control information are processed, and a management/control bus 102 where both control and management data are passed.
• control information may also be simultaneously passed through network data system bus 101.
• this type of parallel processing provides the ability to change the processing parameters within flow based MAC 150 at any given time (i.e., even while packet data is being processed).
• flow based MAC 150 control information may be simultaneously passed through network data system bus 101 to modify portions of the packet that has not yet been processed. Accordingly, the parallel processing nature of flow based MAC 150 is capable of passing appropriate control information to alter specific processing parameters even while data is currently being processed.
• network data BIC 104 may be any suitable interface controller such as a slave interface and a direct memory access (DMA) on-board interface.
• DMA direct memory access
• a first data/control path 144a and a second data control path 144b may be used to interconnect network data bus interface 101 to network data BIC 104 when high performance switching tasks are required of flow based MAC 150.
• first data/control path 144a may be used for performing transfers from the upper LLC layer to flow based MAC 150
• second data/control path 144b may be used for performing transfers from flow based MAC 150 to the upper LLC layer.
• a single bidirectional data/control path may be used by combining 144a and 144b to perform the aforementioned control and data transfers.
• FLFO Tx 106 acts as a buffer (e.g., RAM memory) for holding data that is being transmitted from the upper LLC layer through network data system bus 101.
• FLFO Tx 106 is preferably capable of storing a large number of packet data. This is a significant improvement over conventional packet FLFO structures that would typically be unable to accommodate greater storage requirements associated with increased throughputs produced by gigabit speed (e.g., + 1,000 Mbps) systems in accordance with one embodiment of the present invention.
• a network flow managing FLFO Tx controller 110 is implemented to manage the high speed flow of packets from FLFO Tx 106 into a micro-RISC stream processor 114a.
• network flow managing FLFO Tx controller 110 may be responsible for prioritizing the different types of data being transferred across a network, such as audio, video, graphics, etc. into a number of linked buffers contained within FIFO Tx 106.
• flow based MAC 150 is capable of having multiple simultaneous streams of data flowing through FIFO Tx 106 at one time. In one feature, when packets are being read out from FIFO Tx 106, any one particular packet may be skipped without reading the entire packet.
• a packet may be re-transmitted from FLFO Tx 106 by holding a given packet for a programmable time.
• a packet being written into FLFO Tx 106 may be flushed directly out of FIFO Tx 106 before being transmitted to micro-RISC stream processor 114a.
• control information may be embedded within packets buffered in FLFO Tx 106.
• the processing parameters may be modifiable in a pipe-lined packet-by-packet basis.
• the embedded control information may contain modifications to the processing parameters as well as identifying information to single out a particular packet for modification. It should be appreciated that having a smart network flow managing FLFO Tx controller 110 also facilities network management and associated testing protocols. Although few circumstances should require the processing parameters to be changed for each successive packet, it will be appreciated that the ability to modify the processing parameters for any given packet in a packet stream is a powerful feature.
• micro-RISC stream processor 114a is suited to performs various user programmable packet processing, parsing, filtering and encapsulation operations.
• micro-RISC stream processor 114a operates in an in-line manner for modifying data stream characteristics.
• micro-RISC stream processor 114a (as well as 114b for the receive side) operates on 32 bit-word portions at one time to efficiently process information along flow based MAC 150, while achieving giga-bit speed (and higher) performance.
• instructions are preferably triggered off of the byte stream.
• micro-RISC stream processor 114a is also suited to operate in various addressing modes such as, for example, relative byte count mode.
• micro-RISC stream processor 114a will preferably have a set of general purpose registers, data structure registers, and analyzing computer units.
• the analyzing computer units may include a CRC unit, a compressed hash data unit, an ALU unit, a programmable checksum generator, a CAM, and comparators.
• micro-RISC stream processor 114a is preferably capable of operating in a conditional, branch, and loop mode, which provides additional flexibility and improved performance.
• micro-RISC stream processor 114a processing instructions may include a number of inventive packet field manipulations. Exemplary manipulations may include: CUT, CLEAR, COPY, APPEND, INSERT, AND, OR, XOR, MOVE, JUMP for specialized header generation, separating data and headers, LP_CHKSUM checking and length calculation.
• the micro-RISC stream processors of the present invention include an encryption/decryption unit for selectively parsing packets flowing through the micro- RISC stream processors, and thereby providing a user the ability to selectively encrypt and decrypt packets on demand. In this manner, a user can select certain packets that may be sensitive, and thereby prevent forwarding of the packets in an un-protected state. Still further, a compression/decompression unit may be included to selectively increase flow rates over a network. Thus, the compression/decompression may be targeted for certain packets flowing through the micro-RISC stream processors based on the type of application stream (e.g., audio, video, data, etc.). This also enables the application of lossy or lossless compression standards.
• an encryption/decryption unit for selectively parsing packets flowing through the micro- RISC stream processors, and thereby providing a user the ability to selectively encrypt and decrypt packets on demand.
• a user can select certain packets that may be
• FIG. 2A shows a SUPERMAC Tx controller 118 which is preferably a state machine configured to process packets received from micro-RISC stream processor 114a and output the processed packets to a physical (PHY) medium 140.
• FIG 2A also shows a SUPERMAC management block 117 that is responsible for interfacing between transmitting SUPERMAC Tx controller 118 and a receiving SUPERMAC Rx controller 120.
• SUPERMAC management block 1 17 also interfaces with network flow managing FLFO Tx controller 110, a network flow managing FLFO Rx controller 112, and network data BIC 104.
• SUPERMAC management block 117 functions as an interface that receives flow control information, auto negotiation commands, physical management commands, and pause frame information (i.e., pause frames are used by a receiving unit to notify a transmitting unit to cease the transmission of data until a receiving buffer is free).
• SUPERMAC Tx controller 118 and SUPERMAC Rx controller
• a second micro-RISC stream processor 114c that is preferably contained within a parallel event processor (PEP) 124.
• PEP parallel event processor
• appropriate processing events occurring within SUPERMAC Tx controller 118 and SUPERMAC Rx controller 120 may be transferred to micro-RISC stream processor 114b.
• the processing events occurring within the SUPERMAC Rx and Tx controller may be stored within appropriate statistical counters 128 of PEP 124.
• micro-RISC stream processor 114b is coupled to micro-RISC stream processor 114c in order to monitor and keep track of events being processed in and out of flow based MAC 150.
• data is received into flow based MAC 150 through a physical (PHY) medium 141, and then passed to the Rx SUPERMAC controller 120.
• SUPERMAC Rx controller 120 is capable of passing received CRC fields or padding fields directly to micro-RISC stream processor 114b without performing a conventional stripping functions. When this happens, stripping functions may be performed by micro-RLSC stream processor 114b itself, before passing the received packet data to the upper LLC layer.
• SUPERMAC Rx controller 120 receives an a packet from physical medium 141, the packet is transferred to micro-RISC stream processor 1 14b for processing and then to a multi- packet queue FIFO Rx 108.
• events performed in SUPERMAC Rx controller 120, and micro-RISC stream processor 114b are both linked to micro-RISC stream processor 114c, which accounts for those events in statistical counters 128.
• network flow managing FLFO Rx controller 112 is capable of assigning a number to each of the packets received by FLFO Rx 108.
• a control signal may be transferred to FIFO Rx controller 112 requesting that a particular numbered packet stored in FLFO Rx 108 be transferred (i.e., to LLC layer or PEP 124 for management purposes).
• FIFO Rx controller 112 requesting that a particular numbered packet stored in FLFO Rx 108 be transferred (i.e., to LLC layer or PEP 124 for management purposes).
• data is transferred out of multi-packet queue FLFO Rx 108 and into network data BIC 104, in a switched environment, data is passed through data path 144b onto network data system bus 101.
• a single bi-directional data path may alternatively be used in place of paths 144a and 144b.
• the same packet stream passing to FLFO Rx 108 from the micro- RISC stream processor 114b may be simultaneously passed in full duplex mode to the management side micro-RISC stream processor 114c (i.e., port mirroring). In this manner, management tasks may be performed on received packet stream within the PEP 124 while data is transferred to the upper layers.
• streaming BIC 122 is preferably implemented for passing control information and performing data management tasks.
• it may be necessary to pull (i.e., filter) a particular packet of information from the path of packets being processed through network data BIC 104. Once the desired packet is identified, it may then be filtered by micro-RISC stream processor 114c that lies within parallel event processor (PEP) 124.
• PEP parallel event processor
• Micro-RISC stream processor 114c is also preferably responsible for programming new events, filtering desired packets and buffering the desired packets in suitable buffers. Further, micro-RISC stream processor 114c is also capable of initiating programmable thresholding, alarm generation, SNMP/RMON packet transmission, generating test frames, and detection of flows for matrix statistics generation. In addition, a basic set of hardwired counters may also be provided to account for various processing operations performed by micro-RISC stream processor 114c.
• network management operations are generally used for determining selected network statistics such as throughput, utilization, number of collisions, traffic flow characteristics, etc.
• simple network management protocols SNMP
• RMON remote monitoring
• PEP 124 of Figure 2 PEP 124 of Figure 2.
• RMON monitoring allows a network manager to analyze various traffic statistics and network parameters for comprehensive network fault diagnostics, planning and performance tuning.
• PEP 124 includes an inventive packet buffer 125 for storing appropriate packets that are implemented by the network management protocols such as SNMP and RMON.
• the network management protocols such as SNMP and RMON.
• the micro-RISC stream processors 1 14b and 114c will filter out the desired packets that are subsequently stored in packet buffer 125.
• command and status registers 126 are also included within PEP 124, such that the command registers receive associated control signals from management/control bus 102 through streaming control BIC 122.
• 114b and 114c may be the same processing entity.
• statistical counters 128 that are responsible for storing particular events that may be occurring within SUPERMAC Tx controller 118, SUPERMAC management block 1 17, SUPERMAC Rx controller 120, micro-RISC stream processor 114a, and micro-RISC stream processor 114b. Accordingly, as packets are processed and events occur, the event information is streamed into micro-RISC stream processor 114c and then stored in statistical counters 128. Further, a plurality of programmable counters 130 are provided within PEP 124 for keeping track of new events (i.e., programmable events) that may be undefined at present time, but may be defined at a future date.
• the new events may be generated by the micro code that a user programs in the micro-RISC 114a, 114b, and 114c.
• Figure 2B is a more detailed architectural diagram of micro-RISC stream processor 114b that is specifically implemented for receiving packet data from SUPERMAC controller Rx 120 in accordance with one embodiment of the present invention.
• packet data is initially introduced into flow based media access controller 150 from physical medium 141, and once user defined processing is performed in micro-RISC stream processor 114b, the processed packet data is transferred to multi-packet FIFO Rx 108, which is in communication with FIFO Rx controller 112.
• the processed packet is preferably sorted into a plurality of varying priority buffers contained within multi-packet queue FLFO Rx 108. In this manner, if a particular packet contains time sensitive data, that packet will be placed into a higher priority buffer, and other data that is less time sensitive will be placed in other buffers of varying priorities.
• FIFO Rx controller 112 may be well suited to monitor the traffic intensity being handled by the host CPU.
• FIFO Rx controller 112 determines that a period of high traffic is being experienced by the host CPU (e.g., a server)
• the received packets will be temporarily stored in FLFO Rx 108, and then transferred all at once to the upper layers to reduce the number of interrupts experienced by the host CPU.
• micro-RISC stream processor 114b is a user programmable in-line packet processing engine that is capable of rapidly parsing through received packet data to build user defined data structures that may be appended to the beginning of the received packet before being transferred to multi-packet queue FIFO Rx 108.
• the user may configure a software instruction set designating the type of parsing to be performed on in-coming packet data, as well as the type of data structure to build and append to respective packets through the use of a graphical user interface (GUI).
• GUI graphical user interface
• packet data processing occurring in micro-RISC stream processor 114b rapidly generates the user defined data structures in an in-line manner (i.e., without slowing down data transfer rates) to advantageously append the defined data structures to the packets being streamed to upper layers.
• the upper layers need not scan the entire packet byte-by- byte (or bit-by-bit) tying up CPU bandwidth to identify packet data of interest.
• the user defined data structure may be programmed to store pointers to portions within the packet data that may be of interest to upper layer protocols, or portions of data (hashed or compressed data) that may be quickly read and processed without having to spend CPU bandwidth to scan and process the entire packet.
• the upper layers may rapidly stream the packet data to its intended destination (e.g., a switch, a router, a client, a server, etc.).
• the data structure information may be provided to the host in the form of a "status/descriptor" that is then processed by the host packet processing software.
• micro-RISC stream processor 114b may program micro-RISC stream processor 114b to generate custom data structures containing, for example, a pointer to the start of an internet protocol (IP) header, a pointer to the start of a transmission control protocol (TCP) header, and a pointer to the start of a simple mail transfer protocol (SMTP) header.
• IP internet protocol
• TCP transmission control protocol
• SMTP simple mail transfer protocol
• Other exemplary data structures may be programmed to include portions of the packet data itself such as an IP destinations address and compressed hashed data. Because the type of data structure and the content of the data structures are fully programmable by the user, other exemplary data structures may include "flag" data structures where each bit is programmed to identify one protocol or another, or "field" data structures where multiple bits are coded to identify different networking protocols.
• FIG. 2C illustrates an alternative embodiment for micro-RISC stream processor 114b in accordance with one embodiment of the present invention.
• the hardware logic components of micro-RISC stream processor 114b are divided into a first section (PART I) and a second section (PART II).
• PART I first section
• PART II second section
• the structural separation provides a built-in "delay" to facilitate processing, such as, packet header modifications, and protocol translation processing.
• packet header modification may include packet fragmentation and transformation to convert standard Ethernet packets into an asynchronous transfer mode (ATM) cells.
• Other packet translation functionalities may include translational bridging between Ethernet, Token Ring and FDDI.
• the split structure also allows a user to program micro-RISC stream processor 114b to perform a checksum operation after being output from the multi-packet queue FLFO Rx 108.
• micro-RISC stream processor 114b is a flexible processing unit that may be custom programmed to process in-coming packets in a user defined manner
• the split structure of micro-RISC stream processor 114b may be used to perform a number of other user defined tasks that may inherently require internal delays. It should be understood that these minor internal delays in no way slow down the high speed (e.g., gigabit or higher) data transfer rates of flow based MAC 150. On contrary, the internal delays provided by the split structure of Figure 2C only enhance the processing and data transfer rates by off-loading a host's CPU from having to examine substantial portions of the received packets.
• the split architecture of the micro-RISC stream processor may also be implemented in the transmit side for micro-RISC stream processor 114a.
• FIG. 3A is a high level block diagram illustrating the preferred interactions between a host CPU 300 and micro-RISC stream processor 114b in accordance with one embodiment of the present invention.
• the user is preferably directed to define a software instruction set identifying the type of data structure to build, as well as the content of the data structures.
• the user preferably implements a graphical user interface (GUI) 300 that provides a list of choices for ease of programming.
• GUI graphical user interface
• the GUI 300 generates a software instruction set that is compiled by a CPU 300.
• the compiled software instruction set is then converted into executable microcode.
• the microcode will preferably contain all of the user programmed information identifying the type of data structure to build, and the content of each data structure that will be appended to each packet received by micro-RISC stream processor 114b.
• a protocol descriptive language may be used to define a class of protocols using a set of predefined mnemonics with well understood semantics.
• Example mnemonics may include IP v.4 address, protocol LD, 802.3, and SNAP-encapsulation.
• a PDL compiler program can then generate the micocode for the Micro-RISC stream processor.
• microcode for carrying out the processing within micro-RISC stream processor 114b has been executed by the CPU 300
• the microcode is transferred to a bus (e.g., 101/102), and then to a bus interface controller (e.g., 104/122) as shown in Figure 2A above.
• the bus interface controller then transfers the microcode to hardware storage locations within micro-RISC stream processor 114b.
• the packet data may be simultaneously (i.e., mirrored) or independently transferred through both or one of the network bus 101 and management bus 102.
• a portion of the microcode is transferred into a random access memory (RAM) 302
• a portion of the microcode is transferred into a content addressed memory (CAM) 334
• a portion of the microcode is transferred into comparators 336.
• RAM 302, CAM 334 and comparators 336 have received the user programmed microcode, the micro-RISC stream processor 114b will be initialized and ready to receive packet data from SUPERMAC controller Rx 120 as described above.
• RAM 302 is preferably a thirty-two bit wide (or wider) by 256 deep static RAM, which contains an input register on the address input. Accordingly, when an address enable is high, the input register latches the address.
• any other suitable storage device may be implemented, including a read only memory having pre-programmed microcode instructions or an FPGA.
• CAM 334 preferably includes a set of sixteen 16-bit registers with equality comparators. In this manner, data to be compared is latched into a register having an output that goes to each of the equality comparators, and flags from the comparator are added together to produce a match signal (matchfound).
• FIG. 3B is an architectural diagram of the preferred hardware units contained within micro-RISC stream processor 114b in accordance with one embodiment of the present invention. Assuming that, RAM 302, CAM 334, and comparators 336 have already received the user- defined microcode from CPU 301 as described in Figure 3 A, an initial portion of the microcode contained within RAM 302 is transferred to an instruction register 304. Further, the transferred microcode will preferably contain microcode information to set a word count 308. In this embodiment, the microcode that is resident in word count 308 is configured to identify a desired word count in an in-coming packet.
• pipeline register stages 323 preferably includes a "stage 1" 324, a "stage 2" 326, and a "stage 3" 328 that provides powerful processing capabilities.
• stage 1 324 contains the 57th word
• stage 2 326 will contain the 56th word
• stage 3 328 will contain the 55th word
• a MUX 320 may select portions of the 55th, 56th and 57th word to process at one time.
• a summing unit 305 is preferably configured to continuously receive the current word count number from word counter 307, which notifies word count 308 that it is time to transfer the microcode to the execution instruction register 306.
• execution logic 312 which controls the current action of the micro-RISC stream processor 114b.
• execution logic 312 communicates with a MUX 320, a MUX 318, a MUX 314, a CRC unit 330, a HASH 331, an arithmetic logic unit (ALU) 332, CAM 334, comparators 336, and a programmable checksum generator 333.
• ALU arithmetic logic unit
• CRC 330, HASH 331, ALU 332, CAM 334, comparators 336, and a programmable checksum generator 333 are part of an analyzing computer 337 that is configured to act on the word of interest (of a current packet) identified by word count 308.
• CRC 330 is preferably configured to perform a CRC calculation and strip the CRC field before the packet is transferred to the upper LLC layer.
• the CRC calculation is a 32 bit or 16 bit cyclic redundancy check using a generator polynomial.
• execution logic 312 Based on the execution commands provided by execution logic 312, execution logic 312 instantaneously programs the analyzing computer 337 as well as MUX 320 that selects the identified word stored in stage 1 324, or a portion of the words stored in stage 2 326 and stage 3 328. That is, if portions of words are selected from each stage to construct a new 32-word, MUX 320 will select that new 32-bit word and transfer it to a bus 340. Once the desired word has been transferred to bus 340, the analyzing computer that includes CRC 330, HASH 331, ALU 332, CAM 334, comparators 336, and programmable checksum generator 333 operate on the 32-bit word selected by MUX 320.
• the word count will be transferred from word counter 307 to MUX 318 to be input into a current data structure.
• the current data structure will preferably be stored in a data structure register file 316. Once all of the data of interest for a current packet has been parsed and stored into the data structure register file 316, the data structure will be appended to the beginning of the packet data being output from MUX 314.
• the hashed data will be processed in HASH 331 and then passed to MUX 318.
• the user may desire that portions (i.e., selected 32-bit words) of the received packet data be placed into the data structure for quick reference by upper layer protocols.
• the control information provided to encoder 317 is preferably used to set (i.e., through encoded set bits) the type of data structure the user wants to build, and the control information provided to the next address logic is used to identify the next address from the microcode stored in RAM 302.
• a branch operation or a move operation will be performed.
• the next address logic 310 will locate another address location in RAM 302.
• one of the analyzing computer 337 units will transfer an output to MUX 318 and into data structure register file 316.
• the next address logic 310 contains logic for performing a vectored branch which identifies the next address in the microcode stored in RAM 302 based on the results obtained from the comparator's look up table contained within CAM 334. Further, conditional branching may be used to identify the next address from the microcode itself stored in RAM 302, based on outputs from comparators 337. Still further, Un-conditional branch instructions may come directly from the microcode stored in RAM 302 without analyzing the comparison results generated in CAM 334.
• next address logic 310 will ascertain the next address location in the microcode stored in RAM 302 based on information provided from the execution instruction register 306 and the received comparison results received from CAM 334 and comparators 336. Meanwhile, each time a new address is located in RAM 302, that address is stored in a program counter (PC) 311. In this embodiment, the program counter PC 311 will keep track of the most recent address selected in RAM 302. Accordingly, program counter (PC) 311 is continually updated after each access operation into RAM 302.
• word count 308 will contain the next word count of interest within the current packet being received.
• the next exemplary word of interest may be word 88.
• word 88 may identify the beginning of a header, the beginning of data to be compressed (e.g., hashed) or the beginning of data to be captured.
• word counter 307 reaches the 88th word in the packet, the microcode stored in instruction register 304 is shifted into execution register 306 to enable the executing on the newly received data word that is currently stored in stage 1 324 of the pipeline register stage 323.
• execution instruction register the contents of execution instruction register are transferred to execution logic 312 for programming the computation functions of the analyzing computer 337, and multiplexors 320, 314, and 318.
• the data structure being built is preferably stored in data structure register file 316 before being passed to MUX 318.
• register file 316 Once the entire data structure for a particular packet is stored in register file 316 (i.e., after all of the positions within a current packet have been examined), the actual packet data that was being passed through pipeline register stages 323 is temporarily stored in a RAM FIFO 322.
• execution logic 312 the user programmed data structure is passed into MUX 314 where it is appended to the beginning of the packet data being received from RAM FLFO 322.
• MUX 314 then outputs the packet and appended data structure to the multi-packet queue FLFO 108 as described above with reference to Figures 2A-2C.
• the next packet is again analyzed based on the same microcode provided by the user.
• the user wants to modify the processing set in the software instruction set input through GUI 300 of Figure 3A, the received packets will be processed in accordance with those new parameters.
• the data structures created for each packet may include only pointers to selected locations in the packet, only portions of data from the packet itself, only hashed data from the packet itself, or a combination thereof. Accordingly, micro-RISC stream processor 114b will operate on different packets in accordance with the specific microcode programmed by the user.
• each packet may have similar header information (i.e., the LP header) located in different byte locations within a received packet, and therefore, a host's CPU is typically required to laboriously scan through most of the contents of each packet before it can perform any necessary routing or processing. Accordingly, by appending a user defined data structure to the front of a received packet, even greater than gigabit Ethernet transmission speeds may be attained with substantially fewer CPU interrupts.
• FIG. 4A is an overview flowchart diagram of the preferred processing steps performed within micro-RISC stream processor 114b in accordance with one embodiment of the present invention.
• the method begins at a step 402 where a user defined software instruction set is loaded into micro-RISC stream processor 114b for programming the processing performed on packet data being received from SUPERMAC controller Rx 120.
• the software instruction set is preferably programmed into a host receiving computer through the use of a graphical user interface (GUI) which prompts the user to define the desired processing on the received packets.
• GUI graphical user interface
• the software instructions set is compiled.
• the software instructions set is compiled into executable microcode which is then loaded into the RAM 302, CAM 334 and Comparators 336 as described with references to Figure 3B above.
• such packets may include proprietary tagged packets, or any other type of packet that may be defined in the future.
• the initial skip is ascertained from the MAC layer protocol. Therefore, for Ethernet, the initial skip may have a skipping length of about 12 bytes.
• other protocols such as, for example, Token Ring or FDDI, other initial skipping lengths may be implemented as well.
• the method will proceed to a step 406 where the received packet is examined by an analyzing computer contained in the micro-RISC stream processor 114b in accordance with the user defined processing instructions provided in the user defined microcode.
• the packet is typically examined to ascertain the word count location of a particular header, or a particular piece of data.
• the analyzing computer computes the desired data to be appended to a data structure, the desired data is passed to a multiplexor.
• the method will proceed to step 408 where the identified pointer, data, or hashed data (or a combination thereof) is stored into the defined data structure.
• the method will then proceed to a decision step 410 where it is determined if there are any more positions of interest in the examined packet.
• the microcode determines that there are five separate headers locations of interest, then the method will proceed to a step 412 where micro-RISC stream processor 114a will skip to new position in the received packet in response to the examination of the received packet.
• the new skip location will preferably be the location ascertained by the microcode address selected by a next address logic unit contained within micro-RISC stream processor 114b.
• step 406 the received packet is again examined for the new word position identified in the microcode present in word count 308 of Figure 3B.
• step 408 the pointer, data, or hashed data is once again stored in the defined data structure being built in the aforementioned register file.
• decision step 410 it is determined if there are any more positions of interest in the examined packet. Assuming that there are more positions of interest in the examined packet, the method will again proceed through steps 412, 406, 408, and 410 until all positions of interest have been examined and stored in the data structure defined by the user.
• step 414 it is determined if there are any more packets being received from SUPERMAC controller Rx 120 as described with reference to Figures 2A-2C above. If there are more packets being received by SUPERMAC controller Rx 120, then the method will again proceed to step 404 where an initial skip is performed on the newly received packet. The method will again proceed through steps 406 and 408 where the user programmed data structures are built for the received packet. Of course, if the newly received packet is different from the previous packet, then the processing will be performed in accordance with the programming provided by the user for that new type of packet.
• micro-RISC stream processor 114b may be completely different than processing for another packet, even if the packets are received in sequential order. Therefore, the data stracture built for one packet will many times be different than the data structure built for another packet (e.g., flags, fields, pointers, hashed data, or combination thereof).
• Figure 4B is a more detailed flowchart diagram illustrating the method steps performed in loading the desired software instructions set for programming the receiving of packet data in accordance with one embodiment of the present invention.
• Figure 4B describes the preferred steps for initializing micro-RISC stream processor 114b for the receiving of packet data.
• the initialization begins at a step 420, where the desired type of data structure format to be built is programmed by the user into the software instructions set.
• the user will preferably program in the desired type of data stracture which may be, for example, a pointer data structure, a data stracture having portions of packet data, a data structure having hashed data (i.e., compressed), or a combination thereof.
• the resulting data structure is then appended to the front of a received packet.
• the data stracture may alternatively be appended to the back of the received packet. In some cases, this may be useful for processing the packet after the entire packet has been read by the upper layer host. As an example, checksum information may be appended to the back of the packet to verify the packet's integrity.
• micro-RISC stream processor 114b may be programmed in any form, such as, for example, through compiled executable microcode that may be transferred over a network. In this manner, the micro-RISC stream processor of remote hosts may be programmed from a remote server computer.
• the method will proceed to a step 422 where the desired instruction set programmed by the user is compiled to create compiled microcode.
• the compiled microcode will include the binary information needed by micro-RISC stream processor 114b to process the in-coming packets before they are transferred to multi packet queue FLFO Rx 108.
• micro-RISC stream processor 114b preferably contains a random access memory (RAM), a content addressed memory (CAM) and comparators that are suited to receive a portion of the compiled microcode for processing packets received by the micro-RISC stream processor 114b.
• RAM random access memory
• CAM content addressed memory
• comparators that are suited to receive a portion of the compiled microcode for processing packets received by the micro-RISC stream processor 114b.
• the method then proceeds to a step 426 where the micro-RISC stream processor 114b is shifted into a "ready" state for receiving packet data.
• micro-RISC stream processor has been programmed and initialized to perform the user defined processing on packets that will be received by micro-RISC stream processor 114b. As such, only those data structures defined by the user will be built during the receiving of packets until a modification is made to the microcode transferred to the hardware contained within micro-RISC stream processor 114b.
• FIG. 4C is a more detailed flow chart diagram illustrating the method steps associated with examining a received packet in accordance with one embodiment of the present invention.
• the packet examination begins at a step 440 where it is determined if the next 32-bit word of packet data is the desired word count data identified by the user programmed microcode. If the next 32-bit word of packet data is not the desired word count data, then the method will revert back to determine if the next 32-bit word of packet data is the desired word count data. When the desired word count data has been identified, the method will proceed to a step 442 where the desired 32-bit word of the packet data is loaded from a pipeline register stage to an analyzing computer contained within micro-RISC stream processor 114b.
• the analyzing computer preferably contains a CRC unit, a hash unit, an ALU unit, a CAM unit, comparators, an encryption/decryption unit, a compression/decompression unit, and a programmable checksum generator unit.
• the analyzing computer preferably receives data from a pipeline register stage and then acts upon that 32-bit word data based on control information provided by an execution logic unit. Once the desired 32-bit word has been loaded into the analyzing unit from the pipeline register stage in step 442, the method will proceed to a step 444 where the microcode contained in an execution instruction register is executed by the execution logic to control the processing for the current 32-bit word.
• step 446 comparison results derived in the analyzing computer are transferred to a next address logic unit.
• step 448 the next address in the microcode to be executed is identified.
• the next address in the microcode is transferred from the RAM to an instruction register in a step 450 where the microcode sits until a next microcode determined word count in the received packet arrives.
• the microcode contained in the instruction register is transferred to an execution instraction register.
• step 408 of Figure 4A where the pointer, data, or hash data is stored into the user defined data structure.
• the micro-RISC stream processor 114b will first ascertain the correct 32-bit word in the packet that is of interest, and then transfer microcode into an execution register to set the processing of the selected 32-bit word that is loaded from the pipeline register stage to the analyzing computer.
• the analyzing computer processes the selected 32-bit word, an entry is made into a user defined data stracture that temporarily stored in a data stracture register file. Once the data stracture is complete for a given packet being received, the data structure is appended to the leading end of the processed packet. It should be appreciated that all of the described data stracture generation is completed in-line while packets are being streamed out of the flow based MAC 150 of Figure 2A-2C.
• FIG. 4D is a more detailed flowchart describing the processing performed during a skip through the received packet data performed in step 412 of Figure 4A in accordance with one embodiment of the present invention.
• the method begins at step 460 where a word count provided by the microcode provides the micro-RISC stream processor 114a with an amount of bytes to skip forward in the received packet.
• a word count provided by the microcode provides the micro-RISC stream processor 114a with an amount of bytes to skip forward in the received packet.
• the micro-RISC stream processor 114a will allow all 32- bit words received up to word 51 to pass before being directed by the execution logic to place a pointer into the data structure for the 52nd word.
• the method will proceed to a step 462 where the contents of an instraction register are moved into an execution instruction register which instructs the execution logic to process the received 32-bit word in accordance with the user defined settings.
• the execution instraction register receives the instruction register contents in step 462
• the method will proceed to step 406 of Figure 4A where the received packet is examined as described with reference to Figure 4C.
• Figures 5A through 5D show exemplary data structures which may be programmably created for packets being received by micro-RISC stream processor 114b in accordance with one embodiment of the present invention.
• a user may program a data stracture for a packet A to include a pointer to the start of an IP header, a pointer to the start of a TCP header, a pointer to the start of an SMTP header, a pointer to the start of an application header and a data portion.
• the data structure may include actual packet portions, such as, an IP source address, an IP destination address, a source and destination port number, and hashed data.
• Figure 5B shows a data structure for a packet B in which only pointers to specific portions of packet B are identified. As such, the user may have a pointer directed to the IP header, a TCP header, an SMTP header and so on.
• Figure 5C shows a data structure having only packet data portions, such as, an IP source address, an IP destination address and a source and destination port number without the inclusion of pointers or hash data.
• Figure 5D shows a data structure for a packet D that may be programmed to include only hashed data. As is well known in the art, hashed data refers to compression data, which is typically done to reduce processing loads on host CPUs.
• Figure 5E shows packets A through D having an associated data structure appended to the front of each packet in accordance with one embodiment of the present invention.
• a host CPU is no longer required to laboriously scan and search through substantially the whole packet in order to ascertain the location of headers, or data of interest.
• Figure 6A shows a data stracture for a packet F which has been programmed by a user to include a plurality of flags in accordance with one embodiment of the present invention.
• the flag data stracture is preferably composed of 32 bits which may be used to identify the type of packet or its associated layer protocol.
• the first flag may be used to determine whether the incoming packet is an IP or an internet packet exchange (IPX) protocol
• the second flag may be used to distinguish between a TCP or a user datagram protocol (UDP) protocol
• the third bit may be used to distinguish between a TELNET (i.e., TELNET is a TCP/IP application that enables a user to log in to a remote device) or an SMTP protocol.
• the last exemplary flag of the data structure may be used to determine if the packet is an ICMP (i.e., internet control message protocol) or not an ICMP packet.
• IPX internet packet exchange
• UDP user datagram protocol
• the host CPU will be free from having to laboriously analyze the in-coming packet to determine the location of specific portions of interest.
• the upper layers such as the application, presentation, session, and transport layers may simply rout the received packet without loading down the host CPU.
• the flag data structure defined by the user is subsequently appended by the micro-RISC stream processor to the front of packet F before it is passed to the upper LLC layer.
• Figures 7A and 7B show yet another type of data structure that may be defined by the user in accordance with one embodiment of the present invention.
• the data structure may include a plurality of bits grouped into multi-bit fields as shown in Figure 7A.
• field 1 may be a 2-bit field, which may be used to identify the packet as either an IP, IPX, an address resolution protocol (ARP), or a reverse address resolution protocol (RARP).
• field N may be a 3-bit field which may be used to identify the packet as a UDP, TCP, ICMP, RSVP, or an internet group management protocol (IGMP) packet.
• the field data structure constructed for a packet F may be any number of user defined bit field combinations. It should be understood that the above identified protocol combinations are merely exemplary in nature, and the field data structures may be user programmable to define any present or future protocol, as well as any user defined combination.
• micro-RISC stream processor 114a as shown in Figure 2A includes a number of advantageous packet data processing capabilities.
• micro- RISC stream processor 114a is preferably well suited to encapsulate out-going packets with various types of headers to improve packet switching, routing, or convert Ethernet packets into ATM cells. It is important to keep in mind that the transmitter micro-RISC stream processor 114a is also configured to process and parse the packet data in line with the streaming out of the packet data, thereby advantageously avoiding latencies in transmissions.
• FIG. 8 is a block diagram 800 pictorially illustrating packet processing occurring in flow based MAC 150 during a receive and a transmit operation in accordance with one embodiment of the present invention.
• the packet is preferably processed by parsing each 32-bit word in line with streaming packets to an upper layer (or lower layer).
• packet 802 is streamed out of micro-RISC stream processor 114b, including an appended index 804 which represents the user-defined data structure having either pointers, data, hash data, or a combination thereof.
• the appended index 804, and packet 802 is passed to a switch table lookup 806, which preferably analyzes the routing requirements by reading the information stored in the appended index 804 which includes the quality of service (QoS) associated with the received packet.
• QoS quality of service
• the packet data just received is an audio packet
• this packet may require a higher priority to avoid introducing noise or disruptive skipping delays.
• the packet is non-time sensitive data, the received packet will be given a lower priority which, is read from the appended index 804 by the switch table lookup 806. Because this information is conveniently located at the front of packet 802, switch table lookup 806 is able to rapidly ascertain the routing requirements, while employing substantially less host CPU processing (i.e., which may slow down transmission rates).
• packet 802 and appended index 804 is passed into micro-RISC stream processor 114a where the packet data may be processed for transmission out to a remote host (i.e., switch, router, hub, etc.) through the physical layer 140, as shown in Figure 2A.
• the switch table lookup 806 may also append a command header 805 that enables micro-RISC stream processor 114a to determine what type of processing to perform on the packet 802. Once the micro-RISC stream processor 114a uses the command header 805 to create the desired encapsulation headers, the command header 805 will no longer be used.
• micro-RISC stream processor 114a is also well suited to attach an encapsulation header 808 at the front of appended index 804 and packet data 802.
• micro-RISC stream processor 114a may be programmed to calculate a new cyclic redundancy check (CRC), which may be appended to the back of packet 802 before being transmitted to the remote host.
• CRC cyclic redundancy check
• encapsulation header 808 may be a virtual local area network (VLAN) header, which is well known to assist networks in filtering traffic based upon complex schemes other than source and destination addresses.
• condition based filtering may also be performed by the micro-RISC stream processors.
• the VLAN header could empower a network to perform efficient routing based on Ethernet addresses, IP network numbers, or special VLAN designators.
• micro-RISC stream processor 114a may be configured to perform Cisco inter-switch link (ISL) tagging schemes via encapsulation header 808.
• ISL Cisco inter-switch link
• FIG. 9 illustrates a number of functionalities that may be performed within micro-RISC stream processor 114a in accordance with one embodiment of the present invention.
• micro-RISC stream processor 114a may be well suited to provide an encapsulation header 808a, which may be an ISL header used in well known Cisco tagging schemes.
• an original CRC 810a field may be calculated by micro-RISC stream processor 114a, and appended to out-going packets (in-line).
• an additional new CRC 811 which may be appended to the out-going packet in SuperMAC controller Tx 118 before being transmitted to the physical medium 140, as described above.
• micro-RISC stream processor 114a may be well suited to perform ATM cell fragmentation and reassembly tasks.
• DA destination address
• SA source address
• data 906 a fragmentation and reassemble operation may be performed on data 906, source address 904, and destination address 902.
• an ATM header 808b may be appended to the front of the ATM cell. Because ATM cells are generally of a fixed size, the remaining data that was not appended to the first out-going ATM cell, will be appended to the following ATM cell which is also assembled with its own ATM header 808b.
• micro-RISC stream processor 114b may be well suited for performing LP switching, wherein an IP header 910 is parsed and indexed with an IP index 912, which is appended to the front of the packet.
• micro-RISC stream processor 114a is preferably well suited to generate IP index 912 and compress it through a suitable hashing operation. Therefore, for IP switching, the index is a combination of the source and destination ports and the source and destination MAC addresses, and in some cases, parts of the IP header itself. In this manner, a small width index (12 bits for IP switching), may be used to tag all frames and to switch frames.
• micro-RISC stream processors of the described embodiments may also be useful in performing IP fragmentation and IP reassembly to reduce the load on a host's CPU.
• IP checksum functions may also be performed within the various embodiments of the micro-RISC stream processors described herein.
• LEEE 802.3 standard shall be understood to include all current LEEE 802.3 standards, including: (a) LEEE 802.3u standard (100 Mbps-Fast Ethernet)
• the present invention may be implemented using any type of integrated circuit logic or software driven computer-implemented operations.
• a hardware description language (HDL) based design and synthesis program may be used to design the silicon-level circuitry necessary to appropriately perform the data and control operations in accordance with one embodiment of the present invention.
• a VHDL® hardware description language based on standard available from LEEE of New York, New York may be used to design an appropriate silicon-level layout.
• another layout tool may include a hardware description language "Verilog®” tool available from Cadence Design Systems, Inc. of Santa Clara, California.
• the invention may also employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Further, the manipulations performed are often referred to in terms, such as producing, identifying, determining, or comparing.
• the invention also relates to a device or an apparatus for performing these operations.
• the apparatus may be specially constracted for the required purposes, or it may be a general purpose computer selectively activated or configured by a computer program stored in the computer.
• various general purpose machines may be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.
• An exemplary stracture for the invention is described below.
• FIG. 10 is a block diagram of an exemplary computer system 1000 for carrying out the processing according to the invention.
• the computer system 1000 includes a digital computer 1002, a display screen (or monitor) 1004, a printer 1006, a floppy disk drive 1008, a hard disk drive 1010, a network interface 1012, and a keyboard 1014.
• the digital computer 1002 includes a microprocessor 1016, a memory bus 1018, random access memory (RAM) 1020, read only memory (ROM) 1022, a peripheral bus 1024, and a keyboard controller 1026.
• RAM random access memory
• ROM read only memory
• the digital computer 1000 can be a personal computer (such as an LBM compatible personal computer, a Macintosh computer or Macintosh compatible computer), a workstation computer (such as a Sun Microsystems or Hewlett-Packard workstation), or some other type of computer.
• a personal computer such as an LBM compatible personal computer, a Macintosh computer or Macintosh compatible computer
• a workstation computer such as a Sun Microsystems or Hewlett-Packard workstation
• some other type of computer such as a Sun Microsystems or Hewlett-Packard workstation
• the microprocessor 1016 is a general purpose digital processor which controls the operation of the computer system 1000.
• the microprocessor 1016 can be a single-chip processor or can be implemented with multiple components. Using instructions retrieved from memory, the microprocessor 1016 controls the reception and manipulation of input data and the output and display of data on output devices. According to the invention, a particular function of microprocessor 1016 is to assist in the packet processing and network management tasks.
• the memory bus 1018 is used by the microprocessor 1016 to access the RAM 1020 and the ROM 1022.
• the RAM 1020 is used by the microprocessor 1016 as a general storage area and as scratch-pad memory, and can also be used to store input data and processed data.
• ROM 1022 can be used to store instractions or program code followed by the microprocessor
• the peripheral bus 1024 is used to access the input, output, and storage devices used by the digital computer 1002.
• these devices include the display screen 1004, the printer device 1006, the floppy disk drive 1008, the hard disk drive 1010, and the network interface 1012.
• the keyboard controller 1026 is used to receive input from keyboard 1014 and send decoded symbols for each pressed key to microprocessor 1016 over bus 1028.
• the display screen 1004 is an output device that displays images of data provided by the microprocessor 1016 via the peripheral bus 1024 or provided by other components in the computer system 1000.
• the printer device 1006 when operating as a printer provides an image on a sheet of paper or a similar surface.
• Other output devices such as a plotter, typesetter, etc. can be used in place of, or in addition to, the printer device 1006.
• the floppy disk drive 1008 and the hard disk drive 1010 can be used to store various types of data.
• the floppy disk drive 1008 facilitates transporting such data to other computer systems, and hard disk drive 1010 permits fast access to large amounts of stored data.
• the microprocessor 1016 together with an operating system operate to execute computer code and produce and use data.
• the computer code and data may reside on the RAM 1020, the ROM 1022, or the hard disk drive 1020.
• the computer code and data could also reside on a removable program medium and loaded or installed onto the computer system 1000 when needed.
• Removable program mediums include, for example, CD-ROM, PC-CARD, floppy disk and magnetic tape.
• the network interface 1012 is used to send and receive data over a network connected to other computer systems.
• An interface card or similar device and appropriate software implemented by the microprocessor 1016 can be used to connect the computer system 1000 to an existing network and transfer data according to standard protocols.
• the keyboard 1014 is used by a user to input commands and other instructions to the computer system 1000.
• Other types of user input devices can also be used in conjunction with the present invention.
• pointing devices such as a computer mouse, a track ball, a stylus, or a tablet can be used to manipulate a pointer on a screen of a general-purpose computer.
• the invention can also be embodied as computer readable code on a computer readable medium.
• the computer readable medium is any data storage device that can store data which can be thereafter be read by a computer system. Examples of the computer readable medium include read-only memory, random-access memory, CD-ROMs, magnetic tape, optical data storage devices.
• the computer readable medium can also be distributed over a network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.
• processing functions described above may be implemented both in silicon as hardware integrated circuits, packaged application specific integrated circuits (ASICs), or as software code (e.g., C and C++ programming code) that may be stored and retrieved from any suitable storage medium.
• storage mediums may include a disk drive, a hard drive, a floppy disk, a server computer, a remotely networked computer, etc.

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