TW495671B - Media access control micro-RISC stream processor and method for implementing the same - Google Patents

Media access control micro-RISC stream processor and method for implementing the same Download PDF

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Publication number
TW495671B
TW495671B TW087101838A TW87101838A TW495671B TW 495671 B TW495671 B TW 495671B TW 087101838 A TW087101838 A TW 087101838A TW 87101838 A TW87101838 A TW 87101838A TW 495671 B TW495671 B TW 495671B
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Taiwan
Prior art keywords
packet data
packet
data
received
scope
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TW087101838A
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Chinese (zh)
Inventor
Alak K Deb
Namakkal S Sambamurthy
William H Bares
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Xaqti Corp
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Priority claimed from US08/968,551 external-priority patent/US6172990B1/en
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Publication of TW495671B publication Critical patent/TW495671B/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Buffering arrangements
    • H04L49/901Buffering arrangements using storage descriptor, e.g. read or write pointers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/50Queue scheduling
    • H04L47/62Queue scheduling characterised by scheduling criteria
    • H04L47/6215Individual queue per QOS, rate or priority
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Buffering arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Buffering arrangements
    • H04L49/9057Arrangements for supporting packet reassembly or resequencing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Buffering arrangements
    • H04L49/9084Reactions to storage capacity overflow
    • H04L49/9089Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
    • H04L49/9094Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12Protocol engines

Abstract

Disclosed are methods and apparatus for processing packet data received from a physical layer. The processing is performed in-line while streaming packets to an upper layer. The method includes loading an instruction set for custom programming the processing of packet data received from the physical layer. Determining a type of packet data received from the physical layer. Identifying a first word location in the packet data based on the contents of the instruction set. Examining the packet data received from the physical layer at the first identified word location. The method further includes storing an element indicative of information contained in the first identified word location into a data structure, and appending the data structure to the packet data before the packet is streamed to the upper layer. The methods and apparatus also have direct applicability to reducing a CPU's work load during transmissions of data over a network.

Description

495671 A7 B7 五、發明説明(1 ) 1 ·本發明之領域: 本發明係關於一般用以透過通訊網路來處理資料的積 體電路裝置,尤指在媒體存取控制標準之內用於高速封包 處理以降低主中央處理單元負荷的方法及裝置。 2 ·相關技術之說明: 以太網路(Ethernet)區域網路(L A N )係世界上最 受觀迎並且爲大眾所普遍使用之電腦網.路中的其中一種, 因爲以太網路的起源始於1 9 7 0年初期,所以電腦網路 公司和工程技術人員持續不斷地工作以改進以太網路產品 多用性,可靠度以及傳送速度,爲了確保新的以太網路產 品係相容的,可互相操作的和可靠的,國際電機電子工程 師協會(I EEE)組成一個標準的團體來製定及提昇工 業LAN標準。·時下,I EEE 802 ·3標準團體負 責在被稱爲'Μ Ε Ε Ε 8 0 2 · 3標準之國際知名的 L A Ν標準下將新的以太網路協定和產生之發展予以標準 化。 經濟部中央標準局員工消費合作社印t (請先閱讀背面之注意事項再填寫本頁)495671 A7 B7 V. Description of the invention (1) 1 · Field of the invention: The present invention relates to integrated circuit devices that are generally used to process data through communication networks, especially for high-speed packets within the media access control standard Method and device for processing to reduce load of main central processing unit. 2 · Explanation of related technologies: Ethernet (Local Area Network) is the most popular and widely used computer network in the world. One of the roads, because the origin of the Ethernet road began in 1 In the early 970s, computer network companies and engineering technicians continued to work to improve the versatility, reliability, and transmission speed of Ethernet products. To ensure that new Ethernet products are compatible and interoperable And reliable, the International Society of Electrical and Electronics Engineers (I EEE) has formed a standards body to develop and upgrade industrial LAN standards. · Currently, the I EEE 802 · 3 standards body is responsible for standardizing new Ethernet protocols and developments under the internationally well-known LAN standard known as the 'Μ Ε Ε Ε 8 0 · 3 standard. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page)

目前,有各種不同用來接收,處理和發送在以太網路 上的資料之標準的溫順以太網路產品,藉由示例,這些網 路產品典型上被整合成網路化電腦,網路介面卡 (NICs)、SNMP/RMON探針、路由器、交換 集線器、橋接器以及中繼器等,直到最近,在以太網路上 的共同資料傳送速度爲每秒1 0百萬位元(M b p s ), 但是,爲了符合更快速之資料傳送速度的需求,_ I E E E 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) _ 4 - 495671 經濟部中央標準局員工消費合作社印繁 A7 _ B7五、發明説明(2 ) 802 · 3標準委員會於1995年5月正式提出 IEEE 8 0 2 · 3 u 〃標準,此標準也被視爲'' 1〇〇 BASE T Fast Ethernet〃標準,因爲其執行資料傳 送的能力上達大約1 0 0 M b p S。 圖1 A係一個由國際標準組織(I S 0 )所發展用以 說明介於層與層之間的資訊交換之開放式系統連接( 〇S I )層次化模式1 〇的示意圖,該OS I層次化模式 1 〇特別有利於分隔每一層的技術功能,並藉以協助一指 定層的修改或更新而不會嚴重地影響相鄰層的功能,在最 底層,OS I模式1 0具有一實體層1 2,其負責編碼及 解碼資料成爲橫跨於特別的媒體上所傳送的信號,如習於 此技者所熟知的,實體層1 2也以'' Ρ Η Y層〃而聞名。 在實體層1 2之上,資料鏈路層1 4被界定用以提供 可靠的資料傳送·於網路之上而同時執行與實體層1 2和網 路層1 6的適當介接,如所顯示,資料鏈路層1 4通常包 括一邏輯鏈路層(LLC) 14a與一媒體存取控制層( MAC) 14b,LLC層14a通常係軟體功能,其負 責將控制信號結合於從網路層1 6到M A C層1 4 b所傳 送的資,另一方面,MA C層1 4 b負責排程、發送及接 收在鏈路上的資料,因此,M A C層1 4 b主要負責控制 在網路上之資料的流量,確保傳送錯誤被檢測到,以及確 保傳送被適當地同步化,如習於此技者所熟知,M A C層 1 4 b通常使用一種眾所皆知的碰撞式多重存取載體檢測 (CSMA/CD)演算法來排程及控制與實體層1 2之 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -5- 495671 A7 _______B7 五、發明説明(3 ) 間資料的存取。 (請先閱讀背面之注意事項再填寫本頁 網路層1 6負責爲在網路中介於節點與節點之間的資 料選擇路由,以及起動,維持及中止介於被連接到該等節 點的使用者之間的通訊鏈路。運輸層1 8負責執行資料傳 送於特別等級的服務品質之內,藉由示例,一種爲執行運 輸層1 8功能所使用之代表性軟體協定可以是τ C P / I P、Novell IPX及Net Beni。交談層通常有關當使用者基 於該使用者是否能夠全雙工或半雙工傳送的狀況而得以發 送及接收資料時的控制,也有關介於需要與網路存取之使 用者應用之間的相互協調。表識層2 2負責翻、轉換、壓 縮與解壓縮橫跨於媒體之上所傳送的資料,當作一示例, 典型上藉由像 Unix、DOS、Microsoft Windows 95、At present, there are various standard compliant Ethernet products used to receive, process, and send data on the Ethernet. By way of example, these network products are typically integrated into networked computers and network interface cards ( NICs), SNMP / RMON probes, routers, switching hubs, bridges, and repeaters, etc. Until recently, the common data transmission speed on the Ethernet road was 10 million bits per second (M bps). However, In order to meet the requirements of faster data transmission speed, _ IEEE This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) _ 4-495671 Employee Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, India and India A7 _ B7 Note (2) The IEEE 802 · 3 Standards Committee formally proposed the IEEE 802 · 3 u〃 standard in May 1995. This standard is also considered as the '' 〇BASE T Fast Ethernet〃 standard because it performs data transmission. Capacity up to approximately 100 M bp S. Figure 1 A is a schematic diagram of an open system connection (〇SI) hierarchical model 1 〇 developed by the International Standards Organization (IS 0) to explain the information exchange between layers. The OS I is hierarchical. Mode 1 〇 is particularly useful for separating the technical functions of each layer, and thereby assists the modification or update of a specified layer without seriously affecting the functions of adjacent layers. At the lowest level, OS I mode 10 has a physical layer 1 2 It is responsible for encoding and decoding data to be transmitted across special media. As is well known to those skilled in the art, the physical layer 12 is also known as the "P Η Y layer". Above the physical layer 12, the data link layer 14 is defined to provide reliable data transmission over the network while performing appropriate interfacing with the physical layer 12 and the network layer 16 as shown. It is shown that the data link layer 14 usually includes a logical link layer (LLC) 14a and a media access control layer (MAC) 14b. The LLC layer 14a is usually a software function that is responsible for combining control signals with the slave network layer. 16 to the MAC layer 1 4 b. On the other hand, the MA C layer 1 4 b is responsible for scheduling, sending, and receiving data on the link. Therefore, the MAC layer 1 4 b is mainly responsible for controlling the data on the network. The flow of data, ensuring that transmission errors are detected, and ensuring that transmissions are properly synchronized. As is known to those skilled in the art, the MAC layer 1 4 b usually uses a well-known collision-based multiple access carrier detection ( CSMA / CD) algorithm to schedule and control the physical layer 1 2 (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) -5- 495671 A7 _______B7 5. Access to data between the description of invention (3). (Please read the notes on the back before filling out this page. Network layer 1 6 is responsible for selecting the routing for the data between nodes in the network, and starting, maintaining and discontinuing the use connected to these nodes. The communication link between the parties. The transport layer 18 is responsible for performing data transmission within a special level of service quality. By way of example, a representative software protocol used to perform the functions of the transport layer 18 may be τ CP / IP , Novell IPX, and Net Beni. The conversation layer is usually related to the control when a user is able to send and receive data based on whether the user can transmit in full-duplex or half-duplex mode. Coordination between user applications. The recognition layer 22 is responsible for translating, converting, compressing, and decompressing the data transmitted across the media. As an example, typically by using Unix, DOS, Microsoft Windows 95,

Windows NT以及Macintosh 〇S等的電腦操作系統來執行表 識層2 2功能。·最後,應用層2 4爲使用者提供'適合的介 面用以與網路作存取及連接。 經濟部中央標準局員工消費合作社印製 圖1 B係一個用以在橫跨於網路之上傳送資料之典型 的以太網路封包的示意圖,封包通常包括係8個位元組長 的前置部分3 0,在前置部分中之最後的位元組(或者8 個的一組(octet))係一起始框限定器(未顯示出),在 該起始框限定器octet之後,一個爲6位元組之終點位址( D A ) 3 2被用來辨識接收以太網路封包的節點,緊接著 D A 3 2之後係一個爲6位元組長之起源位址(S A ) 3 4,S A 3 4被用來辨識直接在所傳送之封包上的發送 節點,在S A 3 4之後,一個長度/型態欄(L / 丁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -6 - 495671 經濟部中央標準局員工消費合作社印製 A7 B7 一_丨 一—— ------- ______ _五、發明説明(4 ) 3 6 (典型上爲2個位元組)通常被用來表示緊接著的資 料欄長度和型態,如習於此技者所熟知,如果提供長度, 那麼該封包被分類成8 0 2 · 3封包,而如果提供型態欄 ,則該封包被分類爲以太網路封包。 接下來的資料欄被辨識爲L L C資料3 8係因爲該資 料欄也包括可能已經藉由L L C層1 4 a而被編碼的資訊 ,一個塡塞部分(P a d) 40也被顯示於接著LLC資 料3 8之後,如習於此技者所熟知的,如果一已知的以太 網路封包小於6 4個位元組,那麼大部分的媒體存取控制 器添加1和0的塡塞物於接著L L C資料3 8之後以便增 加以太網路封包尺寸到至少6 4個位元組,一旦塡塞部分 4 0被加進,如果需要的話,則一個4位元組的循環多餘 檢驗(C R C )欄就被附加於封包的末端以便在接收端檢 驗受損的封包〃如同在此所使用的,''框〃應該被了解爲 在封包之內所包含之資料的子部分。 如上所述,因爲M A C層1 4 b負責控制在網路之上 資料的流量,所以M A C層1 4 b通常負責以一適當的前 置部分 30、DA32、SA34、L/T36、Pad 4 0以及C R C 4 2來封裝所接收的L L C資料3 8,除 此之外,一封包間間隙(I P G )被顯示來辨識介於所傳 送的以太網路封包之間的時間全長,傳統上,I P G係一 個由8 0 2 · 3標準所定義並且由一適合的MAC層 1 4 b所強加之固定値,若要更多有關以太網路通訊技術 方面的資訊,可以參考具有美國專利編號 本纸浪尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) (請先閱讀背面之注意事 J· 項再填. 裝-- :寫本頁)Computer operating systems such as Windows NT and Macintosh OS perform the functions of the recognition layer 2 2. • Finally, the application layer 24 provides users with a 'suitable interface for accessing and connecting to the network. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Figure 1 B is a schematic diagram of a typical Ethernet packet used to transmit data across the network. The packet usually includes a preamble of 8 bytes. 3 0, the last byte in the preamble (or a set of 8 (octet)) is a start box qualifier (not shown). After the start box octet, one is 6 The end address (DA) 3 2 of the byte is used to identify the node that receives the Ethernet packet. Following DA 3 2 is a 6-byte origin address (SA) 3 4, SA 3 4 It is used to identify the sending node directly on the transmitted packet. After SA 3 4, a length / type column (L / D). This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)- 6-495671 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 A _ 丨 A—— ------- ______ _V. Description of the invention (4) 3 6 (typically 2 bytes) Usually Used to indicate the following column length and type, as is familiar to those skilled in the art If you provide length, then the packet is classified into 802-3 packet, and if the provided field type, then the packet is classified as an Ethernet packet road. The next column is identified as LLC data 3 8 because the column also includes information that may have been encoded by LLC layer 1 4 a. A congestion part (P ad) 40 is also displayed next to the LLC data After 38, as is well known to those skilled in the art, if a known Ethernet packet is less than 64 bytes, most media access controllers add 1 and 0 congestion to the packet. LLC data after 3 8 in order to increase the Ethernet packet size to at least 64 bytes. Once the congestion part 40 is added, if necessary, a 4-byte cyclic redundancy check (CRC) field is displayed. Attached to the end of the packet for inspection of the damaged packet at the receiving end. As used herein, the `` frame '' should be understood as a sub-portion of the information contained within the packet. As mentioned above, because the MAC layer 1 4 b is responsible for controlling the flow of data over the network, the MAC layer 1 4 b is usually responsible for a proper preamble 30, DA32, SA34, L / T36, Pad 4 0, and CRC 4 2 encapsulates the received LLC data 38. In addition, an inter-packet gap (IPG) is displayed to identify the total length of time between the transmitted Ethernet packets. Traditionally, IPG is a Defined by the 80 2 · 3 standard and imposed by a suitable MAC layer 1 4 b. For more information about Ethernet communication technology, please refer to the paper with US patent No. China National Standard (CNS) Α4 Specification (210 × 297 mm) (Please read the Caution J · on the back before filling. Installation-: Write this page)

、1T 4 495671 經濟部中央標準局負工消費合作社印製 A7 B7 五、發明説明(5 ) 5,311,114 及 5,504,738 之標題爲、、, 1T 4 495671 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (5) 5,311,114 and 5,504,738 are titled ,,

Apparatus and Method for Full-Duplex Ethernet Communications〃所發結的美國專利,這些專利在此當作參 考而被倂入。 雖然傳統的M A C層1 4 b電路對於像1 〇及1 〇 〇 BASE T系統等的較低速以太網路系統而言一直工作良好, 但是高速系統通常將高處理負荷加諸於.主機的中央處理單 元(C PU)之上,藉由示例,當以太網路速度被加速到 十億位元等級時,主C P U通常需要花費較多的時間處理 封包資料和較少的時間執行其他的C P U處理工作,結果 ,主C Ρ ϋ將易於經歷更多可能會妨礙封包發送及接收操 作的處理中斷。 當作示例,當MA C層1 4 b接收到來自較下之實體 層1 2的封包資·料時,傳統上C P U需要依照所接收的順 序從頭到尾掃瞄每一個資料以及其每一個位元以找出封包 頭之位元組位置和可能爲較上層協定所感興趣的資料,一 旦C P U已然辛苦地搜索整個封包並且確定在每一個封包 中特別有興趣的位元組位置,此資訊之全部即均可供像網 路層16、運輸層18、交談層20、表識層2 2或應用 層2 4等之較上層所使用,一旦這些較上層獲得他們需要 之有關所接收的封包之資訊,這些上層就將能夠完成他們 所指定的工作,不幸地,在高速網路中,對主CPU的要 求傾向增加到從頭至尾掃瞄每一個所接收之封包的每一個 位元不再可能不需要導入解碼、傳送或封包路由選擇的延 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -8- --------0¾衣—— (請先閲讀背面之注意事項再填寫本頁) -一口 495671 Α7 Β7 五、發明説明(6 ) 遲的等級。 除了在封包資料的接收期間所執行的C P U處理之外 ,主C P U也擔負分析傳出的資料之每一個位元組的責任 ,藉由示例,當主機係一開關或一路由器時,該開關或路 由器C P U通常負責管理路由選擇表,並且分析流量擁塞 ,此外該開關或路由器c P U也負責致力建立及使路由選 擇表成熟以持續地更新在網路中每一個節點的狀態,其他 的主C P U工作可能包括執行管理工作,回覆來自管理主 機的質詢、建立R Μ〇N資料庫等等,於是,當網路主機 被要求以增加的速度傳送資料時,主C P U將不幸地更傾 向於C P U中斷相關的延遲。 有鑒於上面所述的情形,存在對用於媒體存取控制層 處理之方法與裝置的需求,其相當適合於增加發送和接收 封包處理速度而·同時減少主C P U的處理負荷。 本發明之槪述 經濟部中央標準局員工消費合作社印製 廣泛地來講,本發明藉由提供用於具有可編程之微 R I S C半處理機用以處理在一^局速網路上之接收與發送 資料的媒體存取控制器之方法及裝置來滿足這些需求,應 該理解本發明能夠以各種的方式,包括成爲一處理機、一 裝置、一系統、一元件、一方法、或者一電腦可讀式媒體 等方式來實施,幾個本發明的發明實施例被說明於下。 在一實施例中,一種用以處理從一實體層所接收之封 包資料的方法被揭示,該處理被串列地執行而同時將封包 -9 - (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) 495671 A7 B7 五、發明説明(7 ) 傳送到一較上層,該方法包括載入用以定製編程從實體層 所接收之封包資料的處理之指令集,決定從實體層所接收 之封包資料的型態,根據指令集的內容來辨識在封包資料 中的第一個字元位置,在第一個辨識的字元位置處檢驗從 實體層所接收之封包資料,該方法更包括將一表示在該第 一個辨識的字元位置中所含之資訊的元素儲存列一資料結 構之中,以及在封包被傳送到較上層之前將該資料結構附 加於該封包資料。 在另一實施例中,一種用以處理從一較下層所接收之 封包資料的方法被揭示,該方法包括接收來自較下層之封 包’並且在一第一個字元位置處檢驗在所接收之封包中所 含的封包資料,然後,該方法將一表示在該第一個字元位 置中所含之資訊的元素儲存列一資料結構之中,該資料結 構然後在封包被·傳送到較上層之前被附加到所接收的封包 ,該媒體存取層預先處理所接收之串列的封包而同時將封 包傳送到一較上層。 經濟部中央榡準局員工消費合作社印製 在又一實施例中,用以分析所接收之串列的封包資料 與將該封包資料傳送到一較上層之封包資料處理機被揭示 ,該封包資料處理機包括一個被組構來接收可執行之微碼 的記憶體,該可執行之微碼定義從所接收之封包資料而被 建立之資料結構的型態,一管線暫存器級具有複數個暫存 器用以依序接收和暫時儲存所接收之封包資料的字元,並 且在該管線暫存器級中之複數個暫存器的每一個皆被連接 到一管線多工器,該管線多工器能夠讀取一部.分暫時被儲 -10- (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 A7 B7 五、發明説明(8 ) 存在管線暫存器級之中的字元,該封包資料處理機更包括 一分析電腦,該分析電腦被組構以檢驗從管線多工器輸出 之所接收的封包資料,並且將由分析電腦所產生之所接收 的封包資料之元素儲存到一暫存器檔案之中,此外,該封 包資料處理機包括一執行邏輯單元,其被組構以接收自記 憶體之可執行微碼,該執行邏輯單元最好被設計成藉由分 析電腦來控制所接收之封包的檢驗。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 本發明的一個特別優點在於因爲每一個所傳送的封包 藉由一個被編程來建立並且將定製之資料結構附加於每一 個所傳送的封包之微R I S C串處理機而被預先處理過, 所以使主C P U中斷達到最少,以此方式,當C P U接收 或發送封包時,所有之C P U感興趣的資訊已經被過濾出 來並且以一資料結構的型式而被附加於該封包,因此,該 C P U因爲必須’分析所傳送之封包資料的每一個位元組以 找出可能爲主C P U所感興趣之特別資訊而得以減輕負荷 ,重要的是了解到當封包資料被傳送在介於層與層之間時 ,此處理以線速率而被快速地執行,藉以減少典型上被歸 咎於主C P U中斷之傳送延遲。 另一個優點在於因爲本發明之實施例係完全A可編程 的〃並且實際上提供改善的線速率性能,所以資料結構產 生及附加過程應該相當適合於任何位元或位元組導向的網 路協定,因而應該了解到本發明之以太網路優點可以均等 地應用到其他包括F D D I、信物環流(Token Ring)、 以及A T Μ系列的網路系統之網路協定,本發明之其他方 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) _ ” " 495671 A7 B7 五、發明説明(9 ) 面及優點將從下面的詳細說明,連同伴隨的圖式,並藉由 示例來例舉本發明之原理而變得顯明。 附圖之簡略說明 藉由下面的詳細說明並結合伴隨之圖式將可很容易地 了解本發明,其中相同的參考數字表示相同的結構組件, 而且其中: 圖1 A係用以說明介於層與層之間資訊的交換而由國 際標準組織(I S〇)所發展出之開放式系統連結( 〇S I )層次化模式的示意圖。 圖1 B係傳統上爲傳送橫跨於網路上之資料所使用之 代表性以太網路封包的示意圖。 圖2 A係依據本發明的一實施例之用於高速傳送的流 基媒體存取控制·器(M A C )之結構圖。 圖2 B係依據本發明的一實施例之接收微R〗S c串 處理機之更詳細的結構圖。 經濟部中央標準局員工消費合作社印製 圖2 C係依據本發明的一實施例之圖2 B的微 R I S C串處理機之替代實施例。 圖3 A係圖示說明依據本發明的一實施例之介於圖2 B及圖2 C的主CPU與微R I S C串處理機之間的較佳 互動之高階方塊圖。 圖3 B系在依據本發明的一實施例之圖2 B及圖2 C 的微R I S C串處理機之內所含的較佳硬體單元之結構圖 -12- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 A7 ____B7 五、發明説明(1〇) 圖4A係在依據本發明的一實施例之圖2 B及圖2 C 的微R I S C串處理機之內所執行的較佳處理步驟之綜觀 流程圖。 圖4 B係圖示說明依據本發明的一實施例在載入用以 編程封包資料的接收之所需的軟體指令集時所執行之方法 步驟的更詳細之流程圖。 圖4 C係圖示說明依據本發明的一實施例與檢驗所接 收之封包有關的方法步驟之更詳細的流程圖。 圖4 D係說明依據本發明的一實施例在跳過如說明於 圖4 A中之所接收的封包資料期間所執行的處理之更詳細 的流程圖。 圖5 A到圖5 E顯示依據本發明的一實施例之可能爲 被圖2 B及圖2 C的微R I S C串處理機所接收之封包而 被可編程地產生·之代表性資料結構。 圖6 A及圖6 B顯示依據本發明的一實施例之用於已 經被使用者所編程以包含複數個旗標之封包F的資料結構 〇 經濟部中央標率局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 圖7 A及圖7 B顯示依據本發明的一實施例之可能由 使用者所定義之另一種型態的資料結構。 圖8係圖示說明依據本發明的一實施例之在接收與發 送期間發生於圖2 A之流基M A C的封包處理之方塊圖。 圖9例舉許多可能在依據本發明的一實施例的發送微 R I S C串處理機之內所執行的功能性。 圖1 0係依據本發明用以實施處理之代表性電腦系統 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -13 - 495671 A7 B7 五、發明説明(11) 的方塊圖 ο 主要元件對照表 10 開放式系統連結層次化模式 12 實體層 14 資料鏈路層 14a 邏輯鏈路控制層 14b 媒體存取控制層 經濟部中央標準局員工消費合作社印製 1 6 網 路 層 1 8 運 輸 層 2 〇 交 談 層 2 2 表 識 層 2 4 應 用 層 3 〇 刖 置 • 3 2 終 點 位 址 3 4 起 源 位 址 3 6 長 度 / 型 態 欄 3 8 邏 輯 鏈 路 控 制 資 料 4 〇 塡 補 位 元 4 2 循 τ®. 多 餘 檢 驗 1 〇 〇 結 構 圖 1 〇 1 網 路 系 統 資 料 匯流 1 〇 2 管 理 / 控 制 匯 流排 1 0 4 網路資料匯流排介面控制器 --------衣-- (請先閱讀背面之注意事項再填寫本頁)U.S. patents issued by Apparatus and Method for Full-Duplex Ethernet Communications, which are hereby incorporated by reference. Although traditional MAC layer 14b circuits have always worked well for lower-speed Ethernet systems such as 10 and 100BASE T systems, high-speed systems often place high processing loads on the center of the host. On the processing unit (CPU), by way of example, when the Ethernet speed is accelerated to the gigabit level, the main CPU usually takes more time to process the packet data and less time to perform other CPU processing. Work, as a result, the master CP will be more prone to experience more processing interruptions that may prevent packet transmission and reception operations. As an example, when the MA C layer 1 4 b receives the packet data and data from the lower physical layer 12, the CPU traditionally needs to scan every data and every bit from the beginning to the end according to the received order. To find the byte position of the packet header and the data that may be of interest to higher-level protocols. Once the CPU has worked hard to search the entire packet and determine the byte position of particular interest in each packet, all of this information That is, it can be used by the upper layers such as the network layer 16, the transport layer 18, the conversation layer 20, the surface recognition layer 22, or the application layer 24. Once these upper layers obtain the information they need about the received packets These upper layers will be able to complete their assigned tasks. Unfortunately, in high-speed networks, the requirement for the main CPU is increased to scan every bit of every received packet from end to end. The extended paper size that needs to be imported for decoding, transmission, or packet routing is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -8- -------- 0¾ clothing-(Please read the note on the back first matter Complete this page) - a 495671 Α7 Β7 V. invention is described in (6) the level of late. In addition to the CPU processing performed during the reception of packet data, the main CPU is also responsible for analyzing each byte of the outgoing data. By way of example, when the host is a switch or a router, the switch or The router CPU is usually responsible for managing the routing table and analyzing traffic congestion. In addition, the switch or router c PU is also responsible for establishing and maturing the routing table to continuously update the status of each node in the network. The other main CPUs work This may include performing management tasks, responding to inquiries from the management host, establishing an R MON database, etc., so when a network host is required to send data at an increased speed, the main CPU will unfortunately be more inclined to CPU interrupt related Delay. In view of the situation described above, there is a need for a method and apparatus for media access control layer processing, which is quite suitable for increasing the processing speed of sending and receiving packets while reducing the processing load of the main CPU. The invention is described by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economics. Broadly speaking, the present invention provides a micro RISC semi-processor with a program for processing reception and transmission on a local network. Data media access controller method and device to meet these needs, it should be understood that the present invention can be implemented in various ways, including being a processor, a device, a system, a component, a method, or a computer-readable format. Media, etc., several inventive embodiments of the invention are described below. In one embodiment, a method for processing packet data received from a physical layer is disclosed. The process is performed in series while simultaneously packet-9-(Please read the notes on the back before filling this page ) This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 495671 A7 B7 V. Description of invention (7) is transmitted to an upper layer. The method includes loading the custom received program from the physical layer. The instruction set for processing packet data determines the type of packet data received from the physical layer. The first character position in the packet data is identified based on the content of the instruction set, and the first character position is identified. Verifying the packet data received from the physical layer, the method further includes storing an element representing the information contained in the first recognized character position in a data structure, and transmitting the packet to an upper layer The data structure was previously attached to the packet data. In another embodiment, a method for processing packet data received from a lower layer is disclosed. The method includes receiving a packet from a lower layer 'and checking at a first character position the received message. The packet data contained in the packet. Then, the method stores an element representing the information contained in the first character position into a data structure. The data structure is then transmitted to the upper layer after the packet is Previously appended to the received packet, the media access layer pre-processes the received series of packets while transmitting the packets to an upper layer. Printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs in another embodiment, the packet data processor used to analyze the received serialized packet data and transmit the packet data to a higher-level packet data processor is revealed. The packet data The processor includes a memory configured to receive executable microcode. The executable microcode defines a type of data structure created from the received packet data. A pipeline register stage has a plurality of The register is used to sequentially receive and temporarily store the characters of the received packet data, and each of the plurality of registers in the pipeline register stage is connected to a pipeline multiplexer, and the pipeline is One piece can be read by the machine. Temporarily stored -10- (Please read the precautions on the back before filling out this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 495671 A7 B7 5 (8) The characters stored in the pipeline register stage. The packet data processor further includes an analysis computer configured to check the received packets output from the pipeline multiplexer. Data, and stores the elements of the received packet data generated by the analysis computer into a register file. In addition, the packet data processor includes an execution logic unit that is configured to receive data from the memory. Execution microcode, the execution logic unit is preferably designed to control the inspection of received packets by an analysis computer. Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). A special advantage of the present invention is that each transmitted packet is created by a program and customized data The micro RISC string processor attached to each transmitted packet is pre-processed, so that the main CPU interruption is minimized. In this way, when the CPU receives or sends packets, all the information that the CPU is interested in has been Filtered out and appended to the packet as a data structure. Therefore, the CPU is mitigated by having to 'analyze each byte of the transmitted packet data to find special information that may be of interest to the main CPU. It is important to understand that when packet data is transmitted between layers, this process is performed quickly at line rate, thereby reducing the transmission delay typically attributed to the main CPU interrupt. Another advantage is that because the embodiments of the present invention are fully A programmable and actually provide improved line rate performance, the data structure generation and appending process should be quite suitable for any bit or byte-oriented network protocol Therefore, it should be understood that the advantages of the Ethernet circuit of the present invention can be equally applied to other network protocols including FDDI, token ring, and ATM series network systems. The other paper specifications of the present invention are applicable China National Standard (CNS) A4 Specification (210 × 297 mm) _ "" 495671 A7 B7 V. Description of the Invention (9) The aspects and advantages will be described in detail below, along with accompanying drawings, and exemplified by examples The principle of the present invention becomes apparent. Brief description of the drawings The present invention can be easily understood through the following detailed description in conjunction with the accompanying drawings, wherein the same reference numerals indicate the same structural components, and among which: 1 A is an open system developed by the International Standards Organization (IS0) to explain the exchange of information between layers. Figure 1B is a schematic diagram of a representative Ethernet packet traditionally used to transmit data across the network. Figure 2A is a schematic diagram of an embodiment of the present invention. The structure diagram of the stream-based media access control device (MAC) for high-speed transmission. Fig. 2B is a more detailed structure diagram of the receiving micro-channel processor string according to an embodiment of the present invention. Ministry of Economic Affairs Printed by the Central Bureau of Consumer Cooperatives Figure 2C is an alternative embodiment of the micro RISC string processor of Figure 2B according to an embodiment of the present invention. Figure 3A is a diagram illustrating an introduction according to an embodiment of the present invention The high-level block diagram of the better interaction between the main CPU and the micro RISC string processor in Figures 2B and 2C. Figure 3B is a microcomputer of Figures 2B and 2C according to an embodiment of the present invention. The structure of the better hardware unit included in the RISC string processor. -12- (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) 495671 A7 ____B7 V. Description of the invention (1〇) Figure 4A is in accordance with A comprehensive flowchart of the preferred processing steps performed in the micro RISC string processor of Fig. 2B and Fig. 2C according to an embodiment of the present invention. Fig. 4B illustrates an embodiment according to the present invention. A more detailed flowchart of the method steps performed when entering the required software instruction set used to program the reception of the packet data. Figure 4C is a diagram illustrating the processing of a received packet according to an embodiment of the present invention. A more detailed flowchart of the method steps. Fig. 4D is a more detailed flowchart illustrating the processing performed during skipping of the received packet data as illustrated in Fig. 4A according to an embodiment of the present invention. Figs. 5A to 5E show representative data structures that may be generated programmatically for packets received by the micro-RISC processor of Figs. 2B and 2C according to an embodiment of the present invention. 6A and 6B show a data structure for a packet F that has been programmed by a user to include a plurality of flags according to an embodiment of the present invention; printed by an employee consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please (Read the precautions on the back before filling this page) Figures 7A and 7B show another type of data structure that may be defined by the user according to an embodiment of the present invention. FIG. 8 is a block diagram illustrating a packet processing that occurs at the flow-based M A C of FIG. 2 A during reception and transmission according to an embodiment of the present invention. FIG. 9 illustrates many of the functionalities that may be performed within a transmitting micro RIS C string processor according to an embodiment of the invention. Figure 10 is a representative computer system used for processing according to the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -13-495671 A7 B7. 5. Block description of the invention description (11). Comparison table of main components 10 Hierarchical model of open system connection 12 Physical layer 14 Data link layer 14a Logical link control layer 14b Media access control layer Layer 2 〇 Conversation layer 2 2 Knowledge layer 2 4 Application layer 3 〇 Settings • 3 2 End address 3 4 Origin address 3 6 Length / type field 3 8 Logical link control data 4 〇 Supplement bit 4 2 Follow τ®. Redundant inspection 1 〇〇 Structure diagram 1 〇 1 Network system data bus 1 〇 2 Management / control bus 1 0 4 Network data bus interface controller -------- clothing-- (Please read the notes on the back before filling this page)

、1T 本纸張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) -14 - 經濟部中央標率局員工消費合作社印製 495671 A7 —^_ 五、發明説明(12) 106 多重封包佇列先進先出發送器 108 先進先出接收器 110 網路流量管理先進先出發送器控制器 112 先進先出接收器控制器 1 1 3 a 資料路徑 1 1 3 b 資料路徑 1 1 4 a 微RISC串處理機 '1 1 4 b 微RISC串處理機 114c 微RISC串處理機 115a 資料路徑 115b 資料路徑 117 SUPERMAC管理區 118 SUPERMAC發送控制器 12 0 S U· P E R M A C接收器控制器 122 傳送匯流排介面控制器 124 平行事件處理機 125 封包緩衝器 126 狀態暫存器 12 8 統計計數器 1 3 0 可編程計數器 140 實體媒體 1 4 1 實體媒體 144a 第一資料/控制匯流排 144b 第二資料/控制匯流排 (請先閱讀背面之注意事項再填寫本頁)、 1T This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297mm) -14-Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 495671 A7 — ^ _ 5. Description of the invention (12) 106 Multiple packets Queued FIFO transmitter 108 FIFO receiver 110 Network traffic management FIFO controller 112 FIFO controller 1 1 3 a Data path 1 1 3 b Data path 1 1 4 a Micro RISC string processor '1 1 4 b Micro RISC string processor 114c Micro RISC string processor 115a Data path 115b Data path 117 SUPERMAC management area 118 SUPERMAC transmission controller 12 0 SUPERMAC receiver controller 122 Transmission bus interface control Device 124 parallel event processor 125 packet buffer 126 status register 12 8 statistical counter 1 3 0 programmable counter 140 physical media 1 4 1 physical media 144a first data / control bus 144b second data / control bus ( (Please read the notes on the back before filling out this page)

本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -15- 495671 A7 B7 五、發明説明(13) 150 流基媒體存取控制器 300 圖形使用者介面 301 中央處理單元 302 隨機存取記憶體 304 指令暫存器 305 加總單元 306 指令暫存器 307 字元計數器 3 0 8 字元計數 310 下一個位址邏輯 311 程式計數器 312 執行邏輯 314 多工器 3 16 資料’結構暫存器檔案 317 編碼器 318 多工器 320 多工器 經滴部中央標準局—工消費合作社印繁 衣-- (請先閱讀背面之注意事項再填寫本頁) 322 先進先出隨機存取記憶體 323 管線暫存器級 324 第一級暫存器 326 第二級暫存器 328 第三級暫存器 330 循環多餘檢驗單元 331 散列 ^ 本紙張尺度適用中國國家標準(CNS ) A4規格(210Χ297公釐) -16- 495671 A7 B7 五、發明説明(Μ) 經濟部中央標準局員工消費合作社印製 3 3 2 算術邏 輯 單 元 3 3 3 可編程 和 核 對 產 生 器 3 3 4 內容定 址 記 憶 體 3 3 6 比較器 3 3 7 分析電 腦 3 4 〇 匯流排 8 〇 〇 方塊圖 8 〇 2 封包 8 〇 4 附加的 索 引 8 〇 5 命令表 頭 8 〇 6 交換表 查 閱 8 〇 8 封包表 頭 8 〇 8 a 封包 表 頭 8 〇 8 b 非’同 步 傳 送 模 式 表頭 8 1 〇 a 原始 的 C R C 8 1 1 新的C R C 9 〇 2 終點位 址 9 〇 4 起源位 址 9 〇 6 資料 9 1 〇 網際網 路 協 定 表 頭 9 1 2 網際網 路 協 定 索 引 1 〇 〇 〇 電腦 系 統 1 〇 〇 2 數位 電 腦 1 0 0 4 顯不幕 --------衣-- (請先閱讀背面之注意事項再填寫本頁) 、1Τ 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) -17- 495671 A7 ——^^ 五、發明説明(15) 1 〇 0 6 列 印 機 1 〇 0 8 軟 式 磁 碟 機 1 0 1 0 硬 式 磁 碟 機 1 0 1 2 網 路 介 面 1 0 1 4 鍵 盤 1 0 1 6 微 處 理 機 1 0 1 8 記 憶 體 匯 流 排 1 0 2 0 隨 機 存取記 億體 1 0 2 2 唯 讀 記 憶 體 1 0 2 4 周 邊 匯 流 排 1 〇 2 8 匯 流 排 (請先閱讀背面之注意事項再填寫本頁} 經濟部中央標準局員工消費合作社印製 較佳實施例之詳細說明 說明一種用·於高速媒體存取控制層微R I S C機制的 發明,該機制可以被使用者編程來處理串列的封包資料而 同時將封包傳入或傳出該媒體存取控制層中心,也揭示用 於接收及發送封包資料之使用者可編程串列式處理(例如 :分析)而同時執行封包資料之高速傳入或傳出媒體存取 控制層的方法,在下面的說明中,提出各種的特別詳細內 容以便提供本發明之徹底的了解,但是,明顯地,對於習 於此技者而言,本發明就算沒有這些特別的詳細內容,也 可以被實施,在其他的實例中,並沒有詳細說明眾所皆知 之程序操作而使得本發明不致產生不必要之意義含混不淸 本紙張尺度適用中國國家標準(CNS ) A4規格(21〇X 297公釐) -18- 495671 A7 ____B7 五、發明説明(16 ) 1 ·媒體存取控制結構 圖2 A係依據本發明的一實施例之用於高速傳送的流 基媒體取存控制器(MAC) 150之結構圖,在一較佳 實施例中,預期以太網路傳送有十億位元的速度或者更快 ’但是,應該理解本結構可均等地應用於其他的傳送協定 以及較高速傳送和較低速傳送兩者之上,在一實施例中, 流基M A C 1 5 0係一平行的資料與控制處理結構,如在 圖2中所圖示說明,該流基M A C與一處理資料及控制資 訊兩者之網路資料系統匯流排1 0 1 —傳送控制及管理 資料兩者之管理/控制匯流排1 0 2介接,當資料通過網 路資料系統匯流排1 0 1並且經過流基M A C 1 5 0之各 種處理區的處理時,控制資訊也可以同時通過網路資料系 統匯流排1 0 1,重要的是了解這種類型的平行處理提供 在任何指定的時·間改變在流基M A C 1 5 0之內的處理參 數之能力(也就是,甚至當正在處理封包資料的同時)。 經濟部中央標準局員工消費合作社印製 (讀先閱讀背面之注意事項再填寫本頁) 藉由示例,假設資料從一較高之L L C層被接收,並 且經過各種處理區的處理,在該資料中,前置欄及C R C 欄所附加而形成封包,由於流基M A C 1 5 0的平行處理 特性,控制資訊可以同時通過網路資料系統匯流排1 〇 1 以修改封包尙未被處理的部分,於是,流基M A C 1 5 0 之平行處理特性能夠傳送適當的控制資訊以改變特殊之處 理參數,即使當資料目前正被處理之時。 首先參考發送側,當資料剛開始經由網路資料系統匯 流排1 0 1而從較上之L L C層被接收時,資料被傳送到 冢纸張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) ~\〇Τ 495671 A7 B7 五、發明説明(17) 一網路資料匯流排介面控制器(B I C ) 1 0 4,在此實 施例中,網路資料B I C可以是任何像一從屬介面及一直 接記憶體存取(DMA)板上介面等之適當的介面控制器 ,如所顯示,當流基M A C 1 5 0需要高性能交換工作時 ,一第一資料/控制路徑1 4 4 a和一第二資料/控制路 徑1 4 4 b可以被用來將網路資料匯流排介面1 〇 1與網 路資料B I C 1 0 4互相連接,藉由示例,第一資料/控 制路徑1 4 4 a可以被用來執行從較上之L L C層到流基 M A C 1 5 0的傳送,而且第二資料/控制路徑1 4 4 b 可以被用來執行從流基M A C 1 5 0到較上之L L C層的 傳送,當然,也期望藉由組合144a與144b,一條 單一雙向資料/控制路徑可以被用來執行前述之控制及資 料傳送。 經濟部中央標準局負工消費合作社印架 (請先閱讀背面之注意事項再填寫本頁) 一旦資料從·網路資料系統匯流排1 0 1被發送到網路 資料B I C 1 〇 4,然後資料就可以被適當地傳送到一多 種封包佇列FIFO Txl〇6,一般而言,FIFO T X 1 〇 6充當用以保持經由網路資料系統匯流排 1 0 1而從較上之L C C層所發送之資料的緩衝器,在此 實施例中,F I F〇 T X 1 〇 6最好能夠儲存大量的封 包資料,此乃超越傳統的封包F I F〇結構之重大改進, 典型上,傳統之封包F I F 0結構不能夠容納相對於由依 據本發明的一實施例之十億位元速度(例如,+ 1 0 0 0 M b p s )系統所產生之增加的推送量更多的儲存物要求 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) -20 - 495671 A7 B7 五、發明説明(18) 一旦適當量的封包被暫存於FIF〇 Txl06中 ,一網路流量管理F I F Ο T X控制器1 1 0被實施來 管理從F I F〇 Txl 06流入一微R I SC串處理機 1 1 4 a之高速流動的封包,在一較高階層中,網路流量 量管理F I F〇 T X控制器1 1 0可以負責爲橫跨於網 路之上,被傳送到許多在F I F〇 T X 1 0 6之內所含 之鏈結的緩衝器之中,像語音、影像、圖形等之不同類型 的資料排定其優先順序,在此實施例中,流基M A C 1 5 0能夠具有多條同時一起流經F I F〇 T x 1 〇 6 的資料串,在一特色中,當封包從F I F〇 T x 1 〇 6 中被讀出時,可以跳過任何一個特別的封包而無需讀取整 個封包,在另一特色中,一封包可以藉由保持一指定封包 於可編程的時間之內而從F I F〇 Τ X中被再次發送, 在又一特色中,· 一個被寫入F I F〇 Txl 06之中的 封包可以在被發送到微R I S C串處理機1 1 4 a之前直 接被冲出F I F〇 Τ X 1 〇 6之外。 經濟部中央標準局員工消費合作社印製 在又一實施例中,控制資料可以被嵌入在F I F〇 Tx 1 〇 6中所暫存的封包之內,以此方式,處理參數可 以用一種管線式封包接封包的原則來修正,藉由示例,所 嵌入之控制資訊可以包含對處理參數的修正以及爲修正而 選出一特別封包的辨識資訊,應該理解擁有一智慧型網路 流量管理F I F〇 Τ X控制器1 1 〇也協助網路管理和 相關的測試協定’雖然少數情況應該要求處理參數爲了每 一個連續的封包而被改變,將可理解爲了在一封包串中之 -21 - (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ 297公釐) 495671 A7 B7 五、發明説明(19) 任何指定的封包修正處理參數之能力係一種強而有力的特 色。 一旦網路流量管理F I F Ο T X控制器1 1 〇根據 所接收之控制資訊來執行任何所要求的處理,微R I S C 串處理機、1 1 4 a就適合來執行各種的使用者可編程封 包處理、分析、過濾以及封裝操作,藉由示例,微 R I S C串處理機1 1 4 a以一種用以修改資料串特性的 串列方式來運作,最好,微R I S C串處理機1 1 4 a ( 以及用於接收側的1 1 4 b )同時運作於3 2位元字元部 分之上以有效地處理沿著流基M A C 1 5 0流動資訊,而 同時獲得十億位元的速度(以及更高速)性能,此外,指 令最好被位元組串所觸發而停止,在此實施例中,微 R I S C串處理機1 1 4 a也適合以各種像,舉例來說, 相對位元組計算·模式,之定址模式來運作。 經濟部中央標準局員工消費合作社印製 微R I S C串處理機1 1 4 a的內部將最好具有一組 通用暫存器、資料結構暫存器,以及分析電腦單元,藉由 示例,該分析電腦單元可以包括一 C R C單元、一壓縮散 列資料單元、一 A L U單元、一可編程和核對產生器、一 C A Μ,以及比較器,除此之外,微R I S C串處理機 1 1 4 a最好能夠運作於提供額外之彈性度及改進之性能 的一種條件、分支和迴路模式中,最後,微R I S C串處 理機1 1 4 a處理指令可包括許多創新的封包欄操作,代 表性的操作可包括:用於特殊化表頭產生、分離資料及表 頭、IP — CHKSUM核對與長度計算的CUT、 -22- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 A7 B7 五、發明説明(20) CLEAR、COPY、APPEND、WSERT、 AND、〇R、 X〇R、 MOVE、 JUMP。 在又一實施例中,本發明之微R I S C串處理機包括 一加密/解密單元,其用以選擇性分析流經微R I S C串 處理機的封包,並藉以應要求而提供使用者選擇性加密及 解密封包的能力,以此方式,使用者能夠選擇可能是敏感 性的某些封包,並藉以防此封包的傳送於未受保護之狀態 中,仍進一步地,可以包括一壓縮/解壓縮單元以選擇性 增加在網路上的流量率,因此,在該壓縮/解壓縮可以爲 某些流經微R I S C串處理機的封包根據應用串的類型( 例如:語音、影像、資料等等)來定目標,該也致使有損 或無損壓縮標準的應用。 經濟部中央標準局員工消費合作社印製 仍然參考圖2 A,一旦適當的資料及控制資訊被處理 於微R I S C串·處理機1 1 4 a之內,資料即經由資料路 徑1 1 3 a而被傳送到SUPERMAC Tx控制器 1 18 ’該SUPERMAC Tx控制器1 18最好係 一被組構來處理從微R I S C串處理機1丨4 a所接收之 封包並且將處理過的封包輸出到一實體(ρ Η γ )媒體 1 4 0的狀態機。 圖2Α也顯不一 SUPERMAC管理區1 17,宜 負責在介於一發送的SUPERMAC Tx@制J器 1 1 8與一接收的SUPERMAC Rx控制器1 20 之間的介接’ S U P E R M A C管理區1 1 7也與網路流 量管理F I F〇 T X控制器1 1‘ 〇,網路流量管理 -23- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 μ _Β7 五、發明説明(21 ) FIFO R x控制器1 1 2,以及管線資料b ϊ C 1 04介接,一般來講’ SUpERMAC管理區1 1 7 作用當作一接收流量控制資訊、自動協商命令、實際管理 命令,以及暫停框資訊的介面(也就是一接收單元使用暫 停框來通知一發送單元停止資料的傳送直到一接收緩衝器 係處於可用之狀態)° 在此實施例中,SUPERMAC Tx控制器 1 18及SUPER MAC Rx控制器120顯示被鏈 接到一第二微RI SC串處理機1 14c,該第二微RI S C串處理機1 1 4 c最好被包含於一平行事件處理機( PEP) 124之內,在此實施例中,發生在 SUPERMAC Tx控制器118與 SUPERMAC Rx控制器120之內適當的處理事 件可以被傳送到·微R I S C串處理機1 1 4 b,以此方式 ,發生在SUPERMAC Rx與Tx控制器之內的處 理事件可以被儲存於P E P 1 2 4之適當的統計計數器 1 2 8之內。 經濟部中央標準局員工消費合作社印製 在接收側,微R I S C串處理機1 1 4 b被連接到微 R I S C串處理機1 1 4 c以便監視並追踪進出於流基 M A C 1 5 0所處理的資料,典型上,資料經過一實體( Ρ Η Y )媒體1 4 1而被接收到流基M A C 1 5 0之中, 而後被傳送到S U P E R M A C R x控制器1 2 0,在 一實施例中,S U P E R M A C R x控制器1 2 0能夠 直接將所接收之C R C欄或塡充欄‘傳送到微R I S C串處 -24- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 A7 B7 五、發明説明(22) 理機1 1 4 b而無需執行的剝離功能,當此情況發生時, 在將所接收的封包資料傳送到較上之L L C層之前,可以 藉由微R I S C串處理機1 1 4 b其本身來執行剝離功能 ,一旦SUPERMAC Rx控制器120接收來自實 體媒體1 4 1的封包,該封包被傳送到用以處理之微 R I S C串處理機1 1 4 b而後再被傳送到多重封包佇列 FIFO Rxl08。 經濟部中央標準局員工消費合作社印製 當在發送側時,在S U P E R M A C R x控制器 1 2 0所執行的事件與微R I S C串處理機1 1 4 b都被 鏈接到微R I S C串處理機1 1 4 c,其說明那些在統計 計數器1 2 8中的事件,最好,網路流量管理F I F〇 R x控制器1 1 2能夠將一數字指定給每一個由F I F〇 Rxl08所接收的封包,因爲FIF〇 Rx控制器 1 1 2可以知道被指定給每一個封包的數字,所以控制信 號可以被傳送到請求傳送在F I F〇 R X 1 〇 8中所儲 存之特別編號的封包之F I F〇 R X控制器1 1 2 (也 就是,爲了管理目的而傳送到LL C層或PEP 1 2 4) ,一旦資料在交換的環境中被傳送出多重封包佇列 FIFO Rxl08並且被傳送入網路資料BIC 1 0 4時,資料就經由資料路徑1 4 4 b而被傳送到網路 資料系統匯流排1 0 1上,當然,一條單一雙向資料路徑 可以被替代使用來代替路徑1 4 4 a及1 4 4 b。 更注意到從微R I S C串處理機1 1 4 b傳送到 FIFO R X 1 0 8之相同的封包串可以使用全雙工模 -25- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 A7 ______B7_ 五、發明説明(23) 式而被同時傳送到管理側微R I S C串處理機1 1 4 c ( 也就是埠鏡射),以此方式,可以對在P E P 1 2 4之內 所接收之封包串執行管理工作而同時傳送資料到較上層。 在此實施例中,流量控制B I C 1 2 2最好爲傳遞控 制資訊及執行資料管理工作而被實施,藉由示例,在執行 網路管理工作方面,可能必須從經由網路資料B I C 1〇4所處理之封包的路徑上拉出(也就是過濾出)一特 別資訊的封包,一旦所需的封包被辨識出,該封包然後就 可以被位於平行事件處理機(P E P ) 1 2 4之內的微 R I S C串處理機1 1 4 c所過濾。 微R I S C串處理機1 1 4 c最好也負責編程新的事 件,過濾所需的封包以及緩衝所需的封包於適當的緩衝器 中,此外,微R I S C串處理機1 1 4 c能夠起動可編程 的臨界値處理、·警報產生、S Ν Μ P / R Μ〇N封包傳送 、產生測試框、以及用於矩陣統計產生之流量的檢測,除 此之外,一基本組的硬連線計數器也可以被提供來解釋被 微R I S C串處理機1 1 4 c所執行之各種的處理操作。 t 經濟部中央標準局員工消費合作社印製 在此實施例中,網路管理操作通常被用來決定像框送 量、運轉、碰撞的數目,通信量特性等等之所挑選的網路 統計資料,有利的是,簡單網路管理協定(S Ν Μ P ), 和遠程監視(R Μ〇Ν )也可以透過圖2的Ρ Ε Ρ 1 2 4 來實施,如習於此技者所熟知,R Μ Ο Ν監視讓網路管理 員爲包羅萬象的網路錯誤診斷、規劃和性能調整分析各種 的通信量統計資料及網路參數。‘ -26- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 495671 A7 B7 _ 五、發明説明(24 ) 於是,P E P 1 2 4包括一用以儲存適當封包之創新 的封包緩衝器1 2 5,該適當封包藉由像SNMP及 R Μ Ο N之網路管理協定而被實施,藉由示例,如果使用 者想要監視在經由網路資料Β I C 1 〇 4所處理的資料串 之內的某些封包,微RISC串處理機114b及114 c將過濾出隨後被儲存在封包緩衝器1 2 5中之所需的封 包,命令及狀態暫存器1 2 6也被包括在P E P 1 2 4之 內,使得命令暫存器經由流量控制Β I C 1 2 2接收來自 管理/控制匯流排1 〇 2的相關控制信號,在一實施例中 ,1 1 4 b及1 1 4 c可以是相同的處理實體。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 統計計數器1 2 8也被顯示出,其負責儲存可能發生 在 SUPERMAC Tx 控制器 118、 SUPERMAC管理區117、 SUPERMAC Rx控制器12·0、微RI SC串處理機1 14a、以及 微R I S C串處理機1 1 4 b之內的特別事件,於是,當 封包被處理以及事件發生時,事件資訊被傳送入微 R I S C串處理機1 1 4 c之中,而後被儲存於統計計數 器1 2 8之中,此外,複數個可編程計數器1 3 0被提供 於P E P 1 2 4之內,用以追踪可能在目前未被定義,但 可能被定義於未來之新的事件(也就是可編程的事件), 例如,可以用使用者編程於微R I S C 1 1 4 a、 1 1 4 b以及1 1 4 c中之微碼來產生新的事件。 圖2 B係依據本發明的一實施例爲了接收來自 SUPERMAC R X控制器11 2 0之封包資料而特別 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) :27: 495671 kl B7 五、發明説明(25 ) 實施之微R I S C串處理機1 1 4 b的更詳細結構圖,如 上所述,封包資料最初從實體媒體1 4 1被導入流基媒體 存取控制器1 5 0,而且一旦使用者定義的處理被執行於 微R I S C串處理機1 1 4 b,所處理之封包資料被傳送 到多重封包FIFO Rxl08,其係與FIFO R x控制器1 1 2通訊聯絡,在一實施例中,所處理之封 包最好被分類成複數個在多重封包佇列F I F 0 R X 1 0 8之內所含的改變優先順序之緩衝器,以此方式,如 果一特別的封包含有時間敏感資料,那個封包將會被放在 一較高優先順序的緩衝器中,而且其他較無時間敏感的資 料將會被放在其他改變優先順序的緩衝器中,在另一實施 例中,F I F〇 R X控制器1 1 2可能相當適合來監視 由主C P U所處理之通信量密度,在此實施例中,當 FIFO R χ·控制器1 1 2決定該主C P U (例如伺服 機)正在經歷一段高通信量時,所接收之封包將暫時被儲 存在F I F〇 Rxl 08之中,而後一次全部被傳送到 較上層以減少被主C P U所經歷之中斷的次數。 經濟部中央標準局員工消費合作社印紫 (請先閱讀背面之注意事項再填寫本頁) 在一實施例中,微R I S C串處理機1 1 4 b係一種 使用者可編程式串列封包處理機制,其能夠快速地從頭到 尾分析所接收之封包資料以建立使用者定義的資料結構, 該使用者定義的資料結構可以被附加於所接收之封包的開 頭在其被傳送到多重封包佇列F I F 0 R X 1 0 8之前 ,爲了起動微R I S C串處理機1 1 4 b之使用者編程操 作,使用者可以組構一指定即將對進入之封包資料執行分 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -28 - 495671 A7 __________B7_ 五、發明説明(26 ) 析的類型以及資料結構的類型之軟體指令集,以透過圖形 使用者介面(G U I )的使用來建立並附加於個別之封包 ,一旦指令集被組構,軟體指令集就藉由主C P U而被編 譯成可執行、、微碼〃,而後被傳送入位於微R I S C串處 理機1 1 4 b之積體電路中心的硬體記憶體位置之中。 經濟部中央標準局員工消費合作社印製 重要的是了解發生於微R I S C串處理機1 1 4 b之 封包資料處理快速產生呈串列型式之使用者定義的資料結 構(也就是不致降低資料傳送速率)以有利於將定義的資 料結構附加到被傳送到較上層之封包,當較上層接收具有 所附加之資料結構的資料封包時,該較上層不需要一個位 元組接一個位元組(或者一個位元接一個位元)掃瞄緊密 結合於C P U頻寬之整個封包來辨識感興趣的封包資料, 這是因爲使用者定義的資料結構可以被編程而將指標儲存 於在爲較上層協·定所感興趣的封包資料之內的部分,或者 在可以被快速讀取及處理之資料(散列或壓縮的資料)的 部分,而不必花費C P U頻寬以掃瞄和處理整個封包,一 旦較上層接收緊縮編碼的資料結構資訊,該較上層就可以 快速地將封包資料傳送到其預期的目的地(例如:開關、 路由器、客戶、伺服機等等),在一實施例中,該資料結 構資訊可以以一種 >狀態/解說符〃的形式而被提供給主 機,該v'狀態/解說符〃其後被主封包處理軟體所處理。 如上所述,使用者可以編程微R I S C串處理機 1 1 4 b以產生定製的資料結構,其包含,例如,一指到 網際網路協定(I P )頭之起始的‘指標、一指到傳送控制 -29- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X29?公釐) 495671 A7 ___ _B7 五、發明説明(27 ) 協定(T C P )表頭之起始的指標、以及一指到簡單郵件 傳送協定(S Μ T P )表頭之起始的指標,其他代表性資 料結構可以被編程來包括封包資料其本身像I Ρ目的位址 和壓縮散列資料的部分,因爲資料結構的類型及資料結構 的內容可以完全由使用者編程,其他代表性資料結構可以 包括''旗標〃資料結構,其中每一個位元被編程以辨識一 協定或另一協定,或者〜欄〃資料結構,其中多數位元被 編碼來辨識不同的網路協定。 , 圖2 C圖示說明依據本發明的一實施例之用於微 R I S C串處理機1 1 4 b的替代實施例,在此實施例中 ,微R I S C串處理機1 1 4 b的硬體邏輯組件被分成第 一部分(PART I)及第二部分(PART II) ,藉由分裂微R I S C串處理機1 1 4如所顯示,因爲所 接收的封包可以·被處理於PART I以及PART I I中(也就是在被儲存於多重封包佇列F I F〇 R X 1 0 8中之前及之後),所以可以達成顯著的處理能力。 經濟部中央標準局員工消費合作社印繁 藉由示例,該結構分離提供一內建式 ''延遲〃以協助 像封包表頭修正及協定翻譯處理的處理,在一實施例中, 封包表頭修正可以包括封包分裂及轉換來將標準的以太網 路封包轉變成爲一非同步傳送模式(A T Μ )單元,其他 的封包翻譯功能性可以包括介於以太網路,信物環和 F D D I之間的翻譯橋接,該分裂結構也讓使用者編程微 R I S C串處理機1 1 4 b在其從多重封包佇列F I F〇 R X 1 0 8被輸出之後執行和查‘核的操作。 -30- (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 經濟部中央標準局員工消費合作社印製 495671 A7 ____B7_ 五、發明説明(28) 因爲微R I S C串處理機1 1 41^係一種可以被定製 編程而以使用者定義的方式處理進來的封包之彈性的處理 單元’所以微R I S C串處理機1 1 4 b的分裂結構可以 被用來執行許多其他可能本能地要求內部延遲之使用者定 義的工作’應該了解到這些次要的內部延遲絕對不能夠減 慢流基M A C 1 5 0之高速(例如十億位元或者更高)資 料傳送速率’相反地,由圖2 C之分裂結構所提供的內部 延遲僅藉由卸除主C P U必須檢查所接收之封包的實際部 分之負荷來提高處理速率和資料傳送速率,當然,應該了 解到微R I S C串處理機的分裂結構也可以被實施於微 R I S C串處理機1 1 4 b的發送側上。 2 ·微R I S C串處理機結構 圖3 A係圖·示說明依據實施例的一實施例之介於主 C P U 3 0 0與微R I S C串處理機1 1 4 b之間的較佳 互動關係之高階方塊圖,如上所述,因爲使用者能夠編程 即將被執行於微R I S C串處理機1 1 4 b中之處理的方 式,所以使用者最好被引導來定義一爲了辨識資料結構之 類型而建立的軟體指令集以及該資料結構的內容,爲了達 成此目的,使用者最好實施一提供一系列便於編程之選擇 的圖形使用者介面(GUI) 300,該GUI 300產 生被一 C P U 3 0 0所編譯的軟體指令集,所編譯之軟體 指令集然後被轉換成可執行微碼,在一實施例中,該微碼 將最好包含所有辨識建立之資料結構的型態之使用者編程 (請先閱讀背面之注意事項再填寫本頁)This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -15- 495671 A7 B7 V. Description of the invention (13) 150 Stream-based media access controller 300 Graphical user interface 301 Central processing unit 302 Random storage Fetch memory 304 instruction register 305 summing unit 306 instruction register 307 word counter 3 0 8 character count 310 next address logic 311 program counter 312 execution logic 314 multiplexer 3 16 data 'structure temporary storage Device file 317 encoder 318 multiplexer 320 multiplexer printed by the Central Standards Bureau of the Ministry of Industry and Technology—Consumer Cooperative Co., Ltd .— (Please read the precautions on the back before filling this page) 322 FIFO RAM 323 Pipeline register stage 324 First-stage register 326 Second-stage register 328 Third-stage register 330 Recycling redundant inspection unit 331 Hash ^ This paper standard applies to China National Standard (CNS) A4 specification (210 × 297 (Mm) -16- 495671 A7 B7 V. Description of Invention (M) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3 3 2 Arithmetic and logic unit 3 3 3 Programmable and check generated Device 3 3 4 Content addressing memory 3 3 6 Comparator 3 3 7 Analysis computer 3 4 〇 Bus 8 〇 〇 Block diagram 8 〇 2 Packet 8 〇 4 Additional index 8 〇 5 Command header 8 〇 6 Exchange table lookup 8 〇8 Packet header 8 〇8 a Packet header 8 〇8 b Asynchronous transmission mode header 8 1 〇a Original CRC 8 1 1 New CRC 9 〇 End point address 9 〇 Origin address 9 〇6 Data 9 1 〇 Internet Protocol Header 9 1 2 Internet Protocol Index 1 〇〇〇〇 Computer System 1 〇 02 Digital Computer 1 0 0 4 Unseen -------- Clothing- (Please read the precautions on the back before filling this page), 1T This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) -17- 495671 A7 —— ^^ V. Description of the invention (15) 1 〇0 6 Printer 1 〇8 Soft Disk Drive 1 0 1 0 Hard Disk Drive 1 0 1 2 Network Interface 1 0 1 4 Keyboard 1 0 1 6 Microprocessor 1 0 1 8 Memory bus 1 0 2 0 Random access memory 100 2 2 Read-only memory 1 0 2 4 Peripheral bus 1 0 2 8 Bus (Please read first Note on the back, please fill out this page again} The detailed description of the preferred embodiment printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economics explains an invention of a micro-RISC mechanism for high-speed media access control layers, which can be programmed by users To process serial packet data while simultaneously transmitting packets to or from the media access control center, and also revealing user-programmable serial processing (such as analysis) for receiving and sending packet data while performing concurrently In the following description, a method for high-speed transmission and reception of packet data into and out of the media access control layer is provided in order to provide a thorough understanding of the present invention. However, it is obvious to those skilled in the art that In other words, the present invention can be implemented even without these special details. In other examples, well-known procedures are not described in detail. So that the present invention does not produce unnecessary meaning. The paper dimensions are applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 mm) -18- 495671 A7 ____B7 V. Description of the invention (16) 1 · Media Access control structure FIG. 2A is a structure diagram of a stream-based media access controller (MAC) 150 for high-speed transmission according to an embodiment of the present invention. In a preferred embodiment, the Ethernet transmission is expected to have Gigabit speed or faster '. However, it should be understood that this structure can be equally applied to other transmission protocols and both higher speed transmission and lower speed transmission. In one embodiment, the flow-based MAC 1 5 0 is a parallel data and control processing structure. As illustrated in Figure 2, the stream-based MAC and a network data system bus that processes both data and control information. 1 0 1—Transmit control and management data The management / control bus of the two is interfaced with 102. When the data is processed by the network data system bus 1 0 and processed by various processing areas of the stream-based MAC 1 50, the control information can also pass through the network at the same time. Department of Information Bus 1 0 1 It is important to understand that this type of parallel processing provides the ability to change the processing parameters within the flow-based MAC 1 50 at any given time (ie, even when the packet data is being processed Simultaneously). Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (read the precautions on the back and then fill out this page). By way of example, suppose that the data is received from a higher LLC layer and processed in various processing areas. In the front column and the CRC column, the packet is formed. Due to the parallel processing characteristics of the stream-based MAC 150, the control information can be simultaneously transmitted through the network data system bus 1 001 to modify the unprocessed part of the packet. Thus, the parallel processing characteristics of the stream-based MAC 150 can transmit appropriate control information to change special processing parameters, even when the data is currently being processed. First refer to the sending side. When the data is first received from the upper LLC layer via the network data system bus 1 0 1, the data is transmitted to the mound paper. The standard is Chinese National Standard (CNS) A4 (210X 297) (Mm) ~ \ 〇Τ 495671 A7 B7 V. Description of the invention (17) A network data bus interface controller (BIC) 104. In this embodiment, the network data BIC can be anything like a slave interface And an appropriate interface controller such as a direct memory access (DMA) on-board interface, as shown, when the flow-based MAC 1 50 requires high-performance switching, a first data / control path 1 4 4 a And a second data / control path 1 4 4 b can be used to interconnect the network data bus interface 1 〇1 and the network data BIC 1 0 4. By way of example, the first data / control path 1 4 4 a can be used to perform the transfer from the upper LLC layer to the flow-based MAC 1 50, and the second data / control path 1 4 4 b can be used to perform the transfer from the flow-based MAC 1 50 to the upper LLC Layer transmission, of course, it is also expected that by combining 144a and 144b, a single Bidirectional data / control path may be used to perform the transfer of control and resource materials. The print stand of the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling this page) Once the data is sent from the network data system bus 1 0 1 to the network data BIC 1 〇4, then the data It can be properly transmitted to a variety of packet queues FIFO Tx106. Generally speaking, FIFO TX 106 is used to keep the data sent from the upper LCC layer via the network data system bus 1 0 1 In this embodiment, it is better that FIF0TX 1 06 can store a large amount of packet data. This is a significant improvement over the traditional packet FIF〇 structure. Typically, the traditional packet FIF 0 structure does not Capable of accommodating more storage compared to the increased push volume generated by a gigabit speed (eg, + 1 0 0 0 bps) system according to an embodiment of the present invention. This paper size applies Chinese national standards (CNS) A4 specification (210 X 297 mm) -20-495671 A7 B7 V. Description of the invention (18) Once the appropriate amount of packets are temporarily stored in FIF〇Txl06, a network traffic management FIF TX TX controller 1 1 0 Shi Lai manages the high-speed packets flowing from FIF0Txl 06 to a micro RI SC string processor 1 1 4 a. In a higher level, the network traffic management FIF TX controller 1 1 0 can be responsible for horizontal Across the network, it is transmitted to many buffers in the link contained in FIF0TX 106. Different types of data such as voice, video, graphics, etc. are prioritized. In this embodiment, the flow-based MAC 1 50 can have multiple data strings flowing through FIFOT x 1 〇6 at the same time. In a feature, when a packet is read from FIFOT x 1 〇6 You can skip any particular packet without reading the entire packet. In another feature, a packet can be re-sent from FIF〇Τ X by keeping a specified packet within a programmable time. In yet another feature, a packet written into FIF0Txl 06 can be directly flushed out of FIF0T X 1 06 before being sent to the micro RISC string processor 1 1 4a. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. In another embodiment, the control data can be embedded in the temporarily stored packets in FIFOTx 106. In this way, the processing parameters can be packaged in a pipeline. Modify the principle of receiving packets. By way of example, the embedded control information can include corrections to processing parameters and identification information for selecting a special packet for correction. It should be understood that it has an intelligent network traffic management FIF〇Τ X control Device 1 1 〇 also assists with network management and related testing protocols. 'Although in a few cases, processing parameters should be changed for each successive packet. It will be understood that -21 in a packet string-(Please read the back first Note: Please fill in this page again.) This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 495671 A7 B7 V. Description of the invention (19) The ability of any specified packet to modify the processing parameters is a powerful Characteristics. Once the network traffic management FIF 〇 TX controller 1 1 〇 performs any required processing based on the received control information, the micro RISC string processor, 1 1 4 a is suitable to perform various user-programmable packet processing, Analysis, filtering, and packaging operations. By way of example, the micro RISC string processor 1 1 4 a operates in a tandem manner to modify the characteristics of the data string. Preferably, the micro RISC string processor 1 1 4 a (and use 1 1 4 b) on the receiving side operates on 32-bit characters at the same time to effectively process the flow of information along the stream-based MAC 1 50 while obtaining a billion-bit speed (and higher speed) Performance, in addition, the instruction is preferably triggered and stopped by the byte string. In this embodiment, the micro RISC string processor 1 1 4 a is also suitable for various images, for example, relative byte calculation and mode. Addressing mode to operate. The micro-RISC string processor 1 1 4 a printed by the staff consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs will preferably have a set of general purpose registers, data structure registers, and an analysis computer unit. By way of example, the analysis computer The unit may include a CRC unit, a compressed hash data unit, an ALU unit, a programmable and check generator, a CA M, and a comparator. In addition, the micro RISC string processor 1 1 4 a is best Can operate in a condition, branch, and loop mode that provides additional flexibility and improved performance. Finally, the micro RISC string processor 1 1 4 a processing instructions can include many innovative packet bar operations. Representative operations can include : CUT for special header generation, separation of data and header, IP — CHKSUM check and length calculation, -22- (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS ) A4 specification (210X297mm) 495671 A7 B7 V. Description of the invention (20) CLEAR, COPY, APPEND, WSERT, AND, OR, XOR, MOVE, JUMP. In another embodiment, the micro RISC string processor of the present invention includes an encryption / decryption unit for selectively analyzing packets passing through the micro RISC string processor, and providing users with selective encryption and encryption upon request. The ability to decapsulate packets, in this way, the user can select certain packets that may be sensitive and prevent this packet from being transmitted in an unprotected state. Still further, a compression / decompression unit may be included to Selectively increase the traffic rate on the network. Therefore, in this compression / decompression, some packets passing through the micro RISC string processor can be targeted according to the type of application string (for example: voice, image, data, etc.) This should also lead to the application of lossy or lossless compression standards. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs still refer to Figure 2A. Once the appropriate data and control information is processed within the micro RISC string processor 1 1 4 a, the data is processed via the data path 1 1 3 a Transmitted to the SUPERMAC Tx controller 1 18 'The SUPERMAC Tx controller 1 18 is preferably configured to process the packets received from the micro RISC string processor 1 丨 4 a and output the processed packets to an entity ( ρ Η γ) the state machine of the medium 140. Figure 2A also shows a SUPERMAC management area 1 17 and should be responsible for interfacing between a SUPERMAC Tx @ 制 J 器 1 1 8 and a received SUPERMAC Rx controller 1 20 'SUPERMAC management area 1 1 7 also with network traffic management FIF TX controller 1 1 〇, network traffic management -23- (Please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specifications ( 210X297 mm) 495671 μ _B7 V. Description of the invention (21) FIFO R x controller 1 1 2 and pipeline information b ϊ C 1 04 interface. Generally speaking, 'SUpERMAC management area 1 1 7 functions as a receiving traffic Interfaces for control information, auto-negotiation commands, actual management commands, and pause frame information (that is, a receiving unit uses the pause frame to notify a sending unit to stop data transmission until a receiving buffer is available) ° implemented here In the example, the SUPERMAC Tx controller 1 18 and the SUPER MAC Rx controller 120 show that they are linked to a second micro RI SC string processor 1 14c, which is preferably included in A parallel event Within the processing machine (PEP) 124, in this embodiment, appropriate processing events that occur within the SUPERMAC Tx controller 118 and the SUPERMAC Rx controller 120 can be transmitted to the micro RISC string processor 1 1 4 b to In this way, processing events that occur within the SUPERMAC Rx and Tx controllers can be stored in the appropriate statistical counters 1 2 8 of PEP 1 2 4. Printed on the receiving side by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, the micro RISC string processor 1 1 4 b is connected to the micro RISC string processor 1 1 4 c to monitor and track incoming and outgoing processing by the stream-based MAC 1 50 The data is typically received in a stream-based MAC 1 50 through a physical (P Η Y) media 1 4 1 and then transmitted to the SUPERMACR x controller 1 2 0. In one embodiment, the SUPERMACR The x controller 1 2 0 can directly transmit the received CRC column or refill column to the micro RISC string -24- (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS ) A4 specification (210X297 mm) 495671 A7 B7 V. Invention description (22) Machine 1 1 4 b without the need to perform the stripping function. When this happens, the received packet information is transmitted to the upper LLC Before the layer, the stripping function can be performed by the micro RISC string processor 1 1 4 b itself. Once the SUPERMAC Rx controller 120 receives a packet from the physical media 1 4 1, the packet is transmitted to the micro RISC string for processing. Place 1 1 4 b and the machine then the packet is transmitted to multiple queue FIFO Rxl08. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. On the sending side, the events executed at the SUPERMACR x controller 1 2 0 and the micro RISC string processor 1 1 4 b are linked to the micro RISC string processor 1 1 4 c, which describes those events in the statistics counter 1 28. Preferably, the network traffic management FIFOR x controller 1 1 2 can assign a number to each packet received by FIFORR 108, because FIF 〇Rx controller 1 1 2 can know the number assigned to each packet, so the control signal can be transmitted to the FIF RX controller 1 1 requesting the transmission of the specially numbered packet stored in FIF〇RX 1 〇8 2 (that is, to the LLC layer or PEP 1 2 4 for management purposes), once the data is transmitted out of the multiple packet queue FIFO Rxl08 in the exchange environment and is transmitted to the network data BIC 1 0 4 The data is transmitted to the network data system bus 101 through the data path 1 4 4 b. Of course, a single two-way data path can be used instead of the paths 1 4 4 a and 1 4 4 b. It is also noted that the same packet string transmitted from the micro RISC string processor 1 1 4 b to the FIFO RX 1 0 8 can use the full duplex mode -25- (Please read the precautions on the back before filling this page) This paper size Applicable to China National Standard (CNS) A4 specification (210X297 mm) 495671 A7 ______B7_ V. Description of the invention (23) is simultaneously transmitted to the management side micro RISC string processor 1 1 4 c (ie port mirroring), In this way, it is possible to perform management on the packet string received within PEP 1 2 4 while transmitting data to the upper layers. In this embodiment, the flow control BIC 1 2 2 is preferably implemented for transmitting control information and performing data management work. By way of example, in performing network management work, it may be necessary to start from the network data BIC 104. A packet of special information is pulled out (that is, filtered out) from the path of the processed packet. Once the required packet is identified, the packet can then be located within the Parallel Event Processor (PEP) 1 2 4 Filtered by micro RISC string processor 1 1 4 c. The micro RISC string processor 1 1 4 c is also preferably responsible for programming new events, filtering the required packets and buffering the required packets in the appropriate buffers. In addition, the micro RISC string processor 1 1 4 c can start Programmable threshold processing, alarm generation, S MN P / R MON packet transmission, test frame generation, and traffic detection for matrix statistics generation. In addition, a basic set of hard-wired counters It can also be provided to explain various processing operations performed by the micro RISC string processor 1 1 4 c. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. In this embodiment, network management operations are usually used to determine selected network statistics such as frame delivery, operation, number of collisions, traffic characteristics, etc. Advantageously, the simple network management protocol (S NM P) and remote monitoring (R MON) can also be implemented through P E P 1 2 4 in Figure 2. As is well known to those skilled in the art, R Μ Ο Ν monitoring allows network administrators to analyze various traffic statistics and network parameters for comprehensive network error diagnosis, planning, and performance tuning. '-26- (Please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 495671 A7 B7 _ V. Description of the invention (24) Therefore, PEP 1 2 4 includes an innovative packet buffer 1 2 5 for storing appropriate packets, which are implemented by network management protocols such as SNMP and MIMO, by way of example, if a user wants to monitor Through certain packets within the data string processed by the network data B IC 104, the micro RISC string processors 114b and 114c will filter out the required packets which are then stored in the packet buffer 1 25, The command and status register 1 2 6 is also included in the PEP 1 2 4 so that the command register receives the relevant control signals from the management / control bus 1 102 via the flow control B IC 1 2 2 In the embodiment, 1 1 4 b and 1 1 4 c may be the same processing entity. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) The statistical counters 1 2 8 are also displayed, which are responsible for storage that may occur in SUPERMAC Tx controller 118, SUPERMAC management area 117, SUPERMAC Rx controller 12.0, micro RI SC string processor 1 14a, and micro RISC string processor 1 1 4 b special events, so when the packet is processed and the event occurs, the event information is transmitted to the micro RISC The string processor 1 1 4 c is then stored in the statistical counter 1 2 8. In addition, a plurality of programmable counters 1 30 are provided in the PEP 1 2 4 for tracking which may not be currently in use. Definition, but may be defined in the future for new events (that is, programmable events), for example, user-programmed microcodes in micro RISC 1 1 4 a, 1 1 4 b, and 1 1 4 c Generate new events. Fig. 2 B is specially for receiving the packet data from the SUPERMAC RX controller 11 2 0 according to an embodiment of the present invention. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm): 27: 495671 kl B7. 2. Description of the invention (25) A more detailed structure diagram of the implemented micro RISC string processor 1 1 4 b. As described above, the packet data is initially imported from the physical media 1 4 1 into the stream-based media access controller 1 50, and Once the user-defined processing is performed on the micro RISC string processor 1 1 4 b, the processed packet data is transmitted to the multi-packet FIFO Rxl08, which is in communication with the FIFO R x controller 1 12. In one embodiment, In the process, the processed packet is preferably classified into a plurality of priority-changing buffers contained in the multiple packet queue FIF 0 RX 1 0 8. In this way, if a particular packet contains time-sensitive data, That packet will be placed in a higher-priority buffer, and other less time-sensitive data will be placed in other priority-changing buffers. In another embodiment, FIF0RX The controller 1 1 2 may be quite suitable to monitor the traffic density handled by the main CPU. In this embodiment, when the FIFO R χ · controller 1 1 2 determines that the main CPU (such as a servo) is experiencing a period of high communication When receiving data, the received packets will be temporarily stored in FIF0Rxl 08, and then all will be transmitted to the upper layer to reduce the number of interrupts experienced by the main CPU. Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) In one embodiment, the micro RISC serial processor 1 1 4 b is a user-programmable serial packet processing mechanism , Which can quickly analyze the received packet data from beginning to end to create a user-defined data structure that can be appended to the beginning of the received packet before it is sent to the multiple packet queue FIF Before 0 RX 1 0 8, in order to start the user programming operation of the micro RISC string processor 1 1 4 b, the user can configure a designated paper to be executed on the incoming packet data. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -28-495671 A7 __________B7_ V. Description of the invention (26) A software instruction set of the type of analysis and the type of data structure to be created and attached to the individual through the use of a graphical user interface (GUI) In the package, once the instruction set is structured, the software instruction set is compiled into an executable, microcode by the main CPU, and then transmitted to R I S C micro processor unit string 1 1 4 b of the center of integrated circuit hardware into a memory location. It is important for employees of the Central Standards Bureau of the Ministry of Economic Affairs to print consumer cooperatives to understand the packet data processing that occurs on the micro RISC string processor 1 1 4 b to quickly generate a user-defined data structure in a serial form (that is, not to reduce the data transfer rate ) To facilitate the attachment of a defined data structure to a packet that is transmitted to an upper layer, when the upper layer receives a data packet with the attached data structure, the upper layer does not need one byte after another byte (or (Bit by Bit) Scanning is closely combined with the entire bandwidth of the CPU bandwidth to identify the packet data of interest. This is because the user-defined data structure can be programmed to store the index in the upper-layer protocol. Specify the portion of the packet information of interest, or the portion of the data (hash or compressed data) that can be quickly read and processed, without having to spend CPU bandwidth to scan and process the entire packet. Receiving compactly encoded data structure information, the upper layer can quickly send packet data to its intended destination ( (E.g., switch, router, client, server, etc.). In one embodiment, the data structure information may be provided to the host in the form of a> status / explanation symbol, the v'status / explanation symbol. It is then processed by the main packet processing software. As described above, the user can program the micro RISC string processor 1 1 4 b to generate a customized data structure that includes, for example, a pointer to the beginning of the Internet Protocol (IP) header, a finger To transfer control-29- (Please read the notes on the back before filling out this page) This paper size applies Chinese National Standard (CNS) A4 specification (210X29? Mm) 495671 A7 ___ _B7 V. Description of Invention (27) Agreement ( TCP) header index and a pointer to the Simple Mail Transfer Protocol (S M TP) header. Other representative data structures can be programmed to include the packet data itself like IP destination bits. Address and compressed hash data, because the type of data structure and the content of the data structure can be completely programmed by the user, other representative data structures can include `` flags '' data structures, where each bit is programmed to identify A protocol or another protocol, or a data structure in which most bits are encoded to identify different network protocols. FIG. 2C illustrates an alternative embodiment for a micro RISC string processor 1 1 4 b according to an embodiment of the present invention. In this embodiment, the hardware logic of the micro RISC string processor 1 1 4 b The component is divided into the first part (PART I) and the second part (PART II), by splitting the micro RISC string processor 1 1 4 as shown, because the received packet can be processed in PART I and PART II ( (That is, before and after being stored in the multi-packet queue FIF0RX 108), so it can achieve significant processing power. The Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs has an example. This structure provides a built-in `` delay '' to assist in the processing of packet header correction and protocol translation processing. In one embodiment, the packet header correction May include packet splitting and conversion to transform standard Ethernet packets into an asynchronous transfer mode (AT M) unit. Other packet translation functionality may include translation bridges between the Ethernet path, the token ring and FDDI. This split structure also allows the user to program the micro RISC string processor 1 1 4 b to execute and check the core operation after it is output from the multiple packet queue FIF0RX 108. -30- (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy 495671 A7 ____B7_ V. Invention Explanation (28) Because the micro RISC string processor 1 1 41 ^ is a flexible processing unit that can be custom programmed to process incoming packets in a user-defined manner, the micro RISC string processor 1 1 4 b is split. Structures can be used to perform many other user-defined tasks that may instinctively require internal delays. 'It should be understood that these secondary internal delays must not slow down the high speed of the flow-based MAC 1 50 (such as gigabit or Higher) data transfer rate 'Conversely, the internal delay provided by the split structure of Figure 2C only increases the processing rate and data transfer rate by offloading the main CPU from having to check the actual portion of the received packet, of course It should be understood that the split structure of the micro RISC string processor can also be implemented on the transmitting side of the micro RISC string processor 1 1 4 b. 2 · Structure of the micro RISC string processor Figure 3 A is a diagram illustrating a high-level order of a better interaction between the main CPU 3 0 0 and the micro RISC string processor 1 1 4 b according to an embodiment Block diagram, as mentioned above, because the user can program the processing to be executed in the micro RISC string processor 1 1 4 b, so the user is preferably guided to define a type created to identify the type of data structure The contents of the software instruction set and the data structure. To achieve this, the user preferably implements a graphical user interface (GUI) 300 that provides a series of programming-friendly options. The GUI 300 is generated and compiled by a CPU 300. Software instruction set, the compiled software instruction set is then converted into executable microcode. In one embodiment, the microcode will preferably include all types of user programming that identify the type of data structure created (Notes on the back then fill out this page)

本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -31 - 495671 Α7 Β7 五、發明説明(29) 的資訊,並且每一個資料結構的內容將被附加到每一個被 微RI SC串處理機1 14b所接收的封包。 在另一實施例中,一種協定描述語言(P D L )可以 用來定義一類型使用一組具有相當了解之語意的預先定義 之助憶法的協定,代表性之助憶法可以包括I P v · 4 位址、協定ID、802 · 3,以及SNAP —封裝,這 些助憶法也可以被組合而形成一資料結構,一 P D L編譯 器程式然後能夠產生用於微R I S C串處理機的微碼。 經濟部中央標準局員工消費合作社印聚 一般而言,一旦用以實施在微R I S C串處理機 1 14b之內的處理之微碼已經被CPU300所執行, 該微碼被傳送到匯流排(例如1 〇 1 / 1 0 2 ),而後到 匯流排介面控制器(例如1 〇 4 / 1 2 2 ),如在上面的 圖2 A中所顯示,該匯流排介面控制器然後將微碼傳送到 在微R I S C串·處理機之內的硬體儲存位置,於是,封包 資料可以經由網路匯流排1 0 1與管理匯流排1 〇 2兩者 或是其中之一而被同時地(也就是鏡射地)或單獨地傳送 ,在一實施例中,一部分的微碼被傳送到隨機存取記憶體 (R A Μ ) 3 0 2之中,一部分的微碼被傳送到定址內容 記憶體(C A Μ ) 3 3 4之中,而一部分的微碼則被傳送 到比器336之中,一旦RAM302、 CAM334和 比較器3 3 6已經接收到使用者編程的微碼,微R I s C 串處理機1 1 4 b就將被起動並且如上所述地準備接收來 自SUPERMAC 控制器Rxl20的封包資料。 在此實施例中,R A Μ 3 0 2 ‘最好係一 3 2位元寬( -32- (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) 495671 A7 B7 五、發明説明(30) (請先閱讀背面之注意事項再填寫本頁) 或者更寬m 2 5 6之深靜態R A Μ,其包含在位址輸 入端上的輸入暫存器,於是,當位址致能爲高位準時,該 輸入暫存器閂鎖該位址,當然任何其他適合的儲存裝置可 以被實施,其包括一具有預先被編程之微碼指令的唯讀記 憶體或者一 FPGA,進一步地,CAM334最好包括 一組具有相等比較器之1 6個1 6位元的暫存器,以此方 式,即將被編譯之資料被閂鎖在一具有傳送到每一個相等 比較器之輸出的暫存器之中,並且來自該等比較器的旗標 被加總在一起而產生一匹配信號(匹配發現),又進一步 地,CAM3 3 4可以包含一 1 6個1 6位元入口的查閱 表,而且當匹配發生時,對應的入口被輸出。 經濟部中央標準局員工消費合作社印製 圖3 Β係依據本發明的一實施例之在微R I S C串處 理機1 1 4 b內所含之較佳硬體單元的結構圖,假設 RAM3 0 2、*CAM3 3 4、和比較器3 3 6已經接收 到來自CPU30 1之使用者定義的微碼,如在圖3A中 所說明,在R A Μ 3 0 2之內所含之微碼的起始部分被傳 送到一指令暫存器3 0 4,此外,所傳送之微碼最好包含 設定一字元計數3 0 8的微碼資訊,在此實施例中’存在 於字元計數3 0 8中的微碼被組構來辨識在一進來之封包 中所需的字元計數。 藉由不例,每一次當新的封包被微R I S C串處理機 1 1 4 a所接收時,一字元計數器3 0 7將重設於零’ ,而後字元計數器3 0 7開始依序計算每一個從資料路徑 1 1 5 a被接收到管線暫存器級3' 2 3之中的字元,如所 -33- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) 495671 Α7 Β7 五、發明説明(31 ) 顯示,管線暫存器3 2 3最好包括提供強而有力之處理能 力的一、、第一級〃 3 2 4、一 ''第二級〃 3 2 6,以及一 、、第三級〃 3 2 8,藉由示例,如果第一級3 2 4包含第 % 5 7個字元,則第二級3 2 6將包含第5 6個字元,而第 三級3 2 8將包含第,5 5個字元,並且一MUS 3 2 0可 以選擇第5 5個,第5 6個和第5 7個字元的部分來同時 處理,爲了易於了解,管線暫存器級3 2 3的優點將更詳 細地說明於下,當然’應該了解可以使用任何數目的管線 暫存器級。 當被字元計數器3 0 8所辨識之所需的字元計數被接 數到管線暫存器3 2 3之中時’在指令暫存器3 0 4中所 最初儲存的微碼將被傳送到一執行指令暫存器3 0 6,如 所顯示,一加總單元3 0 5最好被組構以連續接收來自字 元計數器3 0 7·之目前的字元計數數目’其通知字元計數 3 0 8是該將微碼傳送到執行指令暫存器3 0 6的時候了 0 經濟部中央標準局負工消費合作社印^ 當此發生時,進入之封包所選擇的字元現在已經被儲 存於管線暫存器級3 2 3的第一級3 2 4之中,在此同時 ,在執行指令暫存器3 0 6中所含的微碼被傳送到控制微 R I S C串處理機11 4 b之目前動作的執行邏輯3 1 2 ,在一實施例中,執行邏輯3 1 2與一 M U X 3 2〇、 一MUX318、一MUX314、一 CRC 單元 33 0 、一 HASH331、一算術邏輯單元(ALU) 332 、C A Μ 3 3 4、比較器3 3 6、‘以及一可編程和核對產 -34 - (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) Α4規格(210x297公釐) 495671 Α7 Β7 五、發明説明(32) 生器333通訊聯絡,如所顯示,CRC330、 HASH331、 ALU332、 CAM334、比較器 3 3 6、以及可編程和核對產生器3 3 3均係分析電腦 3 3 7的一部分,其被組構來遵照爲字元計數3 0 8所辨 識之感興趣的字元(目前封包之感興趣的字元)行事,如 上所述,如果SUPERMAC Rx控制器120將所 接收之封包與C R C欄一起傳送,則C R C 3 3 0最好被 組構在封包被傳送到較上的L L C層之前執行C R C計算 並且剝離該C R C欄,在一實施例中,C R C計算係使用 一產生多項式之3 2位元或1 6位元循環多餘檢驗。 經濟部中央標準局員工消費合作社印繁 以由執行還輯3 1 2所提供之執行命令爲根據,執行 邏輯3 1 2即時編程分析電腦3 1 7以及選擇在第一級 3 2 4中所儲存之辨識的字元或者在第二級3 2 6和第三 級3 2 8中所儲·存的一部分字元之MUX3 2 0,也就是 說,如果部分字元係從每一級來挑選以組構一新的3 2 — 字元,MUX 3 2 0將挑選那個新的3 2位元的字元並且 將它傳送到匯流排3 4 0,一旦所需的字元已經被傳送到 匯流排3 4 0,包括C R C 3 3〇、H A S Η 3 3 1、 ALU332、 CAM334、比較器336、以及可編 程和核對產生器3 3 3之分析電腦即運作由M U X 3 2 0 所選出之3 2位元的字元。 如果使用者想要創造一具有指向目前所挑選之3 2位 元的字元之指標(其可以是表頭的開始)的資料結構,那 麼字元計數將從字元計數器3 0 7‘被傳送到MUX 3 1 8 - 35 - (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) 495671 A 7 B7 五、發明説明(33) 而被輸入到目前的資料結構之中,‘在實施例中’該目前的 資料結構最好將被儲存於資料結構暫存器檔案3 1 6之中 ,一旦爲目前的封包所感興趣之所有資料已經被分析並且 被儲存到資料結構暫存器檔案3 1 6之中’該資料結構就 將附加於從M U X 3 1 4所輸出之封包資料的開頭。 經濟部中央標準局員工消費合作社印製 在另一實施例中,如果使用者想要組構一包括散列資 料(亦即被壓縮的封包資料)的資料結構,那麼該散列資 料將被處理於H A S Η 3 3 1中,而後被傳送到M U X 3 1 8,仍進一步地,使用者可能想要所接收之封包資料 的那個部分(也就是所選擇之3 2位元的字元)被放在由 較上層協定之用於快速參考的資料結構之中,一旦形成入 口於目前的資料結構之中,對於目前的封包而言,C A Μ 3 3 4及比較器3 3 6產生被傳送到編碼器3 1 7和到下 一個位址邏輯3· 1 0的比較控制信號,被提供結編碼器 3 1 7的控制資料最好被用來設定(也就是經由編碼設定 位元)使用者想要建立之資料結構的型態,並且被提供給 下一個位址邏輯之控制資訊被使用來辨識來自R A Μ 3 Ο 2中所儲存之微碼的下一個位址,於是,根據在 C A Μ 3 3 4及比較器3 3 6中所執行的比較,將執行一 分支操作或移動操作,藉由示例,當執行分支操作時,下 一個位址邏輯310將會設定在RAM302中另一個位 址位置,此外,如果執行移動操作,那麼其中一個分析電 腦3 3 7單元將傳送一輸出列MUX 3 1 8並且進入資料 結構暫存器檔案3 1 6之中。 1 -36- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 A7 ——_B7__ 五、發明説明(34) (請先閱讀背面之注意事項再填寫本頁) 在一實施例中,下一個位址邏輯3 1 0包含用以執行 一向量分支的邏輯,該向量分支的邏輯根據從在CAM 3 3 4之內所含之比較器的查閱表中所獲得之結果來辨識 在RAM3 0 2中所儲存之微碼中的下一個位址,進一步 % ’條件性分支可以被用來根據來自比較器3 3 7的輸出 而辨識其本身被儲存在RAM3 0 2之中的微碼之下一個 位址,更進一步地,無條件性分支指令可以直接來自在 RAM3 0 2中所儲存的微碼而不需分析在CAM3 3 4 中所產生的比較結果。 如上所述,一旦分析電腦之C A Μ 3 3 4及比較器 3 3 6已經檢查過所需之3 2位元的字元,比較的結果就 被傳送到下一個位址邏輯3 1 0,在一實施例中,下一個 位址邏輯3 1 0將根據從執行指令暫存器3 0 6所提供之 資訊和從C A Μ· 3 3 4及比較器3 3 6所獲得之所接收的 比較結果來確定在R A Μ 3 0 2中所儲存之微碼中的下一 個位址位置,此時,每一次當一新位址被設定於R A Μ 3 Ο 2中時,那個位址被儲存於程式計數器(P C ) 經濟部中央標準局員工消費合作社印製 3 1 1之中,在此實施例中,程式計數器P C 3 1 1將追 踪在R A Μ 3 0 2中所選擇之最近的位址,於是,在每一 次存取操作到R A Μ 3 0 2中之後,程式計數器P C 3 1 1被持續地更新。 一旦確定在RAM3 0 2之內所含之微碼中的下一個 位置,微碼的那個部分就再次被傳送到指令暫存器3 0 4 和字元計數3 0 8,再次地,字元_計數3 0 8將包含在所 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) -37: 495671 A7 B7 五、發明説明(35 ) 接收的目前封包之內感興趣的下一個字元計數,藉由示例 ,因爲感興趣的最後一個字元爲字元5 7,所以感興趣的 下一個代表性字元可能是字元8 8,在此例中,字元8 8 可以辨識一表頭的開頭,即將被壓縮(例如被散列)之資 料的開頭或是即將被捕獲之資料的開頭,當字元計數器 3 0 7到達封包中的第8 8個字元時,在指令暫存器 3 〇 4中所儲存之微碼被移位到執行暫存器3 0 6之中以 致能對目前被儲存於管線暫存器3 2 3的第一級3 2 4中 之最近所接收之資料字元的執行。 經濟部中央標準局負工消費合作社印製 再次地,執行指令暫存器的內容被傳送到用以編程分 析電腦3 3 7之計算功能的執行邏輯3 1 2,以及多工器 3 2 0、3 1 4和3 1 8,如上所述,所建立之資料結構 最好在被傳送到MUX 3 1 8之前被儲存在資料結構暫存 器檔案3 1 6之·中,一旦用於一特別封包之整個資料結構 被儲存於暫存器3 1 6之中(也就是在已經檢查所有在一 目前封包之內的位置之後),經由管線暫存器級323所 傳送之實際的封包資料被暫時儲存於R A M FIFO 3 2 2之中,如同被執行邏輯3 1 2所控制地,使用者編 程的資料被傳送到M U X 3 1 4之中,在M U X 3 1 4中 ,使用者編程的資料結構被附加於從R A M FIFO 3 2 2所接收之封包資料的開頭。 M U X 3 1 4然後將封包及附加之資料結携輸出到多 重封包佇列F I F〇1 0 8,如上所述地參考圖2 Α — 2 C,一旦對一封包完成該項處理,‘根據由使用者所提供之 -38- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) 495671 A7 ____B7_ 五、發明説明(36) 相同的微碼再次分析下一個封包,但是,如果使用者想要 修改經由圖3 A之G U I 3 0 0在軟體指令設定輸入中所 設定的處理,那麼將依據那些新的參考來處理所接收的封 包,如同稍早所注意的,爲每一封包所創造之資料結構可 以僅包括指向在封包中所選擇之位置的指標,來自封包本 身之資料的部分,來自封包本身之散列的資料,或者包括 其組合,於是,微R I S C串處理機1 1 4 b將依據由使 用者所編程之特別微碼而對不同的封包運作,當如此所說 明之結構被認爲工作的特別良好之同時,應該理解相似的 功能性同樣地能夠使用其他的架構來完成。 經濟部中央標準局員工消費合作社印製 如稍早所述,當較上層接收具有附加之資料結構的封 包時,較上層可以祇讀取他們需要的資料來完成封包路由 安裝而不須實際檢查所有所接收的封包以安置較上層所感 興趣的資訊,應·該注意大部分的時間,每一封包可以有相 同之位於在一所接收的封包之內不同的位元組位置中的表 頭資訊(也就是I P表頭),而因此,一主機之C P U典 型上在其能夠執行任何需要的路由安排及處理之前需要率 若地從頭到尾掃瞄每一封包之大部分的內容,於是,藉由 將使用者定義的資料結構附加在所接收之封包的前面,甚 至大於十億位元以太網路傳送速度可以被達成具有實際上 較少的C P u中斷。 圖4 A係依據本發明的一實施例之在微R I s C串處 理機1 1 4 b之內所執行之較佳處理步驟的綜觀流程圖, 該方法開始於步驟4 0 2,在步驟‘4 0 2中使用者定義的 -39- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明(37 ) 軟體指令集被載入微R I S C串處理機1 1 4 b之中用以 編程對S U P E R M A C 控制器R x 1 2 0所接收之封 包資料所執行的處理,藉由示例,該軟體指令集最好透過 激勵使用者對所接收的封包定義所需之處理的圖形使用者 介面(G U I )之使用而被編程到主接收電腦之中。 於是,一旦使用者已經爲在所接收的封包之內感興趣 的封包定義一資料結構的型態及字元計數位置,而將從該 所接收的封包之內所感興趣的封包建立該資料結構,軟體 指令集就被編譯,一般來講,該軟體指令集被編譯成可執 行微碼,該可執行微碼然後被載入RAM302、 CAM 3 3 4以及比較器3 3 6之中,如同參考上面之圖3 B所 明的,一旦微R I S C串處理機1 1 4 b已經接收到對所 接收之封包所執行之處理指定其方式之所需的微碼,該方 法就將繼續進行’到步驟404,在步驟404中一最初跳 過將會在所接收的封包之內被執行,也就是說,一旦封包 被微R I S C串處理機1 1 4 b所接收,一最初跳入該封 包之中將被執行以決定何種類型的封包已經被接收,藉由 示例,這種封包可以包括特許之貼上標籤的封包,或者任 何其他類型之可以定義於未來的封包通常,該最初跳過可 以從M A C層協定中被確定,因此,對以太網路而言,該 最初跳過可以有大約1 2位元組的跳過長度,當然,如果 使用其他的協定,例如信物環或者F D D I ,其他的最初 跳過長度也一樣可以被實施。 一旦該最初跳過已經被執行於所接收的封包之中,該 石氏張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁) 495671 A7 _ B7 _ 五、發明説明(38) 方法將繼續進行到步驟4 0 6,在步驟4 0 6中,所接收 之封包依據在使用者定義的微碼中所提供之使用者定義的 處理指令而被在微R I S C串處理機1 1 4 b中所含之分 析電腦所檢查,藉由示例,該封包典型上被檢查以確定一 特別表頭或一特別段的資料之字元計數位置,一旦分析電 腦計算出即將被附加於一資料結構之所需的資料,該所需 的資料就被傳送到多工器。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 在封包已經被檢驗於步驟4 0 6中之後,該方法將繼 續進行到步驟4 0 8,在步驟4 0 8中,所辨識之指標、 資料、或散列的資料(或是組合)被儲存在所定義的資料 結構之中,該方法然後將繼續進行到步驟4 1 0,在步驟 4 1 0中,其決定是否在所檢查的封包中有任何更多感興 趣的位置,藉由示例,如果微碼決定有5個獨立之感興趣 的表頭位置,那·麼該方法將繼續進行到步驟4 1 2,在步 驟4 1 2中,微R I S C串處理機1 1 4 a將跳到所接收 之封包中的新位置以回應所接收之封包的檢查,在此實施 例中,新的跳過位置將最好爲由被在微R I S C串處理機 1 1 4 b之內所含的下一個位址邏輯單元所選擇之微碼位 址所確定的位置。 一旦微R I S C串處理機已經到達在所接收之封包中 的新位置,該方法將繼續進行回到步驟4 0 6,在步驟 4 〇 6中,爲在出現於圖3 B之字元計數3 0 8中的微碼 中所辨識之新的字元位置而再度檢查所接收之封包,一旦 已經在步驟4 0 6中爲此新位置檢‘查該封包,該方法將繼 本紙張尺度適用中國國家標準(CNS ) A4規格(210x297公釐) -41 - 495671 A7 ____ B7 五、發明説明(39) 續進行到步驟4 Ο 8,在步驟4 Ο 8中,指標、資料、或 散列的資料再次被儲存於被建立在前述之暫存器檔案中之 所定義的資料結構之中,該方法然後將繼續進行到步驟 4 1 0,在步驟4 1 0中,其決定是否在所檢查之封包中 有任何更多感興趣的位置,假設在所檢查之封包中有更多 感興趣的位置,該方法將再度從頭到尾進行步驟4 1 2、 406、 408、和410,直到所有感興趣的位置都已 經被檢查並且被儲存在由使用者所定義的資料結構之中。 當決定在所檢查之封包中不再有任何感興趣的位置時 (根據由使用者所編程之微碼),該方法將從決定步驟 4 1 0繼續進行到步驟4 1 4,在步驟4 1 4中,如同參 考上面之圖2 Α - 2 C所說明的,其決定是否有任何更多 之從SUPERMAC 控制器Rxl20所接收的封包 ,如果有更多從·3υΡΕΙΙΜΑ〇 控制器Rxl 20所 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 接收的封包,那麼該方法將再度進行到步驟4 0 4,在步 驟4 0 4中,對最近所接收之封包執行最初跳過,該方法 將再次從頭到尾進行步驟4 0 6及4 0 8,在步驟4 0 6 及4 0 8中,爲所接收之封包建立使用者編程的資料結構 ,當然,如果最近所接收之封包係不同於先前的封包,那 麼將依據由使用者所提供之編程對那個新類型的封包執行 處理。 一旦已經爲最近所接收之封包建立資料結構並且在所 檢查之封包中所有感興趣的位置已經被檢查過以建立所需 之資料結構,該方法然後將進行回到決定步驟4 1 4,一 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐1 - 42 - ~ 495671 A7 B7 五、發明説明(40) 旦決定不再有任何SUPERAMC 控制器Rx 1 2〇 被微R I S C串處理機1 1 4 b所接收的封包,該方法就 將結束,應該了解爲一個被微R I S C串處理機1 1 4b 所接收之封包的處理可以和爲另一個封包的處理完全不同 ,即使是依照連續的順序接收封包,因此,爲一封所建立 的資料結構將常常不同於爲另一封包所建立之資料結構( 例如:旗標、欄、指標、散列資料、或者其組合)。 經濟部中央標準局員工消費合作社印製 圖4 B係圖示說明依據本發明的一實施例在載入用以 編程接收之封包資料的所需之軟體指令集中所執行之方法 步驟的更詳細流程圖,一般而言,圖4 B說明用以起動用 於封包資料之接收的微R I S C串處理機1 1 4 b之較佳 步驟,起動開始於步驟4 2 0,在步驟4 2 0中,即將建 立之所需的資料結構格式之型態由使用者編程到軟體指令 集之中,如上所·述,在一較佳實施例中,使用者將最好以 所需型態的資料結構來編程,例如一種指標資料結構,一 種具有封包資料部分的資料結構,一種具有散列資料(也 就是被壓縮)的資料結構,或者他們的組合,最終的資料 結構然後被附加到所接收之封包的前面,當然,如果所用 者需要,該資料結構可以被替代地附加到所接收之封包的 後面,在某些情況下,這對處理封包於整個封包已經被較 上層主機所讀取之後而言可能是有用的,舉例來說,和核 對資訊可以被附加到封包的後面以證實該封包之整體性。 如上所述,最好以一用以編程由微R I S C串處理機 1 1 4 b所執行之處理的電腦圖形1使用者介面來提供給使 -43- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 4.95671 A7 ______ B7 五、發明説明(41 ) (請先閱讀背面之注意事項再填寫本頁) 用者,但是,應該了解到微RISC串處理機114b可 以用任何方式來編程’譬如像例如藉由可以在網路上被傳 送之所編譯的可執行微碼,以此方式,可以從一遙遠的伺 服電腦編程遙遠之主機的微R I S C串處理機。 在使用者以該型態之資料結構格式和爲在步驟4 2 0 中所接收之封包感興趣的所需部分來編程之後,該方法將 進行到步驟4 2 2,在步驟4 2 2中,由使用者所編程之 所需的指令集被編譯以產生所編譯的微碼,一般來講,所 編譯的微碼將包括爲微R I S C串處理機1 1 4 b所需要 來處理進來的封包在他們被傳送到多重封包佇列 FIFO Rx、 108之前的二進位資訊。 經濟部中央標準局員工消費合作社印製 一旦該指令集已經被編譯於步驟4 2 2,該方法就將 繼續進行到步驟4 2 4,在步驟4 2 4中,所編譯的微碼 從主中央處理單元(C P U )被傳送到微R I S C串處理 機1 1 4b之內所包含的硬體,如上所述,微R I S C串 處理機1 1 4 b最好包含一隨機存取記憶體(R A Μ ), 一內容定址記憶體(C A Μ )以及比較器,他們適合於接 收用以處理被微R I S C串處理機1 1 4 b所接收之封包 的所編譯之微碼部分,該方法然後繼續進行到步驟4 2 6 ,在步驟4 2 6中,微R I S C串處理機1 1 4 b被移到 一用以接收封包資料的''準備〃狀態之中。 至此,微R I S C串處理機已經被編程並被起動來對 將被微R IS C串處理機1 1 4 b所接收之封包執行使用 者所定義的處理,因而,只有那些‘由使用者所定義之資料 -44 - 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 A7 _ B7 五、發明説明(42 ) (請先閱讀背面之注意事項再填寫本頁) 結構將被建立於封包的接收期間,直到對被傳送到在微R I s C串處理機1 1 4 b之內所包含的硬體之微碼做一修 改爲止。 圖4 C係圖示說明依據本發明的一實施例與檢驗所接 收之封包相關的方法步驟之更詳細的流程圖,封包檢驗開 始於步驟440,在步驟440中,決定是否封包資料之 下一個3 2位元的字元爲由使用者編程的微碼所辨識之所 需的字元計數資料,如果封包資料之下一個3 2位元的字 元不是所需的字元計數資料,那麼該方法將重返回到決定 是否封包資料之下一個3 2位元的字元爲所需的字元計數 資料,當所需的字元計數資料已經被辨識時,該方法將繼 續進行到步驟4 4 2,在步驟4 4 2中,封包資料之下一 個3 2位元的字元從管線暫存器級中被載入到在微 R I S C串處理·機1 1 4 b之內所包含的分析電腦之中。 經濟部中央標準局員工消費合作社印製 如上所述,分析電腦最好包含一 C R C單元、一散列 單元、一 ALU單元、一 CAM單元、比較器、一加密/ 解密單元、一壓縮/解壓縮單元、以及一可編程和核對產 生器單元,該分析電腦最好接收來自管線暫存器級的資料 而後根據由執行邏輯單元所提供之控制資訊來對那3 2位 元的字元運作,一旦所需之3 2位元的字元已經在步驟 4 4 2中從管線暫存器級被載入分析單元之中,該步驟就 將繼續進行到步驟4 4 4,在步驟4 4 4中,由執行邏輯 執行在執行指令暫存器中所含的微碼來控制對目前之3 2 位元的字元之處理。 ' ^紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) :45二 495671 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(43) 該方法然後將繼續進行到步驟4 4 6,在步驟4 4 6 中’在分析電腦中所獲得之比較結果被傳送到下一個位址 邏輯單元,該方法然後繼續進行到步驟4 4 8,在步驟 4 4 8中,辨識即將被執行之在微碼中的下一個位址,一 旦被辨識出,在微碼中的下一個位址就在步驟4 5 0中從 RAM被傳送到指令暫存器,在步驟4 5 0中,該微碼維 持不動直到在所接收之封包中的下一個微屬決定的字元計 數到達爲止,當在所接之封包中的下一個微碼決定之字元 計數抵達時,在指令暫存器中所含的微碼被傳送到執行指 令暫存器,該方法現在進行到圖4A中的步驟4 0 8,在 步驟4 0 8中,指標、資料、或散列資料被儲存列使用者 定義的資料結構之中。 簡言之,每一次當封包被檢驗時,微R I S C串處理 機1 1 4 b將首·先確定在封包中之正確的3 2位元字元乃 爲所感興趣的,而後將微碼傳送到執行暫存器之中以設定 所選擇之3 2位元字元的處理,該所選擇之3 2位元的字 元從管線暫存器級被載入到分析電腦,每一次當分析電腦 處理所選擇之3 2位元之字元時,一入口被做成於暫時被 儲存在資料結構暫存器檔案中的使用者定義的資料結構之 中’ 一旦對所接收之指定封包完成其資料結構,該資料結 構就被附加到處理過封包的前端,應該理解所有所說明之 資料結構的產生被串列地完成而同時封包被圖2 A - 2 C 之流基M A C 1 5 0所傳送出去。This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -31-495671 Α7 Β7 V. Information of invention description (29), and the content of each data structure will be appended to each micro-RI SC The packets received by the string processor 1 14b. In another embodiment, a protocol description language (PDL) can be used to define a type of agreement using a set of pre-defined memorizing methods with a fairly understood meaning. Representative memorizing methods can include IP v. 4 Address, protocol ID, 802.3, and SNAP—encapsulation. These memorization methods can also be combined to form a data structure. A PDL compiler program can then generate microcode for a micro RISC string processor. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Generally speaking, once the microcode used to implement the processing within the micro RISC string processor 1 14b has been executed by the CPU 300, the microcode is transmitted to the bus (for example, 1 〇 1/102), and then to the bus interface controller (such as 104/122), as shown in Figure 2A above, the bus interface controller then sends the microcode to the The hardware storage location inside the micro RISC string and processor, so the packet data can be simultaneously (that is, mirrored) through the network bus 1 01 and the management bus 1 002 or one of them. Or separately), in one embodiment, a portion of the microcode is transferred to the random access memory (RA M) 3 02, and a portion of the microcode is transferred to the addressing content memory (CA Μ) 3 3 4 and a part of the microcode is transmitted to the comparator 336. Once the RAM302, CAM334 and the comparator 3 3 6 have received the microcode programmed by the user, the micro RI s C string processor 1 1 4 b will be activated and ready to receive from SU as described above Packet information of PERMAC controller Rxl20. In this embodiment, RA Μ 3 0 2 'is preferably 32-bit wide (-32- (Please read the precautions on the back before filling this page) This paper size applies Chinese National Standard (CNS) Α4 Specifications (210X297 mm) 495671 A7 B7 V. Description of the invention (30) (Please read the precautions on the back before filling this page) or a deeper static RA Μ with a wider width of m 2 5 6 which is included on the address input Input register, when the address is enabled to a high level, the input register latches the address, of course, any other suitable storage device can be implemented, which includes a microcode instruction with pre-programmed Read-only memory or an FPGA. Further, the CAM334 preferably includes a set of 16-bit registers with equal comparators. In this way, the data to be compiled is latched in a Sent to the register of the output of each equal comparator, and the flags from these comparators are added together to generate a matching signal (match discovery). Furthermore, CAM3 3 4 may contain a 16 16-bit entry lookup tables, And when a match occurs, the corresponding entry is output. Figure 3 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. B is a micro-RISC string processor 1 1 4 b according to an embodiment of the present invention. The block diagram of the hardware unit assumes that RAM3 0 2, * CAM3 3 4, and comparator 3 3 6 have received user-defined microcode from CPU 30 1 as described in FIG. 3A, at RA M 3 0 The starting part of the microcode contained in 2 is transmitted to an instruction register 3 0 4. In addition, the transmitted microcode preferably contains microcode information setting a character count of 3 0 8 and is implemented here. In the example, the microcode that exists in the character count 3 0 8 is structured to identify the character count required in an incoming packet. By way of example, each time a new packet is processed by the micro RISC string processor When 1 1 4 a is received, a character counter 3 0 7 will be reset to zero ', and then the character counter 3 0 7 starts to sequentially calculate each slave data path 1 1 5 a is received to the pipeline register stage Characters in 3 '2 3, such as -33- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 495671 Α7 Β7 V. The description of the invention (31) shows that the pipeline register 3 2 3 preferably includes a first, a first stage 提供 3 2 4, a `` second '' Level 〃 3 2 6 and first and third levels 〃 3 2 8. By way of example, if the first level 3 2 4 contains the% 5 7th character, then the second level 3 2 6 will contain the 5 6 Characters, while the third level 3 2 8 will contain the 5th, 5th characters, and a MUS 3 2 0 can select the 5th, 5th and 57th characters to be processed simultaneously For ease of understanding, the advantages of the pipeline register stage 3 2 3 will be explained in more detail below, of course 'it should be understood that any number of pipeline register stages can be used. When the required character count recognized by the character counter 3 0 8 is taken into the pipeline register 3 2 3 ', the microcode originally stored in the instruction register 3 0 4 will be transmitted To an execution instruction register 3 0 6, as shown, the one adding unit 3 5 5 is preferably configured to continuously receive the current number of character counts from the character counter 3 0 7 · 'its notification character Count 3 0 8 is the time to transfer the microcode to the execution instruction register 3 0 0 Stored in the first stage 3 2 4 of the pipeline register stage 3 2 3, at the same time, the microcode contained in the execution instruction register 3 0 6 is transmitted to the control micro RISC string processor 11 4 The execution logic of the current action b is 3 1 2. In one embodiment, the execution logic 3 1 2 and a MUX 3 2 0, a MUX318, a MUX314, a CRC unit 33 0, a HASH 331, and an arithmetic logic unit (ALU ) 332, CA Μ 3 3 4, comparator 3 3 6, ', and a programmable and check production -34-(Please read the Please fill in this page for the matters needing attention) This paper size applies Chinese National Standard (CNS) Α4 size (210x297 mm) 495671 Α7 Β7 V. Description of the invention (32) Communication with 333 generator, as shown, CRC330, HASH331, ALU332, The CAM334, the comparator 3 3 6, and the programmable and check generator 3 3 3 are all part of the analysis computer 3 3 7 and are configured to follow the characters of interest identified by the character count 3 0 8 ( Characters of interest in the current packet). As mentioned above, if the SUPERMAC Rx controller 120 transmits the received packet with the CRC field, then the CRC 3 3 0 is preferably configured in the packet to be transmitted to the upper one. The LLC layer previously performed a CRC calculation and stripped the CRC column. In one embodiment, the CRC calculation uses a 32-bit or 16-bit cyclic redundancy check that generates a polynomial. Based on the execution order provided by the execution and reversion series 3 1 2, Yin Fan, an employee consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, executes the logic 3 1 2 to program and analyze the computer 3 1 7 in real time and chooses to store in the first level 3 2 4 Recognized characters or some of the characters MUX3 2 0 stored and stored in the second level 3 2 6 and the third level 3 2 8, that is, if some characters are selected from each level to group Construct a new 3 2 — character, MUX 3 2 0 will pick the new 32-bit character and transfer it to bus 3 4 0, once the required character has been transferred to bus 3 4 0, including CRC 3 3〇, HAS Η 3 3 1, ALU332, CAM334, comparator 336, and programmable and check generator 3 3 3 The analysis computer operates the 3 2 bits selected by MUX 3 2 0 Characters. If the user wants to create a data structure with an index (which can be the beginning of the header) pointing to the currently selected 32-bit characters, the character count will be transmitted from the character counter 3 0 7 ' Go to MUX 3 1 8-35-(Please read the precautions on the back before filling in this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 495671 A 7 B7 V. Description of the invention (33) Entered into the current data structure, 'in the embodiment', the current data structure is preferably stored in the data structure register file 3 1 6 once all the data that is of interest to the current packet has been It is analyzed and stored in the data structure register file 3 1 6 'The data structure will be appended to the beginning of the packet data output from MUX 3 1 4'. Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. In another embodiment, if the user wants to structure a data structure that includes hash data (that is, compressed packet data), the hash data will be processed. In HAS Η 3 3 1 and then transmitted to MUX 3 1 8, still further, the user may want to receive that part of the packet data (that is, the selected 32-bit characters). In the data structure used for quick reference by the upper layer agreement, once the entry is formed in the current data structure, for the current packet, CA M 3 3 4 and comparator 3 3 6 are generated and transmitted to the code. The controller 3 1 7 and the comparison control signal to the next address logic 3. 10 are provided with the control data of the encoder 3 1 7 which is best used to set (ie, set the bit by encoding) the user wants The type of data structure created and the control information provided to the next address logic is used to identify the next address from the microcode stored in RA Μ 3 Ο 2, so according to CA Μ 3 3 4 and comparator 3 3 6 The comparison performed in will execute a branch operation or move operation. By way of example, when a branch operation is performed, the next address logic 310 will be set at another address location in RAM 302. In addition, if a move operation is performed, Then one of the analysis computer units 3 3 7 will send an output row MUX 3 1 8 and enter the data structure register file 3 1 6. 1 -36- (Please read the notes on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 495671 A7 ——_ B7__ V. Description of the invention (34) (Please read first Note on the back page, please fill in this page again.) In one embodiment, the next address logic 3 1 0 contains the logic to execute a vector branch. The logic of the vector branch is based on the information contained in CAM 3 3 4 The result obtained in the comparator's look-up table identifies the next address in the microcode stored in RAM 3 02. Further% 'conditional branches can be used to identify based on the output from the comparator 3 3 7 It itself is stored at an address below the microcode in RAM3 02. Furthermore, the unconditional branch instruction can come directly from the microcode stored in RAM3 0 2 without analysis in CAM3 3 4 The result of the comparison. As mentioned above, once the CA MM 3 3 4 and the comparator 3 3 6 of the analysis computer have checked the required 32-bit characters, the comparison result is transmitted to the next address logic 3 1 0. In an embodiment, the next address logic 3 1 0 will be based on the information provided from the execution instruction register 3 0 6 and the received comparison result obtained from the CA M · 3 3 4 and the comparator 3 3 6 To determine the next address location in the microcode stored in RA Μ 3 02. At this time, every time when a new address is set in RA Μ 3 02, that address is stored in the program. Counter (PC) Printed by the Consumer Co-operative Society of the Central Standards Bureau of the Ministry of Economic Affairs 3 1 1 In this embodiment, the program counter PC 3 1 1 will track the nearest address selected in RA M 3 02, so The program counter PC 3 1 1 is continuously updated after each access operation into the RA M 3 2. Once the next position in the microcode contained in RAM3 0 2 is determined, that part of the microcode is transferred to the instruction register 3 0 4 and the character count 3 0 8 again. Again, the character _ Count 3 0 8 will be included in the paper size applicable Chinese National Standard (CNS) A4 specification (210 × 297 mm) -37: 495671 A7 B7 V. Description of the invention (35) The next word of interest within the current packet received Meta count, by way of example, because the last character of interest is character 5 7, the next representative character of interest may be character 8 8. In this example, character 8 8 can identify one The beginning of the header, the beginning of the data to be compressed (eg, hashed) or the beginning of the data to be captured. When the character counter 3 0 7 reaches the 88th character in the packet, The microcode stored in register 3 04 is shifted to the execution register 3 06 to enable the most recently received currently stored in the first stage 3 2 4 of the pipeline register 3 2 3 Implementation of data characters. Printed by the Central Laboratories of the Ministry of Economic Affairs and Consumer Cooperatives. Once again, the contents of the execution instruction register are transferred to the execution logic 3 1 2 used to program and analyze the computing functions of the computer 3 3 7 and the multiplexer 3 2 0, 3 1 4 and 3 1 8 As mentioned above, the created data structure is preferably stored in the data structure register file 3 1 6 · before being transferred to MUX 3 1 8 and once used in a special packet The entire data structure is stored in the register 3 1 6 (that is, after all positions within a current packet have been checked), the actual packet data transmitted via the pipeline register stage 323 is temporarily stored In the RAM FIFO 3 2 2, as controlled by the execution logic 3 1 2, the user-programmed data is transferred to MUX 3 1 4. In MUX 3 1 4, the user-programmed data structure is appended. At the beginning of the packet data received from the RAM FIFO 3 2 2. MUX 3 1 4 then packs the packet and the additional data together and outputs it to the multiple packet queue FIF 0108, as described above with reference to Figure 2 Α-2 C. Once the processing is completed for a packet, 'as used by -38- provided by the author (please read the precautions on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) 495671 A7 ____B7_ V. Description of Invention (36) Same The microcode analyzes the next packet again, but if the user wants to modify the processing set in the software instruction setting input via GUI 3 0 0 of Figure 3 A, then the received packet will be processed according to those new references, As noted earlier, the data structure created for each packet can include only pointers to the location selected in the packet, the portion of the data from the packet itself, the data from the hash of the packet itself, or its The combination, then, the micro RISC string processor 1 1 4 b will operate on different packets according to the special microcode programmed by the user, and the structure thus described is considered to work At the same time, it should be understood that similar functionality can be accomplished using other architectures as well. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, as mentioned earlier, when the upper layers receive packets with additional data structures, the upper layers can only read the data they need to complete the packet routing installation without actually checking all The received packet is used to place the information that is of higher interest. It should be noted that most of the time, each packet can have the same header information located in different byte positions within a received packet ( (That is, the IP header), and therefore, a host's CPU typically needs to scan most of the contents of each packet from beginning to end before it can perform any required routing arrangements and processing. Therefore, by By appending a user-defined data structure to the front of the received packet, even a transmission speed of more than one gigabit Ethernet can be achieved with practically fewer CP u interrupts. FIG. 4A is a comprehensive flowchart of the preferred processing steps performed within the micro RI s C string processor 1 1 4 b according to an embodiment of the present invention. The method starts at step 4 02, at step ' User-defined -39- in 4 2 (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 495671 Employee Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs Print A7 B7 V. Description of the invention (37) The software instruction set is loaded into the micro RISC string processor 1 1 4 b to program the processing performed on the packet data received by the SUPERMAC controller R x 1 2 0, By way of example, the software instruction set is preferably programmed into the host receiving computer through a graphical user interface (GUI) that motivates the user to define the processing required for the received packet. Thus, once the user has defined the type and character count position of a data structure for a packet of interest within the received packet, and then establishes the data structure from the packet of interest within the received packet, The software instruction set is compiled. Generally speaking, the software instruction set is compiled into executable microcode, which is then loaded into RAM302, CAM 3 3 4 and comparator 3 3 6 as described above. As shown in Figure 3B, once the micro RISC string processor 1 1 4 b has received the required microcode that specifies its method for the processing performed on the received packet, the method will proceed to step 404. In step 404, an initial skip will be performed within the received packet, that is, once the packet is received by the micro RISC string processor 1 1 4 b, an initial jump into the packet will be performed. Executed to determine what type of packet has been received. By way of example, such a packet can include a licensed labeled packet, or any other type of packet that can be defined in the future. Generally, the initial skip can be It is determined from the MAC layer protocol. Therefore, for an Ethernet circuit, the initial skip may have a skip length of about 12 bytes. Of course, if other protocols are used, such as a token ring or FDDI, other The initial skip length can be implemented as well. Once the initial skip has been performed in the received packet, the Shih's scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) 495671 A7 _ B7 _ V. Description of the invention (38) The method will continue to step 4 06. In step 4 06, the received packet is based on the user-defined processing instructions provided in the user-defined microcode. Checked by an analysis computer included in the micro RISC string processor 1 1 4 b. By way of example, the packet is typically checked to determine the character count position of a particular header or a particular segment of data. Once analyzed, The computer calculates the required data to be attached to a data structure, and the required data is transmitted to the multiplexer. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling this page). After the packet has been checked in step 4 6, the method will continue to step 4 8 and in step 4 In 08, the identified indicators, data, or hashed data (or combinations) are stored in the defined data structure, and the method will then proceed to step 4 1 0, in step 4 1 0 , Which determines whether there are any more interesting positions in the inspected packet. By way of example, if the microcode determines that there are 5 independent header positions of interest, then the method will continue to step 4 12. In step 4 1 2, the micro RISC string processor 1 1 4 a will jump to a new position in the received packet in response to the check of the received packet. In this embodiment, the new skip position It will preferably be the location determined by the microcode address selected by the next address logic unit contained in the micro RISC string processor 1 1 4 b. Once the micro RISC string processor has reached a new position in the received packet, the method will continue to step 4 06, and in step 4 06, it will count the characters appearing in Figure 3 B 3 0 Check the received packet again with the new character position identified in the microcode in 8. Once the packet has been checked for this new position in step 406, the method will be applicable to the Chinese standard following this paper size Standard (CNS) A4 specification (210x297 mm) -41-495671 A7 ____ B7 V. Description of the invention (39) Continue to step 4 〇 8, in step 4 〇 8, indicators, data, or hashed data again Is stored in the defined data structure created in the aforementioned register file, the method will then proceed to step 4 10, in step 4 10, it decides whether it is in the inspected packet If there are any more positions of interest, assuming there are more positions of interest in the inspected packet, the method will again perform steps 4 1 2, 406, 408, and 410 from beginning to end until all the positions of interest are reached. Have been checked and stored Among the user-defined data structures. When it is decided that there is no longer any interesting place in the inspected packet (based on the microcode programmed by the user), the method will proceed from decision step 4 1 0 to step 4 1 4 and at step 4 1 In 4, as explained with reference to FIG. 2A-2C above, it determines whether there are any more packets received from the SUPERMAC controller Rxl20, and if there are more packets from the 3 × ΡΕΙΙΜΑ〇 controller Rxl20 Ministry of Economic Affairs Printed by the Consumer Standards Cooperative of the Central Bureau of Standards (please read the notes on the back before filling out this page), then the method will proceed to step 4 0 4 again. In step 4 0 4, the most recently received packet Perform the initial skip, and the method will go through steps 406 and 408 again from beginning to end. In steps 406 and 408, create a user-programmed data structure for the received packet. Of course, if recently The received packet is different from the previous packet, and then processing is performed on that new type of packet according to the programming provided by the user. Once the data structure has been established for the most recently received packet and all the locations of interest in the inspected packet have been checked to establish the required data structure, the method will then proceed back to decision step 4 1 4 The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm 1-42-~ 495671 A7 B7 V. Description of the invention (40) Once it is decided that there will be no more SUPERMC controller Rx 1 2 0 being micro-RISC string processor 1 1 4 b The received packet, the method will end, it should be understood that the processing of a packet received by the micro RISC string processor 1 1 4b can be completely different from the processing of another packet, even in a sequential order Receive packets, so the data structure created for one packet will often differ from the data structure created for another packet (for example: flags, columns, indicators, hash data, or a combination thereof). Central Bureau of Standards, Ministry of Economic Affairs Printed by Employee Consumer Cooperative Figure 4B is a diagram illustrating the software instruction set required to load the packet data for programming and receiving according to an embodiment of the present invention. A more detailed flowchart of the method steps performed. In general, FIG. 4B illustrates the preferred steps for starting the micro RISC string processor 1 1 4 b for receiving the packet data. The start starts at step 4 2 0, In step 4 20, the type of the required data structure format to be created is programmed by the user into the software instruction set. As described above, in a preferred embodiment, the user will preferably use the Need a type of data structure to program, such as an indicator data structure, a data structure with a packet data part, a data structure with hash data (that is, compressed), or a combination of them, and the final data structure is then Append to the front of the received packet. Of course, if the user needs it, this data structure can be appended to the end of the received packet instead. In some cases, this pair of processing packets is already higher than the host. It may be useful after reading, for example, and collation information can be appended to the end of a packet to confirm the integrity of the packet. Fortunately, a computer graphics 1 user interface for programming the processing performed by the micro RISC string processor 1 1 4 b is provided to the ambassador -43- (Please read the precautions on the back before filling this page) This paper size Applicable to China National Standard (CNS) A4 specification (210X297 mm) 4.95671 A7 ______ B7 V. Description of invention (41) (Please read the precautions on the back before filling this page) The user, but should understand the micro RISC string processing Machine 114b can be programmed in any way, such as, for example, by compiling executable microcode that can be transmitted over the network. In this way, a remote host's micro RISC string processor can be programmed from a remote servo computer. . After the user has programmed with the data structure format of this type and the required portion of interest for the packet received in step 4 2 0, the method proceeds to step 4 2 2 and in step 4 2 2 The required instruction set programmed by the user is compiled to generate the compiled microcode. Generally, the compiled microcode will include the packets required for the micro RISC string processor 1 1 4 b to process the incoming packets. They are passed to the multiple packet queue FIFO Rx, binary information before 108. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Once the instruction set has been compiled in step 4 2 2, the method will continue to step 4 2 4. In step 4 2 4, the compiled microcode is downloaded from the main central The processing unit (CPU) is transferred to the hardware contained in the micro RISC string processor 1 1 4b. As mentioned above, the micro RISC string processor 1 1 4 b preferably contains a random access memory (RA Μ) A content addressing memory (CA M) and a comparator, they are adapted to receive the compiled microcode portion used to process the packet received by the micro RISC string processor 1 1 4 b, the method then proceeds to step 4 2 6. In step 4 2 6, the micro RISC string processor 1 1 4 b is moved to a “ready” state for receiving packet data. At this point, the micro RISC string processor has been programmed and activated to perform user-defined processing on packets to be received by the micro RIS C string processor 1 1 4 b. Therefore, only those 'defined by the user Information -44-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297mm) 495671 A7 _ B7 V. Description of the invention (42) (Please read the notes on the back before filling this page) The structure will be established During packet reception, a modification is made to the microcode transmitted to the hardware contained in the micro RI s C string processor 1 1 4 b. FIG. 4C is a more detailed flowchart illustrating the method steps related to inspecting the received packet according to an embodiment of the present invention. The packet inspection starts at step 440. In step 440, it is determined whether or not the packet information is next. The 32-bit characters are the required character count data recognized by the user-programmed microcode. If a 32-bit character under the packet data is not the required character count data, then the The method will return to determining whether a 32-bit character under the packet data is the required character count data. When the required character count data has been identified, the method will continue to step 4 4 2. In step 4 4.2, a 32-bit character under the packet information is loaded from the pipeline register stage to the analysis computer included in the micro RISC string processing machine 1 1 4 b. In. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs As mentioned above, the analysis computer preferably includes a CRC unit, a hash unit, an ALU unit, a CAM unit, a comparator, an encryption / decryption unit, and a compression / decompression Unit, and a programmable and check generator unit, the analysis computer preferably receives data from the pipeline register level and then operates on the 32-bit characters based on the control information provided by the execution logic unit. The required 32-bit characters have been loaded into the analysis unit from the pipeline register stage in step 4 4 2 and this step will continue to step 4 4 4. In step 4 4 4 The execution logic executes the microcode contained in the execution instruction register to control the processing of the current 32-bit characters. ^ Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm): 45 2 495671 Printed by A7 B7, Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (43) The method will then proceed to step 4 46. In step 4 46, the comparison result obtained in the analysis computer is transmitted to the next address logic unit. The method then proceeds to step 4 4 8. In step 4 4 8 the identification is about to be performed. When the next address in the microcode is executed, once it is identified, the next address in the microcode is transferred from the RAM to the instruction register in step 450, and in step 450, The microcode remains unchanged until the character count determined by the next microcode in the received packet arrives. When the character count determined by the next microcode in the received packet arrives, it is stored in the instruction register. The microcode contained in is transmitted to the execution instruction register. The method now proceeds to step 4 8 in FIG. 4A. In step 408, the index, data, or hash data is defined by the store user. Data structure. In short, each time the packet is checked, the micro RISC string processor 1 1 4 b will first determine that the correct 32-bit characters in the packet are of interest, and then send the microcode to Execute the processing in the register to set the selected 32-bit characters. The selected 32-bit characters are loaded from the pipeline register level to the analysis computer, and each time it is processed by the analysis computer In the case of the selected 32-bit characters, an entry is made in a user-defined data structure temporarily stored in a data structure register file. Once the data structure is completed for the specified packet received The data structure is attached to the front end of the processed packet. It should be understood that the generation of all the data structures explained is done in series while the packets are transmitted by the stream-based MAC 1 50 of Figures 2 A-2 C.

圖4 D係說明依據本發明的一實施例在跳過於圖4 A 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) -46 - (請先閱讀背面之注意事項再填寫本頁) 訂 495671 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明(44 ) 的步驟4 1 2中所執行之所接收的封包資料期間所執行之 處理的更詳細流程圖,該方法開始於步驟4 6 0,在步驟 4 6 0中,由微碼所提供之字元計數將一數量的位元組提 供給微R I S C串處理機1 1 4 a以便在所接收之封包中 順向跳躍,藉由示例,如果決定字元4 2包含一 I P表頭 ,而該I P表頭爲使用者想要產生用於資料結構之指標其 所需的位置,那麼微R I S C串處理機1 1 4 a將會該所 有所接收之上達字元5 1的3 2位元字元通過,在其被執 行邏輯所指示來放置一指標到用於第5 2個字元的資料結 構之中。 因此,當所接收之封包的第5 2個字元到達時,該方 法將繼續進行到步驟4 6 2,在步驟4 6 2中,指令暫存 器的內容被移動到執行指令暫存器之中,該執行指令暫存 器依據使用者定·義的設定來指導執行邏輯處理所接收之 3 2位元字元,一旦在步驟4 6 2中執行指令暫存器接收 到指令暫存器內容,該方法就將繼續進行到圖4 A的步驟 406,在步驟406中,就像參考圖4C所說明地檢驗 所接收的封包。 圖5 A到圖5 D顯示可以依據本發明的一實施例爲被 微R I S C串處理機1 1 4 b所接收之封包而可編程地建 立的代表性資料結構,如在圖5 A中所顯示,使用者可以 爲封包A編程一資料結構以包括一指向I P表頭之起始的 指標、一指向T C P表頭之起始的指標、一指向S Μ T P 表頭之起始的指標、一指向應用表頭之起始以及資料部分 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) -47 - (請先閲讀背面之注意事項再填寫本頁) 495671 經濟部中央標準局員工消費合作社印製 A7 _ B7五、發明説明(45) 的指標,此外,該資料結構可以包括像一 I P起源位址、 一 I P終點位址、一起源和終點埠號碼,以及散列資料等 之實際的封包部分。 圖5 B顯示一用於封包B的資料結構,在該封包b中 ,只有指向封包B之特殊部分的指標被辨識,因而,使用 者可以有指向IP表頭、TCP表頭、SMTP表頭等等 的指標,在另一例中,圖5 C顯示一祇具像有一 I p起源 位址、一 I P終點位址和一起源及終點埠號碼的封包資料 部分而沒有包括指標或散列資料之資料結構,在又一例中 ,圖5 D顯示一用於封包D的資料結構,其可以被編程而 僅包括散列資料,如習於此技者所熟知,散列資料係指壓 資料,其典型上被用來減輕在主CPUs上的處理負荷。 圖5 E顯示具有依據本發明的一實施例被附加於每一 封包的前面之柑關的資料結構之封包A到封包D,一般來 講,藉由提供爲較上層協定所感興趣之資訊於封包的前面 ,在小型的資料結構配置中,主C P U不再需要辛苦地從 頭到尾實際地掃瞄及搜索整個封包以便確定表頭的位置或 感興趣的資料。 圖6 A示一用於封包F的資料結構,該封包F已經依 據本發明的一實施例被使用者所編程以包括複數個旗標, 在一實施例中,旗標資料結構最好由可以被用來辨識封包 的類型或其相關層協定之3 2位元所組成,在所提供的例 子中,第一個旗標可以被用來決定進來的封包是否爲一 I P或一網際網路封包交換(I PX)協定’第二個旗標 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -48 - ---------- (請先閱讀背面之注意事項再填寫本頁) 訂 矽5671 kl B7 一 一 _________ 五、發明説明(46) 可以被用來區別一 T C P或一使用者數據電報協定( UD P )協定,以及第三個位元可以被用來區別一 TELNET (亦即,TELNET爲一致能使用者登錄 於一遙遠的裝置)或一 SMTP協定,在另一例中,該資 料結構之最後一個代表性旗標可以被用來決定封包是否爲 一 I C Μ P (亦即網際網路控制訊息協定)封包。 藉由提供此資訊到前端當作資料結構的一部分,主 C P U將沒有必須辛辛地分析進來的封包以決定感興趣之 特殊部分的位置之憂慮,此外,像應用層、表識層、交談 層、以及運輸層等之較上層可以祇排定所接收之封包的路 線而不需向下載入主C PU,如在圖6 Β中所顯示,由使 用者所定義之旗標資料結構隨後藉由微R I S C串處理機 在其被傳送到較上的L L C層之前被附加於封包F的前面 〇 · 經濟部中央標準局員工消費合作社印製 圖7 Α及圖7 Β顯示可以依據本發明的一實施例被使 用者所定義之又一類型的資料結構,在此例中,該資料結 構可以包括如在圖7 A中所顯示地被聚集成多位元欄的複 數個位元’在此例中,欄1可以是一個二位元欄,其可以 被用來辨識當作一 I P、 I P X、一位址解析協定( A R P )·或者一反向位址解析協定(ra R P )的封包, 在另一例中,攔N可以是一三位元欄,其可以被用來辨識 當作一UDP、 TCP、 ICMP、 RSVP的封包,或 者,一網際網路組群管理協定(I GMP )封包的封包, 當然,爲封包F所建構之欄資料結構可以是任何數目之使 -49- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 4^5671 A7 B7 五、發明説明(47 ) 用者定義的位元欄組合,應該了解到上面之辨識的協定組 合僅在本質上具代表性,而且攔資料結構可以被使用者所 編程以定義任何現在或未來的協定,以及任何使用者定義 的組合。 如在圖7 B中所顯示,封包F的資料結構現在被附加 到封包F的前面,再次藉由具有由複數個使用者定義的欄 所組成之資料結構,主C P U可免除必須掃瞄及搜索整個 封包以尋找所需的資訊,其可能被分散在整個封包之中, 更注意到所有的封包具有被儲存在相同位置中之資訊,而 因此傳統的C P U s必須從頭到尾盲目地搜索整個封包來 尋找所需的資訊。 3 ·發送微R I S C串處理機 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 在一較佳實·施例中,如在圖2 A中所顯示之微 R I S C串處理機1 1 4 a包括許多有利的封包資料處理 能力,舉例來講,微R I S C串處理機」1 4 a最好相當 適合以各種類型的表頭來封裝出去的封包以改善封包交換 、路由選擇、或者將以太網路封包轉換成ATM單體,重 要的是切記發送器微R I S C串處理機1 1 4 a也可以被 組構來串列地處理和分析封包資料以及封包的傳送,藉以 有利地避免在傳送方面的延遲,此外,因爲封包封裝和翻 譯操作均完成於身處流基MAC 1 5 0之內的微R I S C 串處理機中,所以減輕了主C P U的實際處理負荷,其有 利地免除分析出去的封包以決定適當的翻譯或封裝之艱苦 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) -50: 495671 A7 ____B7 五、發明説明(48) 的工作。 經濟部中央標準局員工消費合作社印製 圖8係圖示說明依據本發明的一實施例在接收及發送 操作期間發生於流基MA C 1 5 0中之封包處理的方塊圖 800,如上所述,當封包80 2被接收於微RI SC串 處理機1 1 4 b之中時’該封包最好藉由串列地分析每一* 個3 2位元字元以及傳送封包到較上層(或較下層)來處 理,如所顯示,封包802被傳送出微RISC串處理機 1 14b之外,該封包802包括表示具有指標、資料、 散列資料或者其組合之使用者定義的資料結構之附加的索 引8 0 4,在此實施例中,附加的索引8 0 4和封包一起 被傳送到一交換表查閱8 0 6,其最好藉由讀取在包括與 所接收之封包有關的服務的品質(Q 〇 S )之附加的索引 8 0 4中所儲存資料來分析路由選擇要求,藉由示例,如 果剛接收到的封·包資料係一語音封包,那麼此封包可能需 要較高的優先權以避免引入雜訊或分裂性跳過延遲,另一 方面,如果封包係非時間敏感性資料,所接收之封包將被 賦予較低的優先權,其指由交換表查閱8 0 6從附加的索 引8 0 4中被讀取的優先順序,因爲此資訊方便被設置在 封包8 0 2的前面,交換表查閱8 0 6能夠快速地確定路 由選擇要求,而同時使用實際上較慢的主C P U處理(亦 亦其可能減慢傳送速率)。 至此,封包8 0 2和附加的索引8 0 4被傳送到微R I SC串處理機1 1 4a之中,在該微R I S C串處理機 1 1 4 a中,封包資料可以被處理用以經由實體層1 4 0 -51 - (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 A7 B7 五、發明説明(49 ) 而傳送到遙遠的主機(也就是開關、路由器、集線器等等 ),如在圖2A中所顯示,在此例中,交換表查閱8〇6 也可以附加一命令表頭8 0 5,其致能微1^丨S c串處理 機1 1 4 a以決定對封包8 0 2執行何種類型的處理,一 旦微R I S C串處理機1 1 4 a利用命令表頭8 〇 5來建 立所需的封包表頭,該命令表頭8 0 5就將不再被使用, 在此實施例中,微R I S C串處理機1 1 4 a也相當適合 將一封裝表頭8 0 8附加於附加的索引8 0 4和封包資料 802的前面,除此之外,微RISC串處理機114a 也可以被編程來計算一新的循環多餘檢驗(C R C ),其 可以在被傳送到遙遠的主機之前被附加於封包8 0 2的後 面。 在一實施例中,封裝表頭8 0 8可以是一虛擬區域網 路(V L A N )·表頭,其係眾所皆知以根據除了起源及終 點位址以外的複雜線路圖來協助網路過濾通信,在另一例 中,基於條件的過濾也可以藉由微R I S C串處理機而被 執行,因此,V L A N能夠授權網路根據以太網路位址、 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) I P網路號數、或特別的V L A N指定者來執行有效的路 由選擇,在又一實施例中,微R I S C串處理機1 1 4 a 可以被組構以經由封裝表頭8 0 8來執行Clsc◦交換鏈路間 (I S L )標記線路圖。 圖9圖示說明複數個可以在依據本發明的一實施例的 微R I S C串處理機1 1 4 a之內被執行的功能性,如上 所述,微R I S C串處理機1 1 4 a也可以相當適合來提 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) -52 - "" 495671 A7 ________ __B7 五、發明説明(5〇 ) 供一封裝表頭8 0 8,其可以是一在眾所皆知之Cisco標記 線路圖中所使用的I S L表頭,也顯示一可以被微 R I S C串處理機1 1 4 a所計算並且被附加於出去的封 包(串列式)之原始的CRC8 1 0 a欄,也顯示一可以 在被傳送到實體媒體1 4 0之前被附加於在Super MAC控制 器T X 1 1 8中之出去的封包之額外的新CRC 8 1 1, 如上所述。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 在下一例中,微R I SC串處理機1 1 4 a可以相當 適合來執行A T Μ單體分裂和重新組合工作,藉由示例, 當微R I S C串處理機1 1 4 a接收到包含一終點位址( DA) 902、一起源位址(SA) 904,以及資料 9 0 6之原始的以太網路封包時,可以對資料9 0 6、起 源位址9 0 4,以及終點位址9 0 6執行分裂及重新組合 的操作,一旦被分裂,ATM表頭8 0 8 b就可以被附加 於ATM單體的前面,因爲ATM單體通常具有固定的尺 寸,沒有被附加於第一個出去的A T Μ單體之剩餘的資料 將被附加在也與其ATM表頭8 0 8 b本身相組合之隨後 的A T Μ單體。 在又一例中,微R I S C串處理機1 1 4 b可以相當 適合用以執行I P交換,其中I P表頭9 1 0被分析並且 以IP索引912來編索,該IP表頭910被附加於封 包的前面,在此實施例中,微R I S C串處理機1 1 4 a 最好相當適合用來產生IP索引912並且藉由適合的散 列操作來壓縮該I P索引9 1 2,因此,對I P交換而言 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公楚) 495671 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(51 ) ’該索引係起源和終點埠以及起源和終點M A C位址,並 且在某一些情況下,再加上I P表頭其本身的部分之組合 ,以此方式,一小寬度索引(對I P交換而言爲1 2位元 )可以被用來對所有的框貼標籤並且將框交換,如同再一 實施例,所述實施例的微R I S C串處理機也可以有效地 執行I P分裂及I P重新組合以減輕在主機之C P U上的 負荷,在仍一實施例中,I P和核對功能也可以被執行於 在此所述之微R I S C串處理機的各種實施例之內。 如同在此所使用的,參考IEEE802 · 3標準將 可了解到包括所有目前的IEEE802 · 3標準,其包 括:(a) IEEE std802.3u 標準(100 Mbpa —快速以太網路)IEEE802.3u — 1995; (b) IEEE 8 0 2 . 3 z ——工作群草 稿--爲標準(1 〇 〇 〇Mp b s -十億位元以太網路) 所提出的;(c) ISO/IEC 8802 — 3, ANSI/IEEE std 8〇2·3(第 5 版 1 9 9 6 ):以及8 0 2 · 1 D橋接標準,所有以上所鑑 定的標準在此均當作參考而被倂入。 本發明可以利用任何型式的積體電路邏輯或軟體驅動 之電腦實施的操作來實施,藉由.示例,依據本發明的一實 施例’一種硬體描述語言(H D L )系列的設計及綜合程 式可以被用來設計爲適當地執行資料和控制操作所需之矽 級電路,藉由示例,一種根據可由New Y〇rk,New York之 I E E E所提供的標準之VHD L ®硬體描述語言可以被 本纸張尺度適用中國國家標準(CNS ) A4規格( ^wi IT (請先閱讀背面之注意事項再填寫本頁) 495671 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(52 ) 用來設計一適當的矽級電路圖,雖然可以利用任何適合的 設計工具,另一種電路圖工作可以包括可由Santa Clara, California 的 Cadence Design Systems, Inc.所提供之硬體描 述語言''Venlog ® 〃工具。 本發明也可以使用各種涉及在電腦系統中所儲存之資 料的電腦實施操作,這些操作係需要實際量之實際運作的 操.作,雖然非必要的,通常這些量採取能夠被儲存、轉移 、組合、比較,否則被運作之電氣信號或磁性信號的形式 ,此外,所執行之運作常常指像產生、辨識、決定、或比 較等項目。 任何在此所述而形成本發明之部分的操作皆爲有用的 機器操作,本發明也與用以執行這些操作的元件或裝置有 關,本裝置可以爲所需之目的而被特別地建構,或者本裝 置可以是由在電腦中所儲存之電腦程式所選擇性地起動或 組構的通用電腦,尤其,各種通用機器可以與依據在此的 教旨所寫的電腦程式一起被使用,或者建構一種更專業化 的裝置來執行所需之操作可能是更方便的事,對本發明之 代表性結構被說明於下。 圖1 0係依據本發明用以實施本處理之代表性電腦系 統1 0 0 0的方塊圖,電腦系統1 〇 〇 〇包括一數位電腦 1 0 0 2、一顯示幕(或監視器)1 〇 〇 4、一列印機 1006、一軟式磁機1008,一硬式磁碟機1010 、一網路介面1 〇 1 2、以及一鍵盤1 0 1 4。數位電腦 1 〇 〇 2包括一微處理機1 0 1 6、一記憶體匯流排 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ 297公釐) -55- --------衣-- (請先閲讀背面之注意事項再填寫本頁)Figure 4D is an illustration according to an embodiment of the present invention. Skip to Figure 4A. The paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) -46-(Please read the precautions on the back before filling in this Page) Order 495671 Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Invention Note (44) Step 4 1 2 Performed in more detailed flowchart of the processing performed during the received packet information, the method Beginning at step 460, in step 460, the number of bytes provided by the microcode provided by the microcode is provided to the micro RISC string processor 1 1 4a to forward in the received packet Jump, by way of example, if the decision character 4 2 contains an IP header, and the IP header is the position where the user wants to generate an index for the data structure, then the micro RISC string processor 1 1 4 a passes all the 32-bit characters up to the character 51, and places an index into the data structure for the 52nd character as instructed by the execution logic. Therefore, when the 52nd character of the received packet arrives, the method will continue to step 4 2 2. In step 4 6 2 the contents of the instruction register are moved to the execution instruction register. In the execution instruction register, the 32-bit characters received by the execution logic processing are guided by the user-defined and defined settings. Once the execution of the instruction register in step 4 2 2 receives the contents of the instruction register. The method will then proceed to step 406 of FIG. 4A. In step 406, the received packet is checked as explained with reference to FIG. 4C. 5A to 5D show representative data structures that can be programmatically established for packets received by the micro RISC string processor 1 1 4 b according to an embodiment of the present invention, as shown in FIG. 5A The user can program a data structure for packet A to include a pointer to the start of the IP header, a pointer to the start of the TCP header, a pointer to the start of the SMTP header, and a pointer Application of the header and the data part This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) -47-(Please read the precautions on the back before filling this page) 495671 Employees of the Central Standards Bureau of the Ministry of Economic Affairs Consumer Cooperatives printed A7 _ B7 V. Indicators of Invention Description (45). In addition, the data structure can include information such as an IP origin address, an IP destination address, a source and destination port number, and hash information. The actual packet part. Figure 5B shows a data structure for packet B. In this packet b, only the pointers pointing to the special part of packet B are identified. Therefore, the user can point to the IP header, TCP header, SMTP header, etc. In another example, FIG. 5C shows a packet data portion that has an IP origin address, an IP destination address, and a source and destination port number without including the indicator or hash data. Structure. In yet another example, FIG. 5D shows a data structure for packet D, which can be programmed to include only hash data. As is familiar to those skilled in the art, hash data is shiatsu data, which is typically It is used to reduce the processing load on the main CPUs. FIG. 5E shows a packet A to a packet D having a data structure attached to the front of each packet according to an embodiment of the present invention. In general, by providing information of interest to a higher-level protocol in a packet Previously, in a small data structure configuration, the main CPU no longer needs to physically scan and search the entire packet from beginning to end in order to determine the position of the header or the data of interest. FIG. 6A shows a data structure for a packet F which has been programmed by a user to include a plurality of flags according to an embodiment of the present invention. In one embodiment, the flag data structure is preferably composed of Consists of 32 bits used to identify the type of packet or its related layer protocol. In the example provided, the first flag can be used to determine whether the incoming packet is an IP or an Internet packet. Exchange (I PX) Agreement 'The second paper size of the specimen is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -48----------- (Please read the notes on the back first (Fill in this page again.) Order silicon 5671 kl B7 one by one _________ 5. Description of the invention (46) can be used to distinguish between a TCP or a user data telegram protocol (UD P) agreement, and the third bit can be used To distinguish between a TELNET (that is, TELNET is a user that can log in to a remote device) or an SMTP protocol. In another example, the last representative flag of the data structure can be used to determine whether the packet is a IC Μ P (i.e. Internet Control Message Agreement) packet. By providing this information to the front end as part of the data structure, the main CPU will not have to worry about analyzing the incoming packets to determine the location of the particular part of interest. In addition, like the application layer, the recognition layer, the conversation layer The upper layers, such as the transport layer, can only schedule the route of the received packets without downloading the main CPU. As shown in Figure 6B, the flag data structure defined by the user is then used by The micro RISC string processor is attached to the front of the packet F before it is transmitted to the upper LLC layer. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Figures 7A and 7B show that an implementation according to the invention Example Another type of data structure defined by the user. In this example, the data structure may include a plurality of bits that are grouped into a multi-bit column as shown in FIG. 7A. In this example, Column 1 can be a two-bit column, which can be used to identify packets that are treated as an IP, IPX, one-bit address resolution protocol (ARP), or a reverse address resolution protocol (ra RP). In one example, N can be a three-bit field, which can be used to identify a packet as a UDP, TCP, ICMP, RSVP, or an Internet Group Management Protocol (I GMP) packet. Of course, it is a packet. The data structure of the column constructed by F can be any number. -49- (Please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 4 ^ 5671 A7 B7 V. Description of the Invention (47) The user-defined bit-column combination should understand that the above-identified agreement combinations are only representative in nature, and the data structure can be programmed by the user to define any present or future Agreement, and any user-defined combination. As shown in Figure 7B, the data structure of packet F is now appended to the front of packet F. By having a data structure composed of multiple user-defined columns again, the main CPU can eliminate the need to scan and search The entire packet to find the required information, which may be scattered throughout the packet, but also notice that all packets have the information stored in the same location, and therefore the traditional CPU s must blindly search the entire packet from beginning to end To find the information you need. 3 · Send micro RISC string processor Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) In a preferred embodiment, as shown in Figure 2A The micro RISC string processor 1 1 4 a includes many advantageous packet data processing capabilities. For example, the micro RISC string processor "1 4 a is best suited to encapsulate packets with various types of headers to improve packet exchange. , Routing, or converting Ethernet packets into ATM cells. It is important to remember that the transmitter micro RISC string processor 1 1 4 a can also be configured to process and analyze packet data and packet transmission in series. This advantageously avoids delays in transmission. In addition, because the packet encapsulation and translation operations are completed in the micro RISC string processor located within the stream-based MAC 150, the actual processing load of the main CPU is reduced, which Advantageously eliminates the arduousness of analyzing the packets to determine proper translation or packaging. This paper size applies Chinese National Standard (CNS) A4 specifications (210X 297 mm) -50: 495671 A7 ____B 7 V. Work of Invention Description (48). Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Figure 8 is a block diagram 800 illustrating packet processing that occurs in the stream-based MA C 150 during a receive and send operation according to an embodiment of the present invention, as described above When the packet 80 2 is received in the micro RI SC string processor 1 1 4 b 'The packet is best analyzed by serially analyzing each * 32-bit characters and transmitting the packet to the upper layer (or (Lower layer) to process, as shown, packet 802 is transmitted outside the micro RISC string processor 1 14b, the packet 802 includes an additional representation of a user-defined data structure with indicators, data, hash data, or a combination thereof The index 8 0 4 in this embodiment is transmitted together with the packet to an exchange table to look up 8 0 6, which is preferably read by including the service related to the received packet. Quality (Q 〇) additional data stored in the index 804 to analyze routing requirements. By way of example, if the newly received packet data is a voice packet, then this packet may need a higher priority Right to avoid introducing noise or Disruptive skip delay. On the other hand, if the packet is not time-sensitive, the received packet will be given a lower priority. This means that the exchange table is looked up 8 0 6 from the additional index 8 0 4 The priority of reading is because this information is conveniently set in front of the packet 8 0 2 and the exchange table lookup 8 0 6 can quickly determine the routing requirements while using the actually slower main CPU processing (also possible). Slow down the transfer rate). At this point, the packet 8 0 2 and the additional index 8 0 4 are transmitted to the micro RI SC string processor 1 1 4a. In the micro RISC string processor 1 1 4 a, the packet data can be processed to pass through the entity. Layer 1 4 0 -51-(Please read the notes on the back before filling out this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 495671 A7 B7 V. Description of the invention (49) Remote hosts (ie switches, routers, hubs, etc.), as shown in Figure 2A. In this example, the exchange table lookup 806 can also be attached with a command header 8 0 5, which enables micro 1 ^ 丨 Sc string processor 1 1 4 a to determine what type of processing is performed on the packet 8 0 2. Once the micro RISC string processor 1 1 4 a uses the command header 8 0 5 to establish the required packet header. The command header 8 0 5 will no longer be used. In this embodiment, the micro RISC string processor 1 1 4 a is also quite suitable for adding a package header 8 0 8 to the additional index 8 0 4 and In front of the packet data 802, in addition, the micro RISC string processor 114a can also be programmed to calculate a new cycle It is attached to the surface of the packet 802 before the excess test (C R C), which can be transferred to the remote host. In one embodiment, the encapsulation header 808 may be a virtual area network (VLAN) header, which is well known to assist network filtering based on complex wiring diagrams other than the origin and destination addresses. Communication, in another example, condition-based filtering can also be performed by a micro RISC string processor. Therefore, VLAN can authorize the network to print based on the Ethernet address Read the notes on the back before filling this page) IP network numbers, or special VLAN designators to perform effective routing. In another embodiment, the micro RISC string processor 1 1 4 a can be configured Clsc is performed via the encapsulation header 808. Switched Link-to-Interlink (ISL) is used to mark the circuit diagram. FIG. 9 illustrates the functionality that can be performed within a micro RISC string processor 1 1 4 a according to an embodiment of the present invention. As described above, the micro RISC string processor 1 1 4 a can also be equivalent Applicable to mention the paper size Applicable to China National Standard (CNS) A4 specification (210X 297 mm) -52-" " 495671 A7 ________ __B7 V. Description of the invention (50) Provide a package header 8 0 8 It can be an ISL header used in the well-known Cisco labeled circuit diagrams, and also shows a packet (serial) that can be calculated by the micro RISC string processor 1 1 4 a and appended The original CRC8 1 0 a column also shows an additional new CRC 8 1 1 that can be attached to the packet going out in the Super MAC Controller TX 1 1 8 before being transmitted to the physical media 1 4 0, as shown above Described. Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling this page) In the next example, the micro RI SC string processor 1 1 4 a can be quite suitable for performing AT Μ monomer splitting and reassembly Work, by way of example, when the micro RISC string processor 1 1 4 a receives an original Ethernet packet containing a destination address (DA) 902, a source address (SA) 904, and data 9 06 You can perform splitting and recombining operations on the data 9 06, the origin address 9 0 4 and the end address 9 06. Once split, the ATM header 8 0 8 b can be added to the ATM unit. Previously, because ATM cells usually have a fixed size, the remaining data that is not attached to the first ATM cell that is going out will be appended to the subsequent AT M that is also combined with its ATM header 8 0 8 b itself. monomer. In yet another example, the micro RISC string processor 1 1 4 b can be quite suitable for performing IP exchange, in which the IP header 9 10 is analyzed and indexed with an IP index 912, and the IP header 910 is attached to the packet Previously, in this embodiment, the micro RISC string processor 1 1 4 a is preferably quite suitable for generating the IP index 912 and compressing the IP index 9 1 2 by a suitable hashing operation. In terms of this paper standard, the Chinese National Standard (CNS) A4 specification (210X 297 Gongchu) 495671 Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (51)' The index is the origin and destination port and origin And destination MAC address, and in some cases, plus the IP header itself, in this way, a small width index (12 bits for IP exchange) can be used Label all the frames and exchange the frames. As in another embodiment, the micro RISC string processor in this embodiment can also effectively perform IP splitting and IP recombination to reduce the load on the host's CPU. Examples Variety, I P, and checking functions may be performed within the micro herein R I S C string handler embodiment of the embodiment. As used herein, reference to the IEEE802 · 3 standard will be understood to include all current IEEE802 · 3 standards, including: (a) IEEE std802.3u standard (100 Mbpa — Fast Ethernet) IEEE802.3u — 1995 ; (B) IEEE 8 0 2 .3 z-draft working group-proposed for the standard (1000Mp bs-gigabit Ethernet); (c) ISO / IEC 8802-3, ANSI / IEEE std 802 · 3 (5th edition 1 996): and 802 · 1 D bridge standards. All the standards identified above are incorporated herein by reference. The present invention can be implemented by using any type of integrated circuit logic or software-driven computer-implemented operations. By way of example, according to an embodiment of the present invention, a design and integrated program of a hardware description language (HDL) series can Used to design silicon-level circuits required to properly perform data and control operations, by way of example, a VHD L ® hardware description language based on standards provided by the IEEE, New York, New York, can be used Paper size applies to Chinese National Standard (CNS) A4 specifications (^ wi IT (please read the notes on the back before filling this page) 495671 Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (52) To design an appropriate silicon-level circuit diagram, although any suitable design tool can be used, another circuit diagram job can include a hardware description language `` Venlog® '' tool provided by Cadence Design Systems, Inc. of Santa Clara, California. The present invention can also be implemented using a variety of computers involving data stored in a computer system. These operations require The actual operation of actual quantities. Although not necessary, these quantities usually take the form of electrical or magnetic signals that can be stored, transferred, combined, or compared. Otherwise, the operations performed are often referred to as Generate, identify, decide, or compare items. Any operation described herein that forms part of the invention is a useful machine operation, and the invention also relates to elements or devices used to perform these operations. The device may be The purpose is specially constructed, or the device may be a general-purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general-purpose machines may be connected with It may be more convenient to use computer programs written together, or to construct a more specialized device to perform the required operations. The representative structure of the present invention is described below. Fig. 10 is implemented according to the present invention. A block diagram of a representative computer system 1000 in this process. Computer system 1000 includes a digital computer 100 and a display screen (or Monitor) 1 004, a printer 1006, a soft magnetic drive 1008, a hard disk drive 1010, a network interface 1 〇2, and a keyboard 1014. The digital computer 1 002 includes A microprocessor 1 0 1 6. A memory bus The paper size applies to the Chinese National Standard (CNS) Α4 specification (210 × 297 mm) -55- -------- clothing-(Please read first (Notes on the back then fill out this page)

、1T 495671 A7 B7 五、發明説明(53 ) 1〇18、隨機存取記憶體(RAM) 1020、唯讀記 憶體(R〇Μ ) 1 〇 2 2、一周邊匯流排1 〇 2 4、以及 一鍵盤控制器1 〇 2 6。該數位電腦1 〇 〇 2可以爲個人 電腦(例如I Β Μ相容的個人電腦、Macintosh電腦或 Macintosh相容的電腦)、工作站電腦(例如Sun Microsystems或Hewlett-Packard工作站)、或其他類型的電 腦。 微處理機1 0 1 6係控制電腦系統1 〇 〇 〇之操作的 通用數位處理機,該微處理機1 〇 1 6能夠是單晶片處理 機或者能夠以多個組件來實施,利用從記憶體所尋回的指 令,微處理機1 0 1 6控制輸入資料及輸出資的接收和運 作並且將資料顯示於輸出裝置之上,依據本發明,該微處 理機1 0 1 6的一項特別的功能在於協助封向處理及網路 管理工作。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 記憶體匯流排1 0 1 8爲微處理機1 0 1 6所使用來 存取 RAM1020 及 ROM1022 ,RAM1020 被微處理機1 0 1 6所使用來當作通用儲存區域以及當作 暫存記憶體,並且也能夠被用來儲存輸入資料及處理過的 資料,R0M1 〇 2 2可以被用來儲存隨著微處理機 1 0 1 6之後的指令或程式以及其他的資料。 周邊匯流排1 0 2 4被用來存取爲數位電腦1 0 0 2 所用的輸入、輸出、以及儲存裝置,在所述之實施例中, 這些裝置包括顯示幕1004、列印機裝置1006、軟 式磁碟機1 0 0 8、硬式磁碟機1 0 1 0、以及網路介面 本纸張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) :56 . 495671 A7 B7 五、發明説明(54 ) 1 0 1 2。鍵盤控制器1 0 2 6被用來接收來自鍵盤 1 0 1 4的輸入並且將爲每一個被按壓之鍵所解碼的信號 在匯流排1 0 2 8上傳送到微處理機1 0 1 6。 顯示幕1 0 0 4係顯示透過周邊匯流排1 0 2 4而由 微處理機1 0 1 6所提供之影像或者由在電腦系統 1 0 0 0中之其他組件所提供之影像的輸出裝置。當列印 機裝置1 0 0 6當作列印機操作時,其提供影像於一張紙 上或相似的表面上,其他像繪圖機、排字機等等之輸出裝 置可以被用來代替該列印機裝置1 0 0 6或者當作另外的 輸出裝置。 軟式磁碟機1 0 0 8和硬式磁碟機1 0 1 0能夠被用 來儲存各種類型的資料,軟式磁碟機1 0 0 8協助傳送這 樣的資料到其他的電腦系統,而硬式磁碟機則允許對大量 的儲存資料做快速存取。 經濟部中央標準局員工消費合作社印製 微處理機1 0 1 6和操作系統一起運作以執行電腦碼 及產生和使用資料,該電腦碼和資料可以存在於R A Μ 1020、 ROM1022、或硬式磁碟機1010之上 ,電腦碼和資料也可以存在於可移動式程式媒體之上並且 當需要時可以被載入或裝設在電腦系統1 0 〇 〇之上,可 移動式程式媒體包括例如CD — ROM、PC — CARD 、軟式磁碟以及碟帶。 網路介面1012被用來發送及接收在被連接到其他 電腦系統的網路上之資料,由微處理機1 0 1 6所施行之 介面卡或類似之裝置和適當的軟體可以被用來連接該電腦 -57- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 A7 B7 五、發明説明(55 ) 系統1 0 0 0到一存在之網路並且依據標準協定來傳送資 料。 鍵盤1 0 1 4被使用者用來輸入命令及其他指令到電 腦系統1 0 0 0,其他類型的使用者輸入裝置也可以被用 來與本發明相連結,舉例來說,像電腦滑鼠、軌跡球、指 示筆、或圖形輸入板的指示裝置能夠被用來操縱在通用電 腦之螢幕上的指示標。 本發明也能夠被具體化成爲在電腦可讀式媒體上的電 腦可讀碼,該電腦可讀式媒體係任何能夠儲存可以隨後被 電腦系統所讀取之資料的資料儲存裝置,電腦可讀式媒體 的例子包括唯讀記憶體、隨機存取記憶體、〇〇-R〇M s、磁帶、光學資料儲存裝置、電腦可讀式媒體也 可以分布在連接電腦系統的網路之上而使得電腦可讀碼以 分散的方式來儲存及執行。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 雖然前述之發明已經爲了淸楚地了解的目的而做某種 程度詳細地說明,在附加的申請專利範圍之內可以實行某 些改變及修正將是明顯的,應該了解上面所述之各種處理 功能能夠以矽當作硬體積體電路’封包的專用積體電路( ASICs),或者當作可以被儲存於及從任何適合之儲 存媒體中檢索的軟體碼(例如C及C + +編程碼)兩種方式 來實施,藉由示例’這樣的儲存媒體可以包括磁碟機、硬 式磁碟機、軟式磁碟、伺服電腦、遙遠的網路化電腦、等 等。 除此之外,應該了解上面所述之特色及功能性被完全 本紙張尺度適用中國國家標準(CNS ) A4規格(210x297公釐) -58 - 495671 A7 ______ _B7 五、發明説明(56 ) 向下相容於1〇Mb p s以太網路系統和1〇〇Mb p s 快速以太網路系統及相關的非同步傳送模式(A Τ Μ )系 統、F D D I、信物環或者任何、、串流〃導向的通訊系統 (例如T1/DS1、SO NET等等),當然,上述之 實施例也適用於交換的、非交換的、和全雙工/半雙工網 路系統’於是,本發明實施例被認爲係例舉性而非限制性 的’並且本發明本不受限於在此所提出的詳細內容,但可 以在附加的申請專利範圍及其相等之物的範疇之內做改變 t V m i am m_l mi mi ·ϋϋ ϋϋ ϋϋ ϋϋ·- —·ϋ .^ϋ— Hi·—· - Μ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製1T 495671 A7 B7 V. Description of the invention (53) 1018, random access memory (RAM) 1020, read-only memory (ROM) 1 〇2, a peripheral bus 1 〇2 4, and A keyboard controller 1 〇 2 6. The digital computer 100 may be a personal computer (such as an IB compatible personal computer, a Macintosh computer, or a Macintosh compatible computer), a workstation computer (such as a Sun Microsystems or Hewlett-Packard workstation), or another type of computer . The microprocessor 106 is a general-purpose digital processor that controls the operation of the computer system 1000. The microprocessor 106 can be a single-chip processor or can be implemented in multiple components, using a slave memory The retrieved instructions, the microprocessor 1 0 1 6 controls the reception and operation of input data and output data and displays the data on the output device. According to the present invention, a special feature of the microprocessor 1 0 16 The function is to assist in routing processing and network management. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Memory bus 1 0 1 8 is used by microprocessor 1 0 1 6 to access RAM1020 and ROM1022. RAM1020 is The microprocessor 1 0 1 6 is used as a general storage area and as temporary storage memory, and can also be used to store input data and processed data. ROM1 〇 2 2 can be used to store Instructions or programs after processor 1 0 1 6 and other data. The peripheral bus 1 0 2 4 is used to access input, output, and storage devices used by the digital computer 1 0 2. In the embodiment described, these devices include a display screen 1004, a printer device 1006, Soft disk drive 1 0 8, hard disk drive 1 0 10, and network interface The paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm): 56.495671 A7 B7 V. Invention Explanation (54) 1 0 1 2. The keyboard controller 1 0 2 6 is used to receive input from the keyboard 1 0 1 4 and upload the signal decoded for each key pressed on the bus 1 0 2 8 to the microprocessor 1 0 1 6. The display screen 1 0 0 4 is an output device that displays the image provided by the microprocessor 1 10 16 or the image provided by other components in the computer system 1 0 0 through the peripheral bus 1 2 4. When the printer device 10 is operated as a printer, it provides images on a piece of paper or a similar surface. Other output devices such as plotters, typewriters, etc. can be used instead of the printer. Machine device 1 0 6 or as another output device. The floppy disk drive 1 0 8 and the hard disk drive 1 0 1 0 can be used to store various types of data. The floppy disk drive 1 0 8 assists in transferring such data to other computer systems, while the hard disk drive The machine allows quick access to large amounts of stored data. The Consumer Standards Cooperative printed by the Central Bureau of Standards of the Ministry of Economic Affairs prints microprocessors 1 10 and 6 to work with the operating system to execute computer code and generate and use data. The computer code and data can be stored in RAM 1020, ROM 1022, or hard disk. On computer 1010, computer code and data can also exist on removable program media and can be loaded or installed on computer system 100 as needed. Removable program media includes, for example, CDs — ROM, PC — CARD, floppy disk and tape. The network interface 1012 is used to send and receive data on the network connected to other computer systems. An interface card or similar device implemented by the microprocessor 10 16 and appropriate software can be used to connect to the Computer-57- (Please read the precautions on the back before filling out this page) This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 495671 A7 B7 V. Description of the invention (55) System 1 0 0 0 to An existing network and transmits data according to standard protocols. The keyboard 1 0 1 4 is used by the user to input commands and other instructions to the computer system 1 0 0. Other types of user input devices can also be used to connect with the present invention. For example, like a computer mouse, A pointing device of a trackball, stylus, or tablet can be used to manipulate the pointer on the screen of a general-purpose computer. The present invention can also be embodied as a computer-readable code on a computer-readable medium, which is any data storage device capable of storing data that can be subsequently read by a computer system. Examples of media include read-only memory, random access memory, 〇〇-ROMs, magnetic tapes, optical data storage devices, computer-readable media can also be distributed over the network connected to the computer system to make the computer The readable code is stored and executed in a decentralized manner. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling out this page) Although the aforementioned invention has been explained in some detail for the purpose of understanding, the scope of additional patent applications It will be obvious that certain changes and modifications can be implemented within it. It should be understood that the various processing functions described above can use silicon as hard volume circuit 'packages' dedicated integrated circuits (ASICs), or as can be stored in And software code retrieved from any suitable storage medium (such as C and C ++ programming code), by way of example, such storage media may include disk drives, hard drives, and floppy disks , Servo computer, remote networked computer, etc. In addition, you should understand that the features and functionalities mentioned above are fully applicable to the Chinese standard (CNS) A4 size (210x297 mm) of this paper size -58-495671 A7 ______ _B7 V. Description of the invention (56) Down Compatible with 10Mb ps Ethernet system and 100Mb ps fast Ethernet system and related asynchronous transmission mode (ATM) system, FDDI, token ring or any, stream-oriented communication Systems (such as T1 / DS1, SO NET, etc.). Of course, the above embodiments are also applicable to switched, non-switched, and full-duplex / half-duplex network systems. Therefore, the embodiments of the present invention are considered It is exemplary rather than restrictive 'and the present invention is not limited to the details presented herein, but may be changed within the scope of additional patent applications and their equivalents t V mi am m_l mi mi · ϋϋ ϋϋ ϋϋ-·-— · ϋ. ^ ϋ— Hi · — ·-Μ (Please read the precautions on the back before filling out this page) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs

-59- 本纸張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐)-59- This paper size applies to China National Standard (CNS) Α4 specification (210 × 297 mm)

Claims (1)

495671 A8 B8 C8 D8 々、申請專利範圍 第87 101 838號專利申請案 中文申請專利範圍修正本 民國90年12月修正 ^•'"r 1·一種用以處理接收自一實體層之封包資料的方法, 該處理被串列地執行而同時發送封包到一較上層,其包括: V,, // rs:i:· (請先閲讀背面之注意事項再填寫本頁) (a )載入一用以定製編程接收自該實體層之封包資料 的處理之指令集; (b)決定接收自該實體層之封包資料的類型; (c )根據該指令集'來辨識在封包資料中的第一個字元 位置; (d)在該第一個辨識的字元位置檢查接收自該實體層 之封包資料, (e )將在該第一個辨識的字元位置中所包含之元素指 示的資訊儲存到一資料結構之中;以及 (f )在封包被傳送到較上層之前將該資料結構附加於 封包資料。 經濟部智慧財產局員工消費合作社印製 2 .如申請專利範圍第1項之用以處理接收自一實體層 之封包資料的方法,其中檢查封包資料更包括: (g )根據該第一個辨識的字元位置之檢查結果和根據 指令集來辨識在封包資料中的第二個字元位置。 3 _如申請專利範圍第2項之用以處理接收自一實體層 之封包資料的方法,其更包括: (h )檢查在封包資料中之辨識的.第二個字元位置; (i)將在辨識的第二個字元位置中所包含之第二元素指 本紙张尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 495671 A8 B8 C8 D8 ^ ^ F 9/ ^---sc / 提之 pE^hfes..«lr^叫容泛¾准予修正" 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 示的資訊儲存到該資料結構之中;以及 (j)在封包資料傳送到較上層之前將包含第一儲存元 素和第二儲存元素的資料結構附加於該封包資料。 4 ·如申請專利範圍第3項之用以處理接收自一實體層 之封包資料的方法,其更包括: 爲另外的字兀位置重複(g )到(j )。 5 ·如申請專利範圍第1至4項中的任何一項之用以處 理接收自一實體層之封包資料的方法,其中用以定製編程從 實體層所接收之封包資料的處理之指令集包括辨識資料結構 的類型與複數個在該封包資料之內感興趣的字元位址之資訊 〇 6 .如申請專利範圍第5項之用以處理接收自一實體層 之封包資料的方法,其中該資料結構的類型係選自包括一指 標資料結構,一封包資料部分資料結構,一散列資料部分資 料結構’一旗標資料結構,以及一欄資料結構的群組中。 7 ·如申請專利範圍第6項之用以處理接收自一實體層 之封包資料的方法,其中該儲存的元素採取在旗標資料結構 中所儲存之旗標的形式。 8 ·如申請專利範圍第6項之用以處理接收自一實體層 之封包資料的方法,其中該儲存的元素採取在指標資料結構 中所儲存之指標的形式。 9 .如申請專利範圍第6項之用以處理接收自一實體層 之封包資料的方法,其中該儲存的元素採取在散列資料部分 貪料結構中所儲存之壓縮資料的形式。 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) 2- 495671 修正本^-]^.4:?'\/ 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 _ D8 六、申請專利範圍 1 0 _如申請專利範圍第1項之用以處理接收自〜實@ 層之封包資料的方法,其中該封包資料處理係藉由一與 輯鏈結控制層聯絡通信之媒體存取控制器層來執行。 1 1 ·如申請專利範圍第1項之用以處理接收自〜實胃 層之封包資料的方法,其中該封包資料連同所附加的資料g 構一起被直接或間接地傳送到一應用層。 1 2 ·如申請專利範圍第1項之用以處理接收自〜實_ 層之封包資料的方法,其中該封包資料連同所附加的資料_ 構一起被傳送到選自包括一邏輯鏈路層、一網路層、〜蓮_ 層、一交談層、一表識層以及一應用層之群組中的層。 1 3 . —種用以處理接收自一較下層之封包資料的方法 ,該處理由一媒體存取層串列地執行而同時傳送封包到〜_ 上層,其包括: (a )接收來自該較下層的封包; (b )在第一個字元位置檢查在所接收之封包內的封包 資料; (c )將在該第一個字元位置中所包含之元素指示的資 料儲存到一資料結構之中;以及 (d )在封包被傳送到較上層之前將該資料結構附加於 所接收的封包; (e)藉此該媒體存取層串列地預先處理所接收之封包 而同時將封包傳送到一較上層。 1 4 ·如申請專利範圍第1 3項之用以處理接收自一較 下層之封包資料的方法,其中該檢查封包資料更包括: 本紙浪尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 一 " -3 - (請先閲讀背面之注意事項再填寫本頁)495671 A8 B8 C8 D8 々 、 Patent Application No. 87 101 838 Patent Application Chinese Application Patent Scope Amendment Dec. 1990 Republic of China Amendment ^ • '" r 1 · A packet processing data received from a physical layer Method, this process is executed in series while sending packets to an upper layer, which includes: V ,, // rs: i: · (Please read the precautions on the back before filling this page) (a) Loading An instruction set for custom programming processing of packet data received from the physical layer; (b) determining the type of packet data received from the physical layer; (c) identifying the packet data in the packet data according to the instruction set ' The first character position; (d) checking the packet data received from the physical layer at the first recognized character position, (e) indicating the element contained in the first recognized character position The information stored in a data structure; and (f) append the data structure to the packet data before the packet is transmitted to the upper layer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. For the method of processing the packet data received from a physical layer as described in item 1 of the scope of patent application, the inspection of the packet data further includes: (g) According to the first identification The result of checking the character position of and identifying the second character position in the packet data according to the instruction set. 3 _ If the method for processing the packet data received from a physical layer in item 2 of the scope of patent application, it further includes: (h) Checking the identification in the packet data. The second character position; (i) The second element to be included in the identified second character position refers to the Chinese paper standard (CNS) A4 specification (210X297 mm) applicable to this paper size 495671 A8 B8 C8 D8 ^ ^ F 9 / ^ --- sc / Mention pE ^ hfes .. «lr ^ called Rong Fan ¾ grant amendments " Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Information shown in the scope of patent applications is stored in this data structure; and (j) in A data structure including a first storage element and a second storage element is attached to the packet data before the packet data is transmitted to an upper layer. 4. The method for processing packet data received from a physical layer as described in item 3 of the scope of patent application, which further comprises: repeating (g) to (j) for other word positions. 5 · A method for processing packet data received from a physical layer as in any of claims 1 to 4 of the scope of patent application, wherein the instruction set for customizing the processing of packet data received from the physical layer Includes information identifying the type of data structure and the number of character addresses that are of interest within the packet data. 6 For example, the method for processing packet data received from a physical layer, such as in item 5 of the patent application, where The type of the data structure is selected from the group consisting of an index data structure, a packet data portion data structure, a hash data portion data structure, a flag data structure, and a column data structure. 7. The method for processing packet data received from a physical layer as described in item 6 of the patent application scope, wherein the stored element takes the form of a flag stored in a flag data structure. 8. The method for processing packet data received from a physical layer as described in item 6 of the scope of patent application, wherein the stored element takes the form of an index stored in an index data structure. 9. The method for processing packet data received from a physical layer as described in item 6 of the scope of patent application, wherein the stored element takes the form of compressed data stored in a hash structure of the data portion. (Please read the precautions on the back before filling out this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 2- 495671 Revised version ^-] ^. 4:? '\ / Ministry of Economy Printed by the Intellectual Property Bureau's Consumer Cooperatives A8 B8 C8 _ D8 VI. Application for patent scope 1 0 _ If the scope of the patent application item 1 is used to process the package data received from the ~ @@ layer, the package data processing Performed by a media access controller layer in communication with the serial link control layer. 1 1 · The method for processing packet data received from the real stomach layer according to item 1 of the scope of the patent application, wherein the packet data is transmitted directly or indirectly to an application layer together with the attached data structure. 1 2 · If the method for processing the packet data received from the real-layer layer in item 1 of the scope of the patent application, the packet data, together with the attached data structure, is transmitted to a group selected from a layer including a logical link layer, A network layer, a lotus layer, a conversation layer, a surface recognition layer, and an application layer. 1 3. — A method for processing packet data received from a lower layer, the processing is performed in series by a media access layer while transmitting packets to the upper layer, which includes: (a) receiving from the lower layer The lower packet; (b) check the packet data in the received packet at the first character position; (c) store the data indicated by the element contained in the first character position to a data structure Among them; and (d) append the data structure to the received packet before the packet is transmitted to the upper layer; (e) thereby the media access layer pre-processes the received packet in series while transmitting the packet Go to the upper level. 1 4 · If the method for processing packet data received from a lower layer is described in item 13 of the scope of patent application, the inspection packet data further includes: This paper wave standard is applicable to China National Standard (CNS) A4 specification (210X297 mm) ) 一 " -3-(Please read the notes on the back before filling this page) 叫提之 經濟部智慧財產局員工消費合作社印製 495671 A8 B8 __g8s__ 六、申請專利範圍 (f )根據該第一個辨識的字元位置之檢查結果與微碼 指令來檢查在封包資料中的第二個字元位置。 1 5 ·如申請專利範圍第1 4項之用以處理接收自一較 下層之封包資料的方法,其更包括: (g )檢查在封包資料中之辨識的第二個字元的位置; (h )將在該辨識之第二個字元位置中所包含之第二元 素指示的資料儲存到該資料結構之中;以及 (i)在封包資料被傳送到較上層之前將包含該第一個 儲存的元素和該第二個儲存的元素之資料結構附加於該資料 封包。 1 6 ·如申請專利範圍第1 4項之用以處理接收自一較 下層之封包資料的方法,其更包括: 爲另外的字元位置重複(f )到(i )。 1 7 ·如申請專利範圍第1 3項到第1 6項的任何一項 之用以處理接收自一較下層之封包資料的方法,其中該微碼 指令預先決定該資料結構係選自包含一指標資料結構、一封 包部分資料結構、一散列封部部分資料結構、一旗標資料部 分以及一欄資料結構之群組中的一個資料結構。 1 8 ·如申請專利範圍第1 7項之用以處理接收自一較 下層之封包貪料的方法’其中該元素係一個即將被儲存於旗 標資料結構之中的旗標位元。 1 9 ·如申請專利範圍第1 7項之用以處理接收自一較 下層之封包貪料的方法,其中該元素係一個即將被儲存於封 包部分資料結構之中的資料部分。 (請先閱讀背面之注意事項再填寫本貢)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 495671 A8 B8 __g8s__ VI. The scope of patent application (f) is based on the inspection result of the first identified character position and microcode instruction to check the Two character positions. 15 · If the method for processing packet data received from a lower layer as described in item 14 of the scope of patent application, it further includes: (g) checking the position of the second character identified in the packet data; (g) h) storing the data indicated by the second element contained in the identified second character position into the data structure; and (i) the packet data will be included before it is transmitted to the upper layer The data structure of the stored element and the second stored element is appended to the data packet. 16 · The method for processing packet data received from a lower layer as described in item 14 of the patent application scope, further comprising: repeating (f) to (i) for another character position. 1 7 · The method for processing packet data received from a lower layer as in any one of the items 13 to 16 of the scope of patent application, wherein the microcode instruction determines in advance that the data structure is selected from the group consisting of A data structure in a group of an indicator data structure, a packet data structure, a hash seal data structure, a flag data structure, and a column data structure. 1 8 · A method for processing packets received from a lower layer as described in item 17 of the scope of patent application ', wherein the element is a flag bit to be stored in the flag data structure. 19 · The method for processing packets received from a lower layer as described in item 17 of the scope of patent application, wherein the element is a data portion to be stored in the data structure of the packet portion. (Please read the notes on the back before filling in the bonbon) "+”:>0/1 子修IL·. ,>、 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8六、申請專利範圍 2 0 ·如申請專利範圍第1 7項之用以處理接收自一較 下層之d包貝料的方法,其中該元素係一個即將被儲存於欄 貪料結構中之多位元組合。 2 1 · 申請專利範圍第1 7項之用以處理接收自一較 下層之封包資料的方法,其中該元素係一個指向一即將被儲 存於指標貪料結構中之表頭的指標。 2 2 ·如申請專利範圍第1 7項之用以處理接收自一較 Τ層之封*包資料的方法,其中該元素係即將被儲存於散列封 包部分資料結構中之被壓縮的資料。 2 3 ·如申請專利範圍第1 3項之用以處理接收自一較 下層之封包資料的方法,其中該資料結構在其被附加於被傳 送到較上層之所接收的封包之前被建立於一暫存器檔案中。 2 4 •如申請專利範圍第1 3項之用以處理接收自一較 下層之封包貪料的方法,其中該封包資料處理藉由一與一邏 輯鏈結控制層通信聯絡的媒體存取控制器層來執行。 2 5 ·如申請專利範圍第1 3項之用以處理接收自一較 下層之封包資料的方法,其中該封包資料連同所附加的資料 結構一起被直接或間接地傳送到一應用層。 2 6 .如申請專利範圍第1 3項之用以處理接收自一較 下層之封包資料的方法,其中該封包資料連同所附加的資料 結構一起被傳送到選自包括一邏輯鏈路層、一網路層、一運 輸層、一交談層、一表識層以及一應用層之群組中的一層。 2 7 · —種用以串列地剖析所接收之封包資料及傳送封 包資料至一較上層的封包資料處理機’其包括: 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) Ρ. 6 5 9 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 一記憶體,其被組構來接收定義即將被建立自所接收之 封包資料之資料結構的類型之可執行微碼; 一管線暫存器級,其具有複數個用以依序接收及暫時儲 存所接收之封包資料的字元之暫存器,在該管線暫存器級中 之複數個暫存器的每一個被連接到能夠讀取在該管線暫存器 級中所暫時儲存之部分字元的管線多工器; 一分析電腦,其被組構來檢查輸出自管線多工器之所接 收的封包資料,並且將由該分析電腦所產生之所接收的封包 資料之元素儲存到一暫存'器檔案之中;以及 一執行邏輯單元,其被組構來接收來自該記憶體之可執 行微碼,該執行邏輯單元被設計成藉由該分析電腦來控制所 接收之封包的檢查。 2 8 .如申請專利範圍第2 7項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中該可執行微碼包含辨識在所接收之封包中感興趣之字 元位置的指令。 2 9 ·如申請專利範圍第2 7項或第2 8項之用以串列 地剖析所接收之封包資料及傳送封包資料至一較上層的封包 資料處理機,其中該管線暫存器級被連接到一傳送所接收之 封包資料至一輸出多工器的先進先出記憶體,該傳送被組構 而發生於分析電腦檢查感興趣之辨識的字元位置的同時。 3 0 .如申請專利範圍第2 7項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中包含由分析電腦所產生之所接收的封包資料之元素的 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁)" + ": > 0/1 Zixiu IL., > Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 6. Application for a patent scope 2 0 A method for processing d bag materials received from a lower layer, wherein the element is a multi-bit combination to be stored in the column structure. 2 1 · The 17th scope of patent application for processing Method for receiving packet data from a lower layer, wherein the element is an indicator pointing to a header that is to be stored in the indicator data structure. 2 2 · For processing the received from item 17 in the scope of patent application A method of comparing the packet data of the T layer, in which the element is the compressed data to be stored in the data structure of the hash packet part. 2 3 · As for the processing of the received from item 13 in the scope of patent application A method for lower-level packet data, in which the data structure is created in a register file before it is attached to the received packet that is transmitted to the upper level. 2 4 • If the scope of patent application is item 13 Used to process received from a comparison A method for packet greed, wherein the packet data processing is performed by a media access controller layer in communication with a logical link control layer. 2 5 · For processing reception as described in item 13 of the scope of patent application A method for packet data from a lower layer, in which the packet data is directly or indirectly transmitted to an application layer together with the attached data structure. 2 6. As described in claim 13 of the scope of patent application for processing received from a A lower-level method of packet data, wherein the packet data is transmitted along with the attached data structure to a packet selected from a logical link layer, a network layer, a transport layer, a conversation layer, a face recognition layer, and One of the groups in the application layer. 2 7 · —A kind of serial analysis of the received packet data and transmission of the packet data to an upper level packet data processor 'It includes: This paper standard applies Chinese national standards ( CNS) Α4 size (210X297 mm) (Please read the notes on the back before filling out this page) P. 6 5 9 Printed by A8, B8, C8, D8, Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs Scope of patent application: a memory that is structured to receive executable microcode that defines the type of data structure to be created from the received packet data; a pipeline register stage that has a plurality of A register that receives and temporarily stores the characters of the received packet data. Each of the plurality of registers in the pipeline register stage is connected to be able to read the temporary data stored in the pipeline register stage. Stored partial character pipeline multiplexer; an analysis computer configured to check the received packet data output from the pipeline multiplexer, and store elements of the received packet data generated by the analysis computer To a temporary storage device file; and an execution logic unit configured to receive executable microcode from the memory, the execution logic unit is designed to control the received packet by the analysis computer Check. 2 8. For serially analyzing the received packet data and transmitting the packet data to an upper-level packet data processor as described in item 27 of the scope of patent application, the executable microcode includes identifying the received packet The position of the character of interest in the instruction. 2 9 · If the scope of the patent application is No. 27 or No. 28 for serially analyzing the received packet data and transmitting the packet data to an upper level packet data processor, the pipeline register level is Connected to a first-in-first-out memory that transmits the received packet data to an output multiplexer, the transmission is structured while the analysis computer checks the position of the recognized character of interest. 30. According to the scope of patent application No. 27, it is used to analyze the received packet data in series and send the packet data to an upper level packet data processor, which contains the received packet data generated by the analysis computer. The paper size of the element is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) -6- 495671 A8 B8 C8 D8___ 六、申請專利範圍 暫存器檔案被傳送到輸出多工器。 (請先閲讀背面之注意事項再填寫本頁) 3 1 ·如申請專利範圍第2 7項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 、,其中該暫存器檔案包含產生自由可執行微碼所設定之資訊 的該類型之資料結構。 3 2 ·如申請專利範圍第2 7項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中產生自由可執行微碼所設定之資訊的該類型之資料結 構被傳送到輸出多工器而'被附加於從先進先出記憶體所接收 之封包資料。 3 3 .如申請專利範圍第2 7項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中該類型之資料結構包含由分析電腦所產生之所接收的 封包資料之元素。 3 4 ·如申請專利範圍第2 7項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中該類型之資料結構係選自包含一指標資料結構、一封 包部分資料結構、一散列封包部分資料結構、一旗標資料結 構以及一欄資料結構的群組中。 3 5 ·如申請專利範圍第3 4項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中該元素係一個即將被儲存在旗標資料結構中的旗標位 元。 3 6 ·如申請專利範圍第3 4項之用以串列地剖析所接收 本紙iMJt適用中關家鮮(CNS )八4胁(210X297公羡) -- 495671 A8 B8 C8 D8 煩讀委员??示^^ It'正本有無變更贺^ 六、申請專利範圍 之封包資料及傳送封包資料至一較上層的封包資料處理機, 其中該元素係一個即將被儲存在封包部分資料結構中的封包 部分。 3 7 ·如申請專利範圍第3 4項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中該元素係一個即將被儲存在欄資料結構中的多位元組 合。 3 8 .如申請專利範圍第3 4項之用以串列地剖析所接 收之封包資料及傳送封包'資料至一較上層的封包資料處理機 ,其中該元素係一個指向即將被儲存在指標資料結構中之表 頭的指標。 3 9 ·如申請專利範圍第3 4項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中該元素係一個即將被儲存在散列封包部分資料結構中 的壓縮資料。 4 0 .如申請專利範圍第2 7項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中該分析電腦包括一 C R C模組用以執行一 C R C核對並且自所接收之封包資料中剝離一 C R C欄以回 應接收自執行邏輯單元的控制信號。 4 1 ·如申請專利範圍第2 7項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中分析電腦包括一散列模組用以壓.縮至少一部分所接收 之封包資料以回應接收自執行邏輯單元的控制信號。 本紙浪尺度適用中國國家梂準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -8- ^l:;Jt£5gr-^βΙΓέχΓ/ί揭之 經濟部智慧財產局員工消費合作社印製 ;^.ν 厂..inv^-^trf:贫内/ί'ί·^准 f 修 I £' 495671 A8 B8 C8 D8 六、申請專利範圍 4 2 ·如申請專利範圍第2 7項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中該分析電臘包括一可編程和核對產生器用以執行多項 式除法運算以回應接收自執行邏輯·單元的控制信號。 4 3 ·如申請.專利範圍第2 7項之用以串列地剖析所接 收之封包資料及傳送封包資料至一較上層的封包資料處理機 ,其中該分析電腦包括一內容定址的記憶體單元用以執行數 値比較以回應接收自執行邏輯單元的控制信號。 4 4 . 一種在一封包資料處理機中用以串列地處理封包 資料及傳送該封包資料至一被組構來傳送該封包資料於一網 路鏈路之上的傳送媒體取存控制器的方法,包括: 辨識一即將被傳送於該網路鏈路之上的封包; 產生一標籤表頭; 產生一循環多餘檢驗表頭;以及 在封包被傳送到該傳送媒體存取控制器之前將循環多餘 檢驗表頭和標籤表頭附加於被辨識即將被傳送於該網路鏈路 之上的封包。 4 5 ·如申請專利範圍第4 4項之方法,其中該標籤表 頭係一VLAN表頭。 4 6 .如申請專利範圍第4 4項或第4 5項之方法,其 中該循環多餘檢驗表頭係爲包含該標籤表頭之封包資料而產 生的。 4 7 ·如申請專利範圍第4 4項之方法,其中串歹fj j;也處 理封包資料及傳送該封包資料係對3 2位元字元來執行。 I紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 〜-- -9 - (請先閱讀背面之注意事項再填寫本頁) 、v一口 f 495671 Α9 Β9 C9 D9 申請專利範圍 修爆 正讀 裟示質V 容/h ί6 上匕押· 經濟部智慧財產局員工消費合作社印製 4 8 ·如申請專利範圍第4 4項之方法,其更包括: 代替媒體存取控制終點及起源欄,該替換被選擇性地執 行以致能I P傳送。 4 9 · 一種串列地重建封包資料與傳送該封包資料到一 實體媒體的方法,其包括: 將一以太網路封包分裂成複數個子封包; 將該複數個以太網路封包的子封包重新組裝成複數個 A T Μ單體;以及 在被傳送至該實體媒'體之前將一 A Τ Μ表頭附加於該複 數個ATM單體的每一個。 5 0 .如申請專利範圍第4 9項之串列地重建封包資料 與傳送該封包資料到一實體媒體的方法,其中該分裂、重新 組裝以及附加係對3 2位元字元串列地執行。 5 1 .如申請專利範圍第4 9項或第5 0項之串列地重 建封包資料與傳送該封包資料到一實體媒體的方法,其中該 分裂係I P分裂。 (請先閲讀背面之注意事項再行繪製) 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) -10--6- 495671 A8 B8 C8 D8___ 6. Scope of patent application The temporary register file is transferred to the output multiplexer. (Please read the precautions on the reverse side before filling out this page) 3 1 · If you are analyzing the received packet data in series and send the packet data to an upper-level packet data processor, such as item 27 of the patent application scope, , Where the register file contains a data structure of the type that generates the information set by the freely executable microcode. 3 2 · If the scope of patent application No. 27 is used to analyze the received packet data in series and send the packet data to an upper level packet data processor, which generates the information set by the freely executable microcode The type of data structure is passed to the output multiplexer and is' attached to the packet data received from the FIFO memory. 3 3. If the scope of patent application No. 27 is used to analyze the received packet data in series and send the packet data to an upper level packet data processor, wherein the type of data structure includes the data generated by the analysis computer Elements of received packet data. 3 4 · If the scope of patent application No. 27 is used to analyze the received packet data in series and send the packet data to an upper-level packet data processor, where the type of data structure is selected from the group consisting of index data Structure, a packet data structure, a hash packet data structure, a flag data structure, and a column data structure. 3 5 · As described in item 34 of the scope of the patent application, it is used to analyze the received packet data in series and send the packet data to an upper level packet data processor, where this element is a data structure to be stored in the flag data Flag bit in. 3 6 · If the scope of the patent application is No. 34, it is used to analyze the received serially. This paper iMJt is suitable for Zhongguan Jiaxian (CNS) Ya 4 threats (210X297 public envy)-495671 A8 B8 C8 D8 ? ^^ It's the original version has been changed. 6. The packet data of the scope of patent application and transmission of the packet data to an upper level packet data processor, where this element is a packet part that will be stored in the packet part data structure. 3 7 · If you use the 34th item in the scope of patent application to analyze the received packet data in series and send the packet data to an upper level packet data processor, this element is an element that will be stored in the column data structure. Multi-bit combination. 38. As described in item 34 of the scope of the patent application, it is used to analyze the received packet data in series and send the packet 'data to an upper level packet data processor, where the element is a pointer to the data to be stored in the index data. Indicator of the header in the structure. 3 9 · If you use the 34th scope of the patent application to analyze the received packet data in series and send the packet data to an upper level packet data processor, this element is an element that will be stored in the hash packet part. Compressed data in a data structure. 40. If item 27 of the scope of patent application is used to analyze the received packet data in series and transmit the packet data to an upper level packet data processor, the analysis computer includes a CRC module for executing a The CRC is checked and a CRC field is stripped from the received packet data in response to the control signal received from the execution logic unit. 4 1 · If the scope of patent application No. 27 is used to analyze the received packet data in series and send the packet data to an upper level packet data processor, the analysis computer includes a hash module for compression. At least a portion of the received packet data is shrunk in response to a control signal received from the execution logic unit. This paper scale is applicable to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs -8- ^ l:; Jt £ 5gr- ^ βΙΓέχΓ / Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs; ^ .ν Factory..inv ^-^ trf: Poor / '' ί · ^ 准 f 修 I £ '495671 A8 B8 C8 D8 6. Scope of patent application 4 2 · If the scope of patent application No. 27 is used to analyze the received packet data in series and send the packet data to an upper level packet data processor, the analysis electric wax includes a The programming and check generator is used to perform polynomial division operation in response to a control signal received from the execution logic unit. 4 3 · If applied. Item 27 of the patent scope is used to analyze the received packet data in series and send the packet data to an upper level packet data processor, wherein the analysis computer includes a memory unit for content addressing. Used to perform data comparison in response to control signals received from the execution logic unit. 4 4. A transmission media retrieval controller for processing packet data in a packet data processor in series and transmitting the packet data to a transmission medium configured to transmit the packet data over a network link The method includes: identifying a packet to be transmitted over the network link; generating a label header; generating a cyclic redundant check header; and cycling the packet before the packet is transmitted to the transmission medium access controller Redundant check headers and label headers are appended to packets identified as being about to be transmitted over the network link. 4 5 · The method according to item 44 of the patent application scope, wherein the tag header is a VLAN header. 46. If the method of item 44 or item 45 of the scope of patent application is applied, wherein the circular redundant inspection header is generated by the packet information containing the label header. 4 7 · The method according to item 44 of the scope of patent application, where fj j is stringed; processing of packet data and transmission of the packet data are performed on 32-bit characters. I paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) ~--9-(Please read the precautions on the back before filling this page), v-bite f 495671 Α9 Β9 C9 D9 Positive reading 裟 量 质 容 / h ί6 On the dagger · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 8 · If the method of the scope of patent application No. 44 is applied, it also includes: instead of the media access control endpoint and origin Column, the replacement is selectively performed to enable IP transmission. 49. A method for serially reconstructing packet data and transmitting the packet data to a physical medium, comprising: splitting an Ethernet packet into a plurality of sub-packets; and reassembling the sub-packets of the plurality of Ethernet packets. A plurality of ATM cells; and an ATM header is attached to each of the plurality of ATM cells before being transmitted to the physical media. 50. A method for serially reconstructing packet data and transmitting the packet data to a physical medium as described in item 49 of the scope of the patent application, wherein the splitting, reassembly and addition are performed in series on 32-bit characters . 51. A method for sequentially reconstructing packet data and transmitting the packet data to a physical medium as described in item 49 or item 50 in the scope of patent application, wherein the division is IP division. (Please read the precautions on the back before drawing) The paper size applies to the Chinese National Standard (CNS) Α4 specification (210X297 mm) -10-
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