EP0951134A1 - Direkte Verarbeitungsschaltung um die Verarbeitung von analogen und numerischen Signalen zu vereinheitlichen in Steuerungs- und Überwachungsschaltungen, insbesondere für Wechselstrommotoren - Google Patents

Direkte Verarbeitungsschaltung um die Verarbeitung von analogen und numerischen Signalen zu vereinheitlichen in Steuerungs- und Überwachungsschaltungen, insbesondere für Wechselstrommotoren Download PDF

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Publication number
EP0951134A1
EP0951134A1 EP99201092A EP99201092A EP0951134A1 EP 0951134 A1 EP0951134 A1 EP 0951134A1 EP 99201092 A EP99201092 A EP 99201092A EP 99201092 A EP99201092 A EP 99201092A EP 0951134 A1 EP0951134 A1 EP 0951134A1
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EP
European Patent Office
Prior art keywords
signals
analog
digital
logic
integrating
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EP99201092A
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English (en)
French (fr)
Inventor
Antonino Fratta
Roberto Bramardo
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ABB Servomotors SpA
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ABB Servomotors SpA
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements

Definitions

  • the present invention relates to a direct processing circuit for unifying the processing of analog and digital signals in control and monitoring circuits, particularly in high-performance AC electric drives.
  • the invention relates to a direct processing circuit for unifying the processing of analog and digital signals which is particularly suitable for use in power converters dedicated to the control of brushless and reluctance motors.
  • any analog input signals must be first converted into a digital form.
  • This can entail problems due to discretization and to sampling (numeric and time resolution, truncations, etcetera) and high costs for providing A/D conversion means dedicated to the individual signals to be converted.
  • an input signal always present in practice is the signal coming from the position transducer of the mechanical movement in output. This signal is very often analog, for example when the transducer is a resolver.
  • the aim of the present invention is to provide a direct processing circuit of analog and digital signals, particularly for the use in high performance AC drives, which is capable of unifying the processing of all the control signals by using, in a time-sharing mode, a single digital/analog conversion hardware to provide algebric functions and digital/analog and analog/digital conversions in zero-follower mode.
  • another object of the present invention is to provide a direct processing circuit for unifying the processing of analog and digital signals for controlling drive circuits which processes in different manners the components of an analog input vector, selected with an appropriate order, in order to generate a single analog output as a function of preset numeric data.
  • Another object of the present invention is to provide a direct processing circuit for unifying the processing of analog and digital signals for controlling drive circuits which provides, in an optimized manner, the functions of trigonometric calculation, particularly position signal demodulation, that arrive from an angular position transducer, and of digital/analog conversion.
  • Another object of the present invention is to provide a direct processing circuit for unifying the processing of analog and digital signals for controlling drive circuits combined with circuits which use numeric microprocessors.
  • Another object of the present invention is to provide a direct processing circuit for unifying the processing of analog and digital signals for controlling drive circuits which is highly reliable, relatively easy to provide and at competitive costs.
  • the direct processing circuit is characterized in that it comprises means for integrating logic and digital functions which are connected to a digital processor and are suitable to send digital signals to means for multiplying digital/analog signals, said multiplying means receiving in input analog signals which are meant to he multiplexed with said digital signals in order to obtain analog output signals as a function of preset numeric data, said means for integrating logic and digital functions driving said multiplying means in a time-sharing mode.
  • Figure 1 is a conceptual block diagram of the direct processing circuit according to the present invention.
  • the means 7 also emit an input address 8 which is meant to drive the multiplexer 1 to select an analog input signal to be processed.
  • the outputs of the sample-and-hold means 5, which are meant to store the result of operations performed in the multiplying means 2, are of the analog type and are designated by O 1 -O n .
  • Some outputs are also fedback, as analog data, to the multiplexing means 1 and others are fedback to the logic and digital function integration means 7 after passing through second integrating means 10, which are connected to the digital and logic function integrating means 7.
  • the means 7 are bidirectionally connected to a digital processor 33 by means of a bus 11.
  • the numeric output data from the logic and digital function integration means 7, designated by the reference numeral 12, are converted into the digital inputs 3 by means of conversion tables 13 which are described hereinafter.
  • the conversion tables 13 are specifically created according to the type of operation required and performed on the basis of the numeric data 12.
  • the above-described circuit is suitable for performing numeric operations directly on analog-type signals (or on signals that are numeric but must be converted into analog signals or viceversa).
  • operations that the circuit is capable of performing D/A conversion, sums and subtractions of analog signals modified numerically, execution of functions (trigonometric, exponential, etcetera) on the signals (by using the tables 13 that implement the chosen functions) can be mentioned.
  • the various functions are therefore executed one at a time, with a preset timing, and sequentially one after the other.
  • the signals in input to the multiplexer I are of the vectorial type with just two components.
  • This layout illustrates means 15 which are suitable to invert the order of the two components of the analog input signals a 1 -a n , as required in order to use the special structures of the D/A multiplying means, designated by the reference numeral 2.
  • the inverting means 15 receive in input a signal 16 which controls the inversion of the order of the components.
  • Said signal 16 comes from the logic and digital junction integration means 7 (such as for example a PGA, Programmable Gate Array).
  • the D/A multiplying means 2 are represented. in this layout, by first multiplying means 21 and second multiplying means 22 which are arranged so as to multiply the two components of the analog vector signal fed to the multiplexing means 1.
  • a first channel, in output from the inverting means 15, is defined by a first gain K 4 through which the "upper" component of the signal a H of the upper channel in output from the inverting means 15 passes. Said signal is then fed along two different paths to an adder node 25, directly in output from the gain K 4 and passing through a second gain ⁇ and the multiplying means 21.
  • the node 25 sums the signals that follow these two paths of the first channel.
  • the second channel relates to the "lower" component of the vector signal, which is designated by a L and is sent to the second multiplying means 22 to be subsequently added in a node 27.
  • Said node 27 receives in input the component in output from the node 25, designated by O H , and the component in output from the multiplying means 22, designated by O L .
  • the signal produced by the sum is then fed to amplifying means 30 and then sent to the sample-and-hold means 5.
  • part of the analog outputs of the sample-and-hold means 5 is fed back to the multiplexer 1, while another one of the analog outputs. which constitutes the position tracking error, is sent to error integrating means 31.
  • Means 31 produce in output a velocity signal 32 which is particularly useful when using a position transducer of the resolver type, in which the position error signal is used to reconstruct and track the electrical angle of the resolver.
  • the tables 13 comprise the necessary entries for the sine and cosine functions, which can be accessed by various variables by means of the numeric data 12.
  • the multiplying means 21 and 22 provided for example by means of networks of the R-2R type, perform multiplication between an analog signal and a numeric datum, which can correspond to a conversion from digital to analog if the analog input is a constant.
  • the sine and cosine functions can be constructed appropriately as a sequence of segments described only in the angular interval between 0 and ⁇ /4. Due to the particular configuration of the circuit, it is in fact sufficient to consider the interval between 0 and ⁇ /4 to store the numeric values required to compose the trigonometric functions over the entire angular range. The fact that the sine is described and provided only for the angle between 0 and ⁇ /4, like the cosine, allows to improve the overall resolution of the system.
  • the constants K 4 and ⁇ are factors delimiting the variation range of the gain that can be applied to the upper channel and therefore to the component a H in output from the order inverting means 15.
  • the circuit according to the invention unifies, in a time-sharing mode, the functions of programmable calculation, particularly of the trigonometric type, of decoding transducer signals (which have an analog information content) and D/A conversion. This is obtained by means of the specialization of D/A circuits (the multiplying means 21 and 22). Said means 21 and 22 are able to process in a differentiated manner the two components of the analog input vector. Such components are selected in an appropriate order so as to generate the individual analog output as a function of numeric data provided by the digital and logic function integration means 7 by means of the entries contained in the tables 13.
  • Figure 3 is a block diagram illustrating electrical circuit elements and electronic devices significant for the efficient provision of the functions indicated in Figure 2.
  • This diagram illustrates the means meant to attribute a sign to the components of the analog input vector signal, as required in order to determine the sign of the functions of the numeric data and therefore the sign of the analog output.
  • Sign reversing means 40 and 41 are connected in pairs in output to the inverting means 15. The outputs of the sign reversing means are sent to selecting means 50 and 51, which select the signal with the required sign and send it to the multiplying channels.
  • the multiplying means 21 and 22 are constituted by two R-2R networks 34 which are integrated in a single electronic device, performed in order to limit the uncertainty between the two networks.
  • said uncertainty which is generally equal to approximately 1%, is equivalent to the introduction of a small but significant gain error when an angular segment is selected.
  • the higher channel has been selected by means of the gain K 4 .
  • the currents in output from the R-2R networks 34 are added together by using an amplifier 35; the feedback of said amplifier is closed by means of a resistor R2 which is contained in the network 34 and has the same value as the resistor R of the R-2R network.
  • the resistor R1 equal in value to the resistor R2
  • the signal in output from the gain K4 is added.
  • the circuit described here corresponds to a particular embodiment of the adder nodes 25 and 27 shown in Figure 2.
  • the above-described circuit is. as a whole, particularly suitable to perform the accurate demodulation of the signals of a resolver.
  • the analog vector signal with two components in output from the resolver is sent in input to the multiplexing means I as one of the input signals a 1 -a n .
  • the input signals, after passing through the inverting means 15, the sign reversing means 40, 41 and the selecting means 50, 51, are conveniently processed by means of functions contained in the tables 13.
  • the input numeric data of tables 13 arrive from the digital and logic function integration means 7 and in particular from counting means 42, for example a numeric counter, the output numeric datum 45 of which represents the reconstructed electrical angle of the resolver.
  • the analog signal in output from the block 30 represents, in the execution of this specific task, an error signal between the real angle and the reconstructed angle of the resolver which, after passing through the sample-and-hold means 5, produces the sampled tracking error signal 43.
  • Said signal 43 after passing through the analog integrating means 31, which provide a signal which is proportional to the velocity, is converted into a signal whose frequency contains the velocity information.
  • converting means 44 such as a voltage-controlled oscillator.
  • the numeric datum 45 is therefore derived by numeric integration of the signal in output from the converting means 44 and represents the reconstructed angle of the resolver.
  • the numeric data 45 are also stored in a register 46 which is contained in the means 7, which also contain other registers which are generally designated by the reference numeral 47.
  • the registers 47 contain other data derived from the numeric datum 45 and numeric data coming from the bus 11. The management of these registers is entrusted to the addressing logic means 48. In the execution of other operations, the tables 13 are addressed by numeric data contained in the register 46 or in the registers 47.
  • the resolver used to obtain the angular position of the mechanical angle is, in modern embodiments, of the brushless type. In any case, the resolver must be supplied (rotor voltage) by an AC voltage of appropriate frequency: a sinusoidal voltage, termed excitation voltage, is usually used.
  • the present invention allows to excite the resolver by using, instead of the sinusoidal voltage, a trapezoidal voltage, as derived efficiency from a square wave by natural switching, for example, of MOSFET transistors of a stage put downstream of integrating means 7.
  • the excitation signal of the resolver is obtained from a circuit shown in Figure 4.
  • the signals V 1 and V 2 are generated by the logic and digital function integrating means 7. They are used as the control signals of the MOSFETs 60 and 61.
  • the signal V 2 assumes a value which is appropriate to keep the MOSFET 61 on, while the signal V 1 assumes a value which is adapted to keep the MOSFET 60 off.
  • the voltage V ecc is negative and its value is a function of the supply voltage V 1 and of the transformation ratio of the transformer 63.
  • both MOSFETs 60 and 61 are kept off. In this interval, due to the capacitors 64 and 65 and to the transformer 63, the voltage V ecc switches, in a natural manner, from the negative value to a symmetrical positive value for which it is possible to bring the MOSFET 60 to the on state.
  • the excitation system uses nondissipative stages. This fact allows to integrate the excitation stage even on signal boards, using surface-mount components. This is possible even in the case of low-impedance resolvers, which are needed in the case of long connections between the resolver mounted on the motor and the electronic demodulation circuit, executed according to the invention, which is physically provided in the converter.
  • Square-wave excitation is particularly useful when it is necessary to sample the signal supplied by the resolver. Differently from sinusoidal excitation, in which sampling should occur on the maximum of the waveform, which is difficult to define, in the case of square-wave excitation sampling occurs on a plateau after an adapted settling time. Accordingly, a time variation of the instant at which sampling occurs (within certain limits, of course) has a scarcely significant effect on the value of the sample, accordingly increasing the repeatability of the measurement, other conditions being equal.
  • a further advantage which arises from the use of the circuit according to the invention, particularly according to the block diagram of Figure 3, is that the decoding of signals arriving from the resolver by means of a tracking loop system is facilitated and simplified.
  • the circuit constitutes the means for processing the transducer signals of a resolver.
  • circuit according to the invention fully achieves the intended aim, since it allows to perform a method for unifying the processing of digital and analog signals by performing operations in time-sharing mode on said signals.
  • Said method for unifying the processing of analog and digital signals, particularly in AC electric drives comprises the steps that are described hereinafter, referring to figure 6.
  • analog input signals 99 are sent to multiplexing means 1 in order to select one of said analog input signals.
  • analog output signals are obtained from said multiplexing means 1 as a function of addressing signals 93 and predefined numeric data 98.
  • digital signals 96 derived from numeric data, are received.
  • step 103 in a time-sharing mode, a multiplication between said analog signals 99 and said digital signals 96 is performed in order to obtain analog output signals 92.
  • said analog output signals 92 are submitted to sample and hold processing obtaining signals 91.
  • a part 93 of said analog output signals 91 is fed back, at step 105, to address said multiplexing means 1.
  • Another part 90 of said analog output signals is sent, at step 105, to said integrating means 10.
  • said analog output signals 90 are integrated and sent, at step 107, to said logic and digital function integrating means 7. Frequency conversion of said analog output signals 90 is then performed at step 112.
  • the resulting analog signals 89 are stored in a register at step 113.
  • numeric data from means 7 are converted into digital signals by means of conversion tables storing functions to apply to said numeric data.
  • Said digitale signal are send to be acquired (step 102) by said multiplying means.
  • Signals 97 and 95 are sent by said logic and digital function integrating means 7 for addressing said multiplying means (at step 103) and said sample-and-hold means (at step 104).
  • Signals 98 are sent by said logic and digital function integrating means 7 for addressing said multiplexing means (at step 101)

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Automation & Control Theory (AREA)
  • Evolutionary Computation (AREA)
  • Fuzzy Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Communication Control (AREA)
  • Control Of Electric Motors In General (AREA)
EP99201092A 1998-04-14 1999-04-13 Direkte Verarbeitungsschaltung um die Verarbeitung von analogen und numerischen Signalen zu vereinheitlichen in Steuerungs- und Überwachungsschaltungen, insbesondere für Wechselstrommotoren Withdrawn EP0951134A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT98MI000778A IT1299072B1 (it) 1998-04-14 1998-04-14 Struttura circuitale di elaborazione diretta per unificare il trattamento di segnali analogici e digitali in circuiti di comando e
ITMI980778 1998-04-14

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EP0951134A1 true EP0951134A1 (de) 1999-10-20

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EP99201092A Withdrawn EP0951134A1 (de) 1998-04-14 1999-04-13 Direkte Verarbeitungsschaltung um die Verarbeitung von analogen und numerischen Signalen zu vereinheitlichen in Steuerungs- und Überwachungsschaltungen, insbesondere für Wechselstrommotoren

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0150472A2 (de) * 1983-12-30 1985-08-07 Kollmorgen Technologies Corporation Regelsystem für einen Induktionsmotor zur Verbesserung des transienten Verhaltens bei winkelgesteuerter Erregung
US4816723A (en) * 1988-04-04 1989-03-28 Sony Corporation Variable speed motor control method and apparatus
US5122719A (en) * 1991-02-27 1992-06-16 Eastman Kodak Company Method and apparatus for reducing recurrent fluctuations in motor torque
US5184156A (en) * 1991-11-12 1993-02-02 Reliant Laser Corporation Glasses with color-switchable, multi-layered lenses
US5225754A (en) * 1988-12-06 1993-07-06 Boral Johns Perry Industries Pty. Ltd. Control system for a motor
US5260650A (en) * 1989-06-19 1993-11-09 Siemens Aktiengesellschaft Method and apparatus for detecting low rotational speeds using a resolver
US5491391A (en) * 1993-09-16 1996-02-13 International Business Machines Corporation Start up circuit for continuous sine-wave commutated brushless motors

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0150472A2 (de) * 1983-12-30 1985-08-07 Kollmorgen Technologies Corporation Regelsystem für einen Induktionsmotor zur Verbesserung des transienten Verhaltens bei winkelgesteuerter Erregung
US4816723A (en) * 1988-04-04 1989-03-28 Sony Corporation Variable speed motor control method and apparatus
US5225754A (en) * 1988-12-06 1993-07-06 Boral Johns Perry Industries Pty. Ltd. Control system for a motor
US5260650A (en) * 1989-06-19 1993-11-09 Siemens Aktiengesellschaft Method and apparatus for detecting low rotational speeds using a resolver
US5122719A (en) * 1991-02-27 1992-06-16 Eastman Kodak Company Method and apparatus for reducing recurrent fluctuations in motor torque
US5184156A (en) * 1991-11-12 1993-02-02 Reliant Laser Corporation Glasses with color-switchable, multi-layered lenses
US5491391A (en) * 1993-09-16 1996-02-13 International Business Machines Corporation Start up circuit for continuous sine-wave commutated brushless motors

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ITMI980778A1 (it) 1999-10-14
IT1299072B1 (it) 2000-02-07

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