EP0931353A1 - Ajustement du seuil dans un transistor dmos vertical - Google Patents

Ajustement du seuil dans un transistor dmos vertical

Info

Publication number
EP0931353A1
EP0931353A1 EP97909973A EP97909973A EP0931353A1 EP 0931353 A1 EP0931353 A1 EP 0931353A1 EP 97909973 A EP97909973 A EP 97909973A EP 97909973 A EP97909973 A EP 97909973A EP 0931353 A1 EP0931353 A1 EP 0931353A1
Authority
EP
European Patent Office
Prior art keywords
region
semiconductor body
conductivity type
regions
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97909973A
Other languages
German (de)
English (en)
Other versions
EP0931353A4 (fr
Inventor
Richard K. Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Inc filed Critical Siliconix Inc
Publication of EP0931353A1 publication Critical patent/EP0931353A1/fr
Publication of EP0931353A4 publication Critical patent/EP0931353A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

Definitions

  • This invention relates to vertical DMOS transistors, and more particularly, to the adjustment of the threshold voltage thereof.
  • Fig. 1 shows a vertical DMOS transistor as disclosed in U.S. Patent No. 5,248,627, issued September 28, 1993, invented by Richard K. Williams and assigned to Siliconix incorporated, and as also disclosed in U.S. Patent No.
  • the vertical DMOS transistor 20 includes a P- type epitaxial layer 22 on a P+ type silicon substrate 24. Spaced-apart N- base regions 26, 28 are formed in the epitaxial layer 22, and P+ source regions 30, 32 are formed in the respective base regions 26, 28.
  • a gate oxide 34 extends over the channel regions 36, 38 and the portion 40 of the epitaxial layer 22 between the base regions 26, 28.
  • a gate 42 is formed over the gate oxide 34, all in accordance with the disclosure of the above-cited patents.
  • the backside of the substrate 24 acts as the drain 44 of the device 20.
  • a P+ threshold adjust implant is undertaken into the channel regions to adjust the threshold voltage of the device, as shown by the dotted line 46.
  • ions also pass through the gate 42 and gate oxide 34 into the epitaxial layer portion 40 between the base regions 26, 28.
  • the device thus far described is highly effective in use as a low threshold, low on resistance MOSFET.
  • the gate-to- drain overlap capacitance is an important factor, i.e., high gate-to-drain capacitance is undesirable. This is so because each time the gate 42 is charged and discharged, power is lost, which decreases the efficiency of the power converter.
  • the doping concentration of the epitaxial layer 22 is raised so that in turn the capacitance between the drain 44 and the gate 42 is increased. This makes the device 20 less desirable in the power converter setting because the ideal device in this application would have very low gate to drain capacitance.
  • a thick oxide region is grown on an epitaxial layer in turn overlying a semiconductor substrate.
  • Base regions are provided on either side of the thick oxide region in the epitaxial layer, and source regions are provided respectively in the base regions.
  • a threshold adjust implant is undertaken into the channel regions, the thick oxide region blocking ions from reaching the epitaxial layer thereunder.
  • a mask portion is provided over a portion of the gate above the epitaxial layer portion between the base regions, so that upon implant of threshold adjust dopant, the mask portion blocks such dopant from reaching the area of the epitaxial layer portion thereunder between the base regions.
  • Fig. 1 is a cross-sectional view of a prior art vertical DMOS device
  • Figs. 2-8 are cross-sectional views showing the process steps in fabricating a first embodiment of the invention
  • Figs. 9-12 are cross-sectional views showing the process steps in fabricating a second embodiment of the invention.
  • Fig. 13 includes Fig. 13a which is a graph of functional characteristics of a representative device, and Fig. 13b which is a schematic of such a representative device; and
  • Fig. 14 is a graph of other functional characteristics of a representative device.
  • the substrate 50 of the device 52 is typically silicon heavily doped with suitable P type dopant such as boron at a resistivity of
  • a P type epitaxial silicon layer 54 is grown on the substrate 50 to a thickness generally from 3 to 60 microns and doped with a suitable P type dopant such as boron at a concentration generally between 5x10 to lxlO 14 atoms/cm 3 .
  • the substrate 50 and epitaxial layer 52 form a semiconductor body 56.
  • the surface 58 of the epitaxial layer is oxidized for a first masking process, forming an oxide 60 of a thickness generally from 50 to 2000A. Oxide 60 is typically thermally grown.
  • a nitride layer 62 of thickness 1 to 5KA is deposited over the oxide layer 60.
  • the nitride layer 62 and oxide layer 60 are then patterned to expose a surface of the epitaxial layer 54.
  • the exposed surface of the epitaxial layer 54 is then oxidized to grow a thick oxide region 64 (Fig. 3), for example, anywhere from 2000A thick to over 1 micron thick, typically in the temperature range of 900° to 1100° C.
  • this thick oxide region 64 can be formed by growing a thick oxide over the entire epitaxial layer 54, and subsequent to appropriate masking, etching the thick oxide layer back to form the thick oxide region 64.
  • the oxide may also be left in the edge termination of the device.
  • gate oxide portions 66, 67 (Fig. 4), of uniform high integrity, are grown, typically in a dry thermal oxidation to a thickness generally from 1 OOA to 1200A.
  • a polysilicon film 68 is deposited on the resulting structure, typically to a thickness of about 5000A but ranging from lOOOA to 7000A.
  • the polysilicon film 68 is heavily doped with a suitable N type dopant such as phosphorous to achieve a sheet resistance of about 35 ohms/square, for example.
  • a mask oxide 70 is formed over the polysilicon 68, typically by low- pressure chemical vapor deposition, followed by the deposition of a photoresist layer (not shown).
  • the photoresist is patterned and the mask oxide 70 is etched to create a mask for the subsequent self-aligned double diffusions.
  • the photoresist is stripped, and the polysilicon 68 is etched through use of the mask oxide 70 to form a gate structure 68 for subsequent double diffusion.
  • a thinner polysilicon layer e.g., 600A to 2000A, can be deposited and coated with a thin layer of a refractive metal such as tungsten or titanium.
  • the metal/polysilicon sandwich is then reacted by a high temperature cycle to form a tungsten-silicide or titanium-silicide layer. Any subsequent oxide must be deposited using low temperature chemical vapor deposition.
  • the mask oxide 70 is etched in any suitable manner to remove portions of the oxide 66, 67 not covered by the polysilicon 68.
  • an implant is undertaken using a suitable N type material such as phosphorous at a dose generally from lxlO 13 to 1x10 atoms/cm 2 and an energy generally from 60 to 120 KeV, and the implant is driven in using a suitable furnace for a time generally from 60 to 600 minutes at a temperature generally from 1000° to 1200°C.
  • the PN junctions of the base regions 72, 74 formed along the surface 58 of the epitaxial layer 54 extend into the epitaxial layer 54 to a depth of about 2.5 microns, for example, and extends laterally under the edges of the polysilicon gate 68 a distance of about 2 microns, for example.
  • a thin oxide 76, 78 also forms over the major part of the base regions 72, 74. Although not shown in the drawings, the thin oxide also extends over the polysilicon 68. In lower voltage devices, the body junction depth may be reduced to around 1.5 ⁇ m with a lateral diffusion extending 1.2 ⁇ m.
  • Figs. 7 and 8 represent two P type implant operations, a source region implant and a threshold adjust implant, respectively.
  • Source regions 80, 82 in base regions 72, 74 respectively show the formation of source regions 80, 82 in base regions 72, 74 respectively.
  • a suitable P type dopant such as boron is implanted through the mask provided by the polysilicon gate 68, at a dose generally 3x10 14 to 8x10 5 atoms/cm and an energy generally from 40 to 100 KeV.
  • the source dopant is driven in for a time generally from 20 to 60 minutes at a temperature generally from 950° to 1100°C. to form source regions 80, 82 in the respective base regions 72, 74 along the surface 58.
  • the source regions 80, 82 are self-aligned with the polysilicon gate 68 and form channel regions 84, 86 near the surface 58 of the epitaxial layer 54 under gate oxide 66, 67.
  • the PN junction of the source region 80 extends into the epitaxial layer 54 to a depth of about 1 micron, for example, and extends laterally under the edge of the polysilicon gate 68 a distance of about 0.8 microns, for example.
  • the PN junction of the source region 82 has similar dimensions.
  • Fig. 8 shows the undertaking of a high energy P+ threshold adjust implant through the same mask, the polysilicon gate 68, as is used for the source implant.
  • the threshold adjust implant As the threshold adjust implant is made with higher energy than the source implant, it penetrates more deeply into the epitaxial layer 54 than the source implant.
  • the region of P concentration resulting from the threshold adjust implant is generally shown by the dotted lines 88, 90.
  • the thick oxide region 64 (much thicker than the gate oxide portion) keeps the threshold adjust implant from penetrating into the epitaxial layer portion 92 thereunder defined by and between the base regions 72,
  • the threshold adjust dopant does not extend continuously from one base region to the other, but in fact the portion 92 of the epitaxial layer 54 is free of threshold adjust dopant.
  • the device is then completed in normal process fabrication, using the backside of the substrate 50 as a device drain 94.
  • a device drain 94 As described above, by blocking dopant of the threshold adjust implant from reaching the epitaxial layer portion 92 between the base regions 72, 74, gate-to-drain capacitance of the device is reduced as compared to the device of Fig. 1. In addition, the relatively larger thickness of the oxide region further reduces this capacitance.
  • the present structure and process thus lend themselves to efficient application in switchable power supplies where high speed switching is desirable.
  • a gate oxide 100 (Fig. 9) is grown on an epitaxial layer 102 in turn grown on a semiconductor substrate 104, the epitaxial layer 102 and substrate 104 making up a semiconductor body 106.
  • a polysilicon film 108 is deposited on the resulting structure, which film is heavily doped with a suitable N type dopant such as phosphorous.
  • a mask oxide 110 is formed over the polysilicon, followed by the deposition of a photoresist layer (not shown). The photoresist is patterned and the mask oxide 110 is etched to create a mask for the subsequent self-aligned double diffusions.
  • a mask portion 124 (Fig. 12) is configured over the polysilicon gate 108, so that this mask portion 124 blocks the threshold adjust implant from penetrating into the epitaxial layer portion 126 thereunder between the base regions 112, 114 (indicated by the dotted lines 128, 130).
  • the device is then completed in normal process fabrication, using the backside of the substrate 104 as a device drain 128.
  • Q g the charge which must be forced onto the gate to turn the device on.
  • the gate charge Q g is actually divided into the charge needed to charge the gate to source capacitance C gs and the gate-to-drain capacitance C cg (see Fig. 13).
  • C gd is more important because its influence is amplified by the gain of the transistor during switching (a type of effect similar to the well known Miller effect in bipolar transistors).
  • Gate charge is convenient since power loss becomes independent of the linearity of the parasitic capacitances. As the gate is charged at a rate of I g the gate voltage V G rises until the drain voltage V D begins to drop.
  • the V t adjust will result in a high value of C gd since the overlap capacitance is less voltage dependent when the concentration is increased.
  • a thick gate high threshold part can reduce the knee of the gate charge curve to InC but doubles the R DS (on).
  • the 300m ⁇ on-resistance and InC charge can be achieved in the same device.
  • the resulting Q g R DS product can be improved over present day solutions by a factor of 2X to 5X.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Une épaisse région d'oxyde (64) est disposée sur une couche épitaxiale (54) qui, elle, recouvre un substrat semi-conducteur (50). Des régions de base sont disposées de part et d'autre de l'épaisse région d'oxyde, et des régions de source sont situées respectivement dans ces régions de base. Après la formation de parties d'oxyde de grille et d'une grille qui est disposée au dessus des parties d'oxyde de grille et de la région épaisse d'oxyde, un implant d'ajustement du seuil est introduit dans les régions de type canal du dispositif, ladite région épaisse d'oxyde empêchant les ions d'atteindre la couche épitaxiale sous-jacente. Selon une autre réalisation, après la formation de l'oxyde de grille, de la grille, des sources et des drains, une partie faisant office de masque est placée sur une partie de la grille, au-dessus de partie de la couche épitaxiale située entre les régions de base, de sorte qu'au moment de l'implantation du dopant d'ajustement du seuil, la partie faisant office de masque empêche ledit dopant d'atteindre la zone de la partie de couche épitaxiale sous-jacente.
EP97909973A 1996-10-25 1997-10-16 Ajustement du seuil dans un transistor dmos vertical Withdrawn EP0931353A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US73590996A 1996-10-25 1996-10-25
US735909 1996-10-25
PCT/US1997/017929 WO1998019344A1 (fr) 1996-10-25 1997-10-16 Ajustement du seuil dans un transistor dmos vertical

Publications (2)

Publication Number Publication Date
EP0931353A1 true EP0931353A1 (fr) 1999-07-28
EP0931353A4 EP0931353A4 (fr) 1999-08-11

Family

ID=24957730

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97909973A Withdrawn EP0931353A1 (fr) 1996-10-25 1997-10-16 Ajustement du seuil dans un transistor dmos vertical

Country Status (2)

Country Link
EP (1) EP0931353A1 (fr)
WO (1) WO1998019344A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102148164B (zh) * 2011-03-10 2016-09-07 上海华虹宏力半导体制造有限公司 Vdmos器件的形成方法
CN104347693A (zh) * 2013-07-23 2015-02-11 北大方正集团有限公司 功率半导体器件及其制造方法
CN107516675B (zh) * 2016-06-16 2019-11-08 北大方正集团有限公司 半导体结构及其制备方法
CN108257872A (zh) * 2018-01-12 2018-07-06 北京品捷电子科技有限公司 一种SiC基DI-MOSFET的制备方法及SiC基DI-MOSFET
CN111129155A (zh) * 2019-12-25 2020-05-08 重庆伟特森电子科技有限公司 一种低栅漏电容碳化硅di-mosfet制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61158181A (ja) * 1984-12-28 1986-07-17 Tdk Corp Ｍｉｓ型半導体装置の製造方法
US5218220A (en) * 1991-11-12 1993-06-08 Harris Corporation Power fet having reduced threshold voltage
WO1993019482A1 (fr) * 1992-03-20 1993-09-30 Siliconix Incorporated Reglage d'une valeur seuil concernant des dispositifs a dmos verticaux

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2604777B2 (ja) * 1988-01-18 1997-04-30 松下電工株式会社 二重拡散型電界効果半導体装置の製法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61158181A (ja) * 1984-12-28 1986-07-17 Tdk Corp Ｍｉｓ型半導体装置の製造方法
US5218220A (en) * 1991-11-12 1993-06-08 Harris Corporation Power fet having reduced threshold voltage
WO1993019482A1 (fr) * 1992-03-20 1993-09-30 Siliconix Incorporated Reglage d'une valeur seuil concernant des dispositifs a dmos verticaux

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 010, no. 363 (E-461), 5 December 1986 -& JP 61 158181 A (TDK CORP), 17 July 1986, *
See also references of WO9819344A1 *

Also Published As

Publication number Publication date
WO1998019344A1 (fr) 1998-05-07
EP0931353A4 (fr) 1999-08-11

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