EP0930604A1 - Synchronisationsvorrichtung und Methode zur Synchronisation einer Anzeigevorrichtung und Anzeigevorrichtung, welche die Synchronisationsvorrichtung verwendet - Google Patents

Synchronisationsvorrichtung und Methode zur Synchronisation einer Anzeigevorrichtung und Anzeigevorrichtung, welche die Synchronisationsvorrichtung verwendet Download PDF

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Publication number
EP0930604A1
EP0930604A1 EP99400082A EP99400082A EP0930604A1 EP 0930604 A1 EP0930604 A1 EP 0930604A1 EP 99400082 A EP99400082 A EP 99400082A EP 99400082 A EP99400082 A EP 99400082A EP 0930604 A1 EP0930604 A1 EP 0930604A1
Authority
EP
European Patent Office
Prior art keywords
display
signal
line
synchronization
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99400082A
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English (en)
French (fr)
Inventor
Christian Noel
Vincent Hubert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Johnson Controls Automotive Electronics SAS
Original Assignee
Sagem SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sagem SA filed Critical Sagem SA
Publication of EP0930604A1 publication Critical patent/EP0930604A1/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0606—Manual adjustment

Definitions

  • the invention originates from the problem of displaying a map. geographic on the liquid crystal display, LCD, browser in a car.
  • An LCD screen has a matrix of controlled display elements each by an associated memory point.
  • the memory points are cyclically refreshed by a video image signal line frame comprising a succession of steps each representing the intensity at restore by one of the elements.
  • Screen management logic samples each step and stores successive samples in the various memory points.
  • the on-board navigator computer provides, in addition to the signal video image signal, a line synchronization signal, comprising a pulse relative to which the start of the video signal exhibits a delay of a fixed term.
  • the screen management logic initializes then sampling with a local clock of period equal to the duration a step, clock with the above delay, increased by half a period in order to sample the bearings in the central area of their period.
  • the above delay is not precisely defined, as the calculator can only adjust it by jumps, or not, equal to the period of a landing. Therefore, if the sampling clock drifts up to one half phase phase shift phase, it will sample the flanks bearings instead of their stable central area, and the computer cannot perform the precise registration necessary.
  • the streets in a map to be displayed, are represented by a line of a single row of pixels, given the limited size of the screen. Any line intersecting a line of the matrix is therefore represented by a only point which presents a strong contrast with those who frame it in the line, and which represent the background.
  • EP-0 791 913A teaches to trigger, by a synchronization signal line, an oscillator sampling pixel signals through a delay circuit adjustable by a control circuit according to a setpoint value in memory.
  • the user of the screen cannot correct the drifts or the time dispersion of the control computer or that of the cables respectively providing image and synchronization.
  • the present invention aims to eliminate the display defect described above, in a manner other than explained above, in order to avoid drawbacks indicated.
  • the invention relates, first of all, to a device for synchronization of a display of image line signals associated with a line synchronization signal, device in which means adjustable time offset are arranged to receive the signal synchronization and to restore it to the display with an offset time determined by means for adjusting the shift means, comprising an input for receiving a setpoint offset value.
  • the device of the invention thus constitutes a fine adjustment element of the display, interposed between it and the microprocessor, or equivalent, who commands it.
  • This device can in fact be mechanically autonomous or be incorporated, display side or microprocessor side, and processes a relatively low frequency signal, so with constraints of very limited achievement.
  • the offset setpoint can be applied by any user, for example by two impulse buttons, respectively increasing and decrease this value, possibly through the microprocessor.
  • the setpoint can be transmitted at any speed desired, i.e. the speed of its transmission is independent of the fineness of the temporal adjustment which it controls, which does not impose thus to the microprocessor no speed constraint. It is the operator which plays the role of a correctly servo feedback loop the display, if the latter does not include a fault detector synchronization.
  • an oscillator is provided, with servo-control on the restored synchronization signal, arranged to provide the display with a line signal sampling clock, clock corresponding to a pixel frequency of these and locked in phase with respect to said signal synchronization restored.
  • the invention also relates to a display comprising a device for synchronization of a display screen for associated image line signals to a line synchronization signal, the device comprising means adjustable time offset arranged to receive signal synchronization and restore it to screen control means, with a time difference determined by means of adjusting the shift means, comprising an input for receiving a value of setpoint offset.
  • the invention finally relates to a method for controlling a display with line scan arranged to receive a line image signal and to sample it cyclically, and display it by a pixel phase clock slaved to a received line synchronization signal, method characterized by the fact that there is interposed between the display and a control circuit supplying said signals, a phase shift circuit of the signal synchronization and you adjust the clock phase, relative to the signal line image, by action on the phase shift circuit.
  • the control assembly 1 of FIG. 1 controls a display 3 at through a line 4 image signal transmission cable L and a cable line synchronization signal consisting of two sections 5 and 6 between which a phase shift device 2 is interposed. All these circuits are installed in a car, to display maps geographical and in particular detailed city maps, the streets being represented by a line the width of a pixel.
  • the line scan display 3 receiving the line image signal L, samples it cyclically, to display it, by a pixel clock Ha at phase controlled by the received line S synchronization signal. To this end, between the display 3 and the control circuit 1 supplying the signals L and S, is interposed the circuit 2 phase shifter of the synchronization signal S and the phase of the clock Ha is adjusted, relative to the image signal L, by action on the phase shift circuit 2.
  • each line signal L comprises a plurality of steps elementary, here 320, corresponding to the number of elements per line of display 3, here of the liquid crystal display, LCD type.
  • the amplitude of each level, of duration T represents the intensity to be displayed on the display element of the same rank.
  • Synchronization signal S has negative pulses I (designated by "Ia” after crossing device 2), one per line period P and of adjustable duration D.
  • the display 3 By an oscillator circuit 31 controlled in phase at from the signal S (fig. 5), the display 3 generates the clock signal Ha of period T, used to sample the signal L to direct the various levels of steps towards memory points each commanding a particular pixel display element.
  • the start of the first level of signal L has a guard time delay R relative to the edge backward, active and here rising, from pulse I (or Ia).
  • the clock signal Ha must present active edges, here amounts, of sampling of the signal L, located approximately in the middle of each landing period T, i.e. delayed by a duration R + T / 2 on the trailing edge of the pulse Ia.
  • circuit 1 includes, for the emission of signals L and S, an oscillator 11 at frequency F, or pixel period T, followed a divider by 400, referenced 12, of period line P.
  • a circuit of formatting 13, such as monostable or decoder of several states of the divider 12, provides on the cable 5, at each period P, the signal S comprising the negative pulse I of duration D.
  • a microprocessor not shown, manages the sequencing of the functioning of the circuits shown.
  • the phase shifting device 2 of FIG. 4 makes it possible to adjust, in advance or in delay, time position, or phase, of the active front, back, of the pulse I with respect to the line L signal.
  • the device 2 comprises at the input an activation circuit 21, such as monostable, sensitive to the front edge of pulses I and unlocking then, by a pulse I widened behind, Ie, (fig. 5), the input of reset of a counter 22.
  • the unlocking time (Ie) is long enough, for example twenty periods T, to exceed clearly the duration of the pulse I received and thus allow adjustment, in a wide range (striped area), the position of the rear edge of the pulse Ia controlling the phase of the PLL circuit 31 of the display 3, at through a delay circuit 30 R.
  • the leading edge of the pulse I, inactive vis-à-vis the display 3, is thus transformed into an activation front of the display 3.
  • the rear edge of the pulse Ia restored is shifted forward with respect to its counterpart to the pulse I of origin.
  • the device 2 is therefore activated by a front, front, of the pulse I different from the front, rear, which synchronizes the display 3, which, in addition to the back shift, allows you to easily shift the front, back, following.
  • a delay of these edges cyclic, of a value adjustable around the period line P would allow still to obtain, in addition to a backward shift, a forward shift for the restored pulse Ia, modulo P, leaves to increase the number of stages of counter 22.
  • the outputs of counter 22 are connected to first inputs of a comparator 26 controlling an input of a door 27 of which a second input receives the widened pulses from circuit 21.
  • An input 23 of the device 2 receives, here by a circuit 16 of the assembly 1, offset adjustment setpoints R, chosen by a user using a keyboard 15. It could have been expected that the device 2 is integrated into assembly 1 or else into display 3.
  • automatic compensation is provided by drift temperature of delay circuit 30 of display 3 and of circuit 13, so that the setpoint is changed according to the value of ambient temperature supplied by a thermal probe 24.
  • a slight frequency drift of the PLL circuit 31 can likewise be masked by control of a compensating phase shift of the clock Ha, by adjusting the pulse Ie, so that the 320 samplings are each carried out on a stable part of the bearing concerned, for example the second half.
  • a memory 25, containing a law or table of correction or compensation in temperature and addressed by the two values, setpoint and temperature, provides a corrected time offset numerical value to second comparator inputs 26.
  • the 31 PLL frequency boost circuit by a factor 400, providing the clock Ha with the delay R of circuit 30, command the clock input of a CCD shift register 32 receiving the signal line L of cable 4 and thus copying the 320 bearings initially contained in the CCD circuit 14.
  • a counter not shown, limits each train of clock signals Ha at 320 pulses.
  • circuits 30 and 31 are in device 2 and that the display 3 receives the Ha clock.
  • the CCD 32 is emptied in parallel in a buffer register 33 whose parallel outputs respectively control the 320 elements of a specific line 34 of display 3.
  • a sequencer switches the line signals successive to as many registers as that referenced 33.
  • a multiplexer addressed by a counter advancing at rhythm F.
  • the analog values would then be directly transferred from a transmission memory, such as RAM or register with parallel outputs, and memorized according to the same principle in reception, through a demultiplexer.
  • the user enters a setpoint offset value, which he modifies until a correct functioning is obtained, i.e. a sampling by the Ha clock which occurs substantially at mid-term of each period T, operation visible by the fact that the display does not no blur.
  • the circuit 21 authorizes the advance of the counter 22, at the rate of the fast clock Fr and the expanded pulse Ie begins to be transmitted to cable 6 through the door 27, the comparator 26 leaving it open.
  • the counter 22 reaches a value equal to that provided by memory 25, the comparator 26 then locks door 27, as well as a locking input clock 22 counter, which freezes the state thereof. So the duration of the pulse Ia retransmitted to the display 3 is adjusted as desired by the counter 22 and comparator 26, which together form a circuit delay, programmable by memory 25 controlled by input 23.
  • the active front, rear, pulse Ia, servo-control of the PLL 31 circuit providing the sampling clock Ha is thus out of phase as desired by relative to the levels of signal line L, unchanged.
  • the frequency Fr being ten times higher than frequency F, the adjustment step is therefore T / 10, or 36 degrees.
  • a simple adjustment of 180 could have been expected degrees or less, i.e. a frequency Fr at least double the pixel frequency F of the elementary steps.
  • circuit 21 again locks the reset input of the counter 22, already stopped, on the rear edge of the widened pulse Ie, this lock resets counter 22 to zero, freeing its input from clock lock, waiting for the next line cycle which will unlock the reset input.
  • a programmable counter could have been provided by the value of memory 25, with a decoder, replacing the comparator 26, to detect the arrival of the counter 22 at a predetermined state, by example the maximum counting state "15" for 4 bits, and therefore for detect the arrival just before the fallout rest state. State "15” could then, with a permanent hold at the input of the meter, authorize the propagation of this output, with the blocking effect exposed for the output of comparator 26.
  • the device 2 could comprise, in place of the counter 22 and comparator 26, analog delay circuits, do not therefore requiring no clock.
  • a multiplexer functional equivalent comparator 26
  • the setting step may thus be of great finesse, while overcoming the problems of radiation related to the presence of a high frequency clock in the digital delay.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Synchronizing For Television (AREA)
  • Liquid Crystal Display Device Control (AREA)
EP99400082A 1998-01-14 1999-01-14 Synchronisationsvorrichtung und Methode zur Synchronisation einer Anzeigevorrichtung und Anzeigevorrichtung, welche die Synchronisationsvorrichtung verwendet Withdrawn EP0930604A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9800307 1998-01-14
FR9800307A FR2773631B1 (fr) 1998-01-14 1998-01-14 Dispositif de synchronisation d'afficheur, afficheur comportant un tel dispositif et procede correspondant de synchronisation d'afficheur

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EP0930604A1 true EP0930604A1 (de) 1999-07-21

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EP99400082A Withdrawn EP0930604A1 (de) 1998-01-14 1999-01-14 Synchronisationsvorrichtung und Methode zur Synchronisation einer Anzeigevorrichtung und Anzeigevorrichtung, welche die Synchronisationsvorrichtung verwendet

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FR (1) FR2773631B1 (de)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0244978A2 (de) * 1986-04-25 1987-11-11 Seiko Instruments Inc. Interface, zum Beispiel für eine Flüssigkristallanzeige
JPH0695638A (ja) * 1992-09-11 1994-04-08 Matsushita Electric Ind Co Ltd サンプリングスタートパルス発生回路
EP0791913A2 (de) * 1996-02-22 1997-08-27 Seiko Epson Corporation Verfahren und Vorrichtung zur Einstellung eines Punkttaktsignales

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0244978A2 (de) * 1986-04-25 1987-11-11 Seiko Instruments Inc. Interface, zum Beispiel für eine Flüssigkristallanzeige
JPH0695638A (ja) * 1992-09-11 1994-04-08 Matsushita Electric Ind Co Ltd サンプリングスタートパルス発生回路
EP0791913A2 (de) * 1996-02-22 1997-08-27 Seiko Epson Corporation Verfahren und Vorrichtung zur Einstellung eines Punkttaktsignales

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"AUTOMATIC PHASE ADJUSTMENT", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 37, no. 5, 1 May 1994 (1994-05-01), pages 203/204, XP000453131 *
PATENT ABSTRACTS OF JAPAN vol. 018, no. 362 (P - 1766) 7 July 1994 (1994-07-07) *

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FR2773631A1 (fr) 1999-07-16
FR2773631B1 (fr) 2001-11-02

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