Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/10—Program control for peripheral devices
  • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
  • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
  • G06F13/4004—Coupling between buses
  • G06F13/4027—Coupling between buses using bus bridges
  • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
  • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses

Definitions

• the present invention relates generally to the design and development of microprocessor and memory systems within computers. More particularly, the present invention relates to transmission of data between a CPU and devices external to the CPU. Still more particularly, the present invention relates to data transmission between a CPU and a multimedia device using receive and transmit FTFO buffers.
• multimedia computers may present video images and/or audio tracks from a medium such as a CD-ROM.
• FIG. 1 shows a typical prior art computer system depicting the elements relevant to the present discussion.
• a central processing unit (CPU) core 10 is coupled to an LI cache system 15 and a bus Input/Output (I O) device 16 over a CPU local bus 8.
• the LI cache system 15 typically includes a cache controller and a cache SRAM (not shown).
• the CPU core 10, LI cache system 15, and bus I/O 16 may be implemented as separate discrete components but preferably are integrated onto a single chip processor as indicated by dashed box 9.
• the bus I/O device 16 couples the CPU local bus 8 to a memory bus 11.
• a memory control unit or memory controller 12 also couples to the memory bus 11.
• a second level cache, referred to as an L2 cache 7, couples to the memory bus 11 and also couples to the memory control unit 12.
• the memory control unit 12 couples to a memory device 13.
• the memory device 13 typically is dynamic random access memory (DRAM).
• DRAM dynamic random access memory
• a bus bridge 17 couples the memory bus 11 to a peripheral bus 18.
• Peripheral devices 19 are coupled to the peripheral bus.
• a multimedia device 190 represents one type of peripheral device which is coupled to the peripheral bus 18. Examples of multimedia devices are CD-ROM drives, graphics cards, video recorders, sound cards, modems, and the like.
• a simple communication scheme allows data from the CPU core 10 to be placed on the CPU local bus 11 and tr.ansferred through the bus I/O device 16, memory bus 11, bus bridge 17, peripheral bus 18, and to a peripheral device/ multimedia device.
• Data communication from the peripheral devices 19 and 190 to the CPU core 10 follows the same path, albeit in the reverse order.
• the CPU core 10 typically engages in multiple activities such as access cycles to the memory device 13 through memory control unit 12, accesses to the LI cache SRAM 15, as well as receiving and transmitting data to a variety of peripheral devices 19/190.
• the CPU core 10 often performs digital signal processing (DSP) operations on video and audio data to and from the multimedia device 190.
• DSP digital signal processing
• Multimedia data often comprises real-time, isochronous data (i.e., video and audio data metered out in regular time periods).
• latency effects renders memory structures incapable of allowing real-time blocks of data to be stored, retrieved, and processed wid out detrimentally effecting me data's real-time nature. Further, latency in accessing DRAM often is unpredictable. For example, video data that is stored in die memory device 13 and periodically processed by the CPU core 10 with the latency inherent to the system may result in dropped frames or missed audio data, thereby resulting in jerky video and poor audio quality .
• Buffering the multimedia data directly in the LI cache system instead of main memory might be beneficial as cache memory accesses are faster and more efficient than accesses to system memory.
• direcdy buffering the multimedia data in the LI cache system 15 and bypassing main memory storage is impractical because cache memories cannot be used direcdy by peripheral devices to store data.
• the present invention incorporates a system and method for communication of data between a central processing unit (CPU) and one or more peripheral devices attached to a peripheral bus.
• the system comprises a CPU coupled to a system or memory bus.
• the system bus in turn couples to a peripheral bus through a bus bridge.
• One or more peripheral devices are coupled to the peripheral bus.
• the present invention comprises one or more memory buffers coupled to the CPU which stores peripheral and/or multimedia data tr.ansferred to or from the one or more peripheral devices.
• FIFO first-in-first-out
• the memory buffer includes separate transmit and receive buffers. Data from the CPU is first stored in the transmit FIFO buffer, and once the transmit FIFO buffer becomes sufficiendy full, the peripheral device requests control over the peripheral bus to retrieve data from the FIFO buffer. The peripheral bus writes data to the receive FIFO buffer via the peripheral bus and bus bridge for subsequent retrieval by the CPU.
• data stored in the respective transmit and receive buffers is transferred direcdy to/from the peripheral devices.
• There data stored in the tr.ansmit FIFO buffer is read by the periphery or multimedia devices without passing through the bus bridge .and periphery bus.
• Data written into the receive FIFO buffer also is communicated direcdy between the peripheral device and FIFO buffer without passing through d e peripheral bus and bus brid ⁇ e.
• the FIFO buffer produces interrupt signals which reflect the amount of the FIFO buffer currendy in use for storing data. These interrupt signals are used by the CPU and the peripheral device as an indication of when to retrieve data from the FIFO buffers.
• the CPU may mon i tor the level of data in the FIFO.
• the CPU may adjust the effective processing rate so as to ensure the FIFO maintains an optimal level of data.
• the CPU may adjust the clock rate of the F FO buffer to maintain an optimal data level.
• Figure 1 is a block diagram representation of a typical prior an computer system.
• Figure 2 is an exemplary block diagram of the parallel implementation of the preferred embodiment.
• Figure 3A is a block diagram of die receive FIFO contained in d e parallel implementation.
• Figure 3B is a block diagram of the transmit FIFO contained in the psLraliel implementation.
• Figure 4 is an exemplary block diagram of the serial data implementation of the preferred embodiment.
• Figure 5A is a block diagram of the receive FIFO contained in the serial implementation.
• Figure 5B is a block diagram of the transmit FIFO contained in die serial implementation.
• Figures 6A-6D are exemplary block diagrams including registers for correcting mismatched data rates.
• a central processing unit (CPU) core 100 is coupled to an LI cache system 150 and bus I/O device 160 over a CPU local bus 80. Also attached to die CPU local bus is a transmit first-in-first-out buffer (TX FIFO) 300 and receive FIFO buffer (RX FIFO) 200 according to the present invention.
• TX FIFO transmit first-in-first-out buffer
• RX FIFO receive FIFO buffer
• a parallel bus structure 175 couples the RX and TX FIFOs to die bus I/O 160.
• these components are integrated into a single processor chip, as indicated by the dashed box 20.
• the bus I/O 160 connects die CPU local bus 80 to a system bus or memory bus 110.
• a memory control unit 120 also couples to the system bus 110.
• the memory control unit 120 couples to a memory device 130 which preferably includes dynamic random access memory (DRAM).
• L2 cache 70 couples to the memory control unit 120 and to the system bus 110.
• a bus bridge 170 provides connectivity between the system bus 110 and a peripheral bus 180.
• External devices 19 and multimedia devices 190 couple to die peripheral bus 180.
• the peripheral bus 180 preferably comprises a PCI (Peripheral Component Interconnect) bus, but may comprise other bus types such those complying widi the ISA and EISA standards. Thus, the peripheral bus 180 is not limited to any panicular bus architecture.
• Multimedia device 190 represents such media devices as graphics/video cars or systems, audio cards or systems, MPEG decoders/encoders, CD ROM systems, video cassette recorders, video cameras, and the like.
• Data to and from the peripheral devices 19 and multimedia device 190 may flow along d e path including the CPU core 100, CPU local bus 80, bus I/O 160, system bus 110, bus bridge 170, peripheral bus 180, and peripheral device 19 or multimedia device 190. Data may flow in either direction-from the CPU core to die peripheral device and vice versa. Data may also be stored in and retrieved from the memory subsystem comprising the memory controller 120 and memory device 130. Thus, data from the multimedia device 190 may be provided to d e memory 130, and die CPU 100 reads from the memory to obtain the data.
• data from the multimedia device 190 may flow over the peripheral bus 180, through the bus bridge 170 to die system bus 110, through the bus I/O 160, and over the bus structure 175 to the RX FIFO 200.
• the CPU retrieves the data over CPU local bus 80.
• Data to be transmitted to die multimedia device from the CPU core flows over the CPU local bus 80 to the TX FIFO 300.
• the multimedia device retrieves the data from die TX FIFO 300 via die bus structure 175, bus I/O 160, system bus 110, bus bridge 170, and peripheral bus 180.
• the RX and TX FIFOs appear to d e CPU 100 as if diey are LI cache units.
• the FIFO's have the same access rights as cache memory and generally are as fast as or faster than cache memory. Accesses to the FIFO's tirus is faster dian DRAM memory accesses with little of die latency problems inherent to DRAM memory accesses. In other words, FIFO accesses by the CPU 100 are similar to cache hits, and thus have reduced latency compared to main memory accesses.
• Multimedia devices typically have real time processing requirements and data rates. This is generally not true for other tasks handled by the CPU. Processing rate also varies among different multimedia devices. Differences in these real time dependencies make data communication problematic. For example, data in the FIFO buffers may be overwritten if the CPU stores data in the buffer faster than the multimedia device can retrieve it. Thus, in one embodiment die processor is programmed witii die isochronous rate of the multimedia device. Synchronizing processing rates between the CPU and die multimedia device efficiently enables data to be written into a FIFO buffer at the same rate the data is retrieved. Thus, valid data in the buffers will not be overwritten.
• die preferred embodiment includes several ways to overcome this problem including the use of interrupt signals, adjusting in real-time die effective data rate of the CPU, and adjusting the clock rate of the FIFO buffers.
• the RX FIFO 200 and TX FIFO 300 preferably contain logic circuitry to generate interrupt signals.
• the RX FIFO 200 includes a FIFO buffer 202 and a logic circuit 204.
• the FIFO buffer 202 is coupled to the CPU local bus 80 and die bus structure 175.
• Logic circuit 204 generates a plurality of signals shown collectively as signal 205. These signals preferably represent interrupt signals which ⁇ ue either received by die system interrupt controller or provided to a pin, such as die NMI pin, of the CPU core 100 as described below.
• the logic circuit 204 generates one or more of the interrupt signals in response to the excess capacity signal 203.
• Excess capacity signal 203 monitors me excess storage capacity of the FIFO buffer 202 to indicate the amount of me FIFO buffer available for storage of new data. Specifically, excess capacity signal 203 indicates whether only one memory position in FIFO buffer 202 contains valid data, whedier the FIFO buffer is half-full of data, whedier the FIFO buffer is completely full of data, or whedier some other number of memory locations contains valid data. This predetermined number of locations may be programmable or fixed (i.e. , hardwired).
• Interrupt signal 210 is generated when the excess capacity signal 203 indicates only one position in the FIFO buffer 202 contains valid data.
• Interrupt signal 220 is generated when die signal 203 indicates diat one-half of die FIFO's memory locations are full.
• Interrupt signal 230 is generated when d e excess capacity signal indicates all of d e FIFO is full of data.
• interrupt signal 240 is generated upon a predetermined number of locations in FIFO buffer 202 becoming full.
• logic circuit 304 generates a plurality of signals shown collectively as signal 305. These signals preferably represent interrupt signals which are either received by the system interrupt controller or provided to a pin, such as die NMI pin, of the CPU core 100.
• the CPU core first fills the FIFO buffer 302.
• the multimedia device then begins retrieving the data from the buffer.
• Buffer level signal 303 indicates d e amount of data stored in die buffer that has yet to be retrieved by the multimedia device. Based on d e status of buffer level signal 303, logic circuit 304 generates one or more of die interrupt signals 310, 320, 330, and 340.
• Interrupt signal 310 is generated when d e buffer level signal 303 indicates only one position in the FIFO buffer 302 contains valid data; that is, all but one memory positions of the buffer have been retrieved by d e multimedia device.
• Interrupt signal 320 is generated when die buffer level signal 303 indicates that one-half of die FIFO's memory have yet to be read by die multimedia device.
• interrupt signal 330 is generated when die multimedia device has retrieved enough data from the buffer so that only a predetermined number of memory locations in the buffer have yet to be retrieved.
• the corresponding interrupt is generated and used by die CPU 100 as an indication of when to store more data in die buffer.
• interrupt signal 220 may be implemented exclusievely to indicate to die CPU core when the multimedia device has retrieved all but one memory positions, thereby signalling the CPU to store new data in the TX FIFO.
• Factors such as the data rate, type of data, and processing power of the CPU relative to die multimedia device influence the designer ' s choice of interrupt protocol.
• Multimedia data communication generally is bi-direcdonal-from die multimedia device 190 to the CPU core 100, and vice versa.
• die multimedia device requests control of the peripheral bus 180 from the bus bridge 170.
• the bus bridge 170 grants control of the peripheral bus to the multimedia device 190.
• the multimedia device dien places its data (including address, data, and control bits) on the peripheral bus and the bus bridge then tr.ansmits that data to die RX FIFO 200 via the system bus 110, bus I/O 160, .and bus structure 175.
• the multimedia data preferably comprises addresses which are mapped to die RX FIFO 200
• the multimedia data received on bus structure 175 from die system bus 110 is stored in FIFO buffer 202.
• some preferred level of capacity i.e. , only 1 position filled, half filled, completely filled, or X number of positions filled as described above
• excess capacity signal 203 signals the logic circuit 204 of this capacity condition.
• die logic circuit generates die corresponding interrupt signal 305 which is received by die CPU core 100. This interrupt signal triggers the CPU to retrieve multimedia data from the RX FIFO 200 over the CPU local 80.
• FIGS 2 and 3B illustrate the preferred embodiment for communicating data from the CPU core 100 to the multimedia device 190 and follows a similar scheme to that for multimedia device-to-CPU communication described above.
• the CPU core 100 begins filling die TX FIFO buffer 302 with data targeted for d e multimedia device.
• the multimedia device retrieves some or all of the data from the buffer through the bus I/O 160. system bus 110, bus bridge 170 and peripheral bus 180.
• buffer level signal 303 directs the logic circuit 304 to generate an interrupt signal reflective of die buffer's data level (i.e. , only 1 position filled, half filled, or X number of positions filled). This interrupt signal is received preferably by die CPU core 100 indicating a need for the CPU core to write more data to die transmit FIFO buffer 304.
• multimedia data may be communicated between multimedia device 190 and CPU core 100 through an RX FIFO 400 and TX FIFO 500 without passing through die bus I/O, system bus, and bus bridge 170.
• This architecture is beneficial when the data to an from the multimedia device constitutes a serial stream of data, and not parallel as in the embodiment described above.
• Serial data from the multimedia device can be written direcdy into the RX FIFO 400 over signal line 192 and ultimately retrieved by CPU core 100 via d e CPU local bus 80.
• Data from the CPU core 100 can be written into die TX FIFO 500 and retrieved by die multimedia device 190 over serial signal line 194.
• the parallel nature of the CPU local bus 80 necessitates the conversion of serial multimedia data received over signal line 192 to parallel form. Further, parallel data from the CPU core to be transmitted to the multimedia device 190 must be converted to serial form for transmission over serial signal line 194.
• the RX FIFO 400 and TX FIFO 500 preferably incorporate logic to convert data between serial and parallel forms. Parallel-to-serial and serial- to-parallel conversion blocks are shown in Figure 5A and 5B.
• a serial-to-parallel converter 401 converts serial data received from multimedia device 190 over signal line 192.
• the data is dien placed on a bus 406.
• die RX FIFO 400 performs identically to RX FIFO 200 with data being read from the FIFO buffer 402 over the CPU local bus 80.
• E-xcess capacity signal 403 is similar to excess capacity signal 203 in Figure 3A. Specifically, signal 403 reflects the excess capacity level of the FIFO buffer 402.
• Logic circuit 404 uses excess capacity signal 403 to generate one or more of the interrupts 410. 420, 430, and 440 shown collectively as signal 405.
• the interrupt signals are used by the CPU core 100 to indicate when to retrieve data from the FIFO buffer.
• Interrupt signal 410 represents die condition in which only one FIFO buffer position contains data.
• Signal 420 represents the condition in which die buffer is half-full.
• Signals 420 represents the condition in which die buffer completely full.
• signal 440 represents the condition when X positions contain data.
• TX FIFO 500 performs identically to TX FIFO 300 ejXcept that the parallel data read from a FIFO buffer 502 is placed on a parallel bus 507 and convened to a serial stream of data by parallel-to-serial convener 506.
• the functions of buffer level signal 503 and interrupt signal 505 comprising signals 510, 520, and 530 correspond to buffer signal 303 and interrupt signals 305 in Figure 3B.
• Figures 6A-6D show an alternative to the embodiment of Figures 3 A, 3B, 5 A, and 5B in which registers .are used instead of interrupt signals to overcome the problems of mismatched data rates, diereby ensuring the efficient flow of data between die CPU core 100 and multimedia device 190.
• registers instead of interrupt signals
• the CPU writes to and reads from die FIFO buffers at a predetermined nominal rate approximating the multimedia data rate.
• die RX FIFO's logic circuit 204 periodically updates a register 250 to indicate how full the FIFO buffer 202 is with data from the multimedia device.
• the logic circuit 204 may store in the register a number indicating the percentage of die total buffer space free for the multimedia device to store more data.
• the number stored in die register might reflect the percentage of the buffer space presently containing data to be read by die CPU.
• die register provides a way for die CPU to infer how full the buffer has become so that the CPU CM adjust its effective data rate if necessary.
• the CPU will increase temporarily its effective data retrieval rate.
• a faster effective rate can be achieved eidier by retrieving the same quantity of data more often man die nominal rate or retrieving less data at die same rate.
• the buffer is only 5% full, it may be desired for die CPU to slow down its effective retrieval rate to let the multimedia device 190 temporarily fill the buffer faster than die CPU 100 retrieves the data. Slower effective retrieval rates are achieved eidier by reading die same quantity of data less often tiian the nominal rate or reading more data at die same nominal rate.
• Figure 6B ejXempiifies die TX FIFO using a register 350 instead of interrupts.
• the CPU 100 writes data to d e TX FIFO buffer 302 at a nominal rate approximating the isochronous rate of the multimedia device.
• the CPU periodically checks the status of register 350.
• Register 350 is updated by logic circuit 304 to reflect die level of data in the FTFO buffer.
• the CPU core 100 can determine how much of die data has been retrieved by the multimedia device 190 and thus, whedier d e multimedia device is able to retrieve data from the FTFO buffer at d e same rate at which the CPU stores data. If, for example, register 350 indicates the FTFO buffer is almost filled, die CPU can use diat information to slow down its effective rate of storing data in the buffer. Slowing die effective rate is accomplished similar to diat described above for slowing die retrieval rate with respect to d e RX FIFO. That is, the CPU core 100 can store the same quantity of data less often than the nominal rate or storing more data at d e nominal rate.
• registers 450 in Figure 6C and 550 in Figure 6D parallels that of registers 250 and 350, respectively, for die serial embodiment of d e present invention.
• An alternative embodiment to the use of interrupt signals or changing the effective data rate of the CPU is to dynamically change me TX or RX FIFO clock rate as needed to output more or less data depending on die amount of data stored in die FIFO.

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• 1997
  • 1997-09-25 EP EP97943566A patent/EP0928452A1/de not_active Withdrawn
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