WO1998013767A9

WO1998013767A9 - Multimedia data controller

Info

Publication number: WO1998013767A9
Application number: PCT/US1997/017197
Authority: WO
Filing date: 1997-09-25
Publication date: 1998-07-09

Abstract

The present invention discloses a system and method for communicating real-time, multimedia data between a host CPU and an external multimedia device using a pair of first-in-first-out (FIFO) buffers. Data from the CPU is stored in a first FIFO buffer and subsequently retrieved by the multimedia device. Data from the multimedia device is stored in a second FIFO buffer and subsequently retrieved by the CPU for processing. The FIFO buffers provide indications to the CPU for the CPU to store more data in the first FIFO buffer and for the CPU to retrieve data from the second FIFO buffer.

Description

TITLE: MULTIMEDIA DATA CONTROLLER

BACKGROUND OF THE INVENTION

1 Field of the Invention

The present invention relates generally to the design and development of microprocessor and memory systems within computers More particularly, die present invention relates to transmission of data between a CPU and devices external to the CPU Still more particularly, the present invention relates to data transmission between a CPU and a multimedia device using receive and transmit FIFO buffers

2 Description of the Relevant Art

The continuing proliferation of computer development and applications has lead to computer systems that incorporate "multimedia" capability That is. present computer technology allows for the processing of audio and video information as such information is generated by devices external to the central processing unit (CPU) or computer For example, multimedia computers mav present video images and/or audio tracks from a medium such as a CD-ROM

Fig 1 shows a typical pπor art computer svstem depicting the elements relevant to the present discussion A central processing unit (CPU) core 10 is coupled to an LI cache svstem 15 and a bus Input/Output (I/O) device 16 over a CPU local bus 8 The LI cache svstem 15 tvpicallv includes a cache controller and a cache SRAM (not shown) The CPU core 10. LI cache svstem 15. and bus I O 16 may be implemented as separate discrete components but preferably are integrated onto a single chip processor as indicated bv dashed box 9

The bus I/O device 16 couples the CPU local bus 8 to a memory bus 11 A memory control unit or memory controller 12 also couples to the memory bus 11 A second level cache, referred to as an L2 cache 7. couples to the memory bus 11 and also couples to the memory control umt 12 The memory control unit 12 couples to a memory device 13 The memory device 13 tvpicallv is dynamic random access memory (DRAM)

A bus bridge 17 couples the memory bus 11 to a peripheral bus 18 Peripheral devices 1 are coupled to the peripheral bus A multimedia device 1 0 represents one type of peripheral device which is coupled to the peripheral bus 18 Examples of multimedia devices are CD-ROM drives, graphics cards, video recorders sound cards, modems and the like The CPU core 10 and peripheral devices 19 and 190 communicate through the bus bπdge 17 in different wavs A simple communication scheme allows data from the CPU core 10 to be placed on the CPU local bus 11 and transferred through the bus I/O device 16. memory bus 11. bus bπdge 17, peripheral bus 18, and to a peripheral device/multimedia device Data communication from the peripheral devices 19 and 190 to the CPU core 1 follows the same path, albeit m the reverse order The CPU core 10 tvpicallv engages m multiple activities such as access cycles to the memory device 1 through memory control umt 12. accesses to the LI cache SRAM 15. as well as receiving and transmitting data to a vaπetv of peripheral devices 19/190 The CPU core 10 often performs digital signal processing (DSP) operations on video and audio data to and from the multimedia device 190 Digital signal processing is a time-consuming, iterative process often involving vast amounts of data and requiring a large portion of the CPU's computing resources Multimedia data often compπses real-time, isochronous data (< e . video and audio data metered out in regular time peπods) For real-time data, such as video and audio, to be effectively observed bv the human user, it must be performed (e g , video data displa ed on a monitor or sound data provided to speakers) at the same rate at which the data was acquired oπginally Anv delavs m processmg will render music or motion pictures, for example, unintelligible and useless As such, multimedia data often requires processmg by the CPU "on the fly" or "in real

These demands on the CPU's processing power often renders direct communication between a multimedia device 1 0 and the CPU core 10 impractical because the CPU generally can receive, transmiL and process data much faster than the multimedia device 190 Direct data transmission between CPU and multimedia device, consequently, mav not be the most efficient transmission scheme in light of other processing demands on the CPU Consequently, data from the multimedia device mav be stored or buffered in the memory 13 Once in the memory, the CPU core 10 can retneve the multimedia data more efficiently as larger blocks of data can be retπeved with less access overhead than widi datum by datum transfers directly between multimedia device and CPU

However, latency effects renders memory structures incapable of allowing real-time blocks of data to be stored, retπeved. and processed without detπmentallv effecting the data's real-time nature Further, latency in accessing DRAM often is unpredictable. For example, video data that is stored m the memory device 13 and peπodically processed bv the CPU core 10 with the latency inherent to the svstem may result in dropped frames or missed audio data, thereby resulting in jerky video and poor audio quality

Buffeπng the multimedia data directly in the LI cache system instead of mam memory might be beneficial as cache memory accesses are faster and more efficient than accesses to system memory However, directly buffeπng die multimedia data in the LI cache system 1 and bypassing main memory storage is impractical because cache memones cannot be used directly by peπpheral devices to store data Therefore, it would be desirable to have a multimedia data controller capable of allowing real-time CPU processing of multimedia data while accomplishing other CPU-related tasks. Such a controller v ould be able to effectively process and display video images and broadcast audio signals without losing the quality or usefulness inherent to the information

SUMMARY OF THE INVENTION

The problems outlined above are in large part solved by the teaclungs of the present invention The present invention incorporates a system and method for communication of data between a central processing unit (CPU) and one or more peπpheral devices attached to a peπpheral bus The svstem compπses a CPU coupled to a svstem or memory bus. The system bus in turn couples to a peπpheral bus through a bus bπdge. One or more peπpheral devices are coupled to the peπpheral bus. The present invention compπses one or more memory buffers coupled to the CPU which stores peπpheral and/or multimedia data transferred to or from the one or more peπpheral devices Data to and from the peπpheral device is stored temporaπly in a first-in-first-out (FTFO) buffer. Both the CPU and peπpheral device receive interrupt signals when retπeval of the data from the FTFO buffer is preferred. The retπeving device then obtains the stored data from the FTFO buffer.

In one embodiment, the memory buffer includes separate transmit and receive buffers. Data from the CPU is first stored in the transmit FTFO buffer, and once the transmit FTFO buffer becomes sufficiently full, the peπpheral device requests control over the peπpheral bus to retneve data from the FTFO buffer. The peπpheral bus wπtes data to the receive FTFO buffer via the peπpheral bus and bus bπdge for subsequent retπeval by the CPU In another embodimenL data stored m the respective transmit and receive buffers is transferred directly to/from die peπpheral devices There data stored in die transmit FIFO buffer is read by the peπpheral or multimedia devices without passing through the bus bπdge and penpheral bus. Data wπtten into the receive FIFO buffer also is commumcated direcUv between the penpheral device and FTFO buffer without passmg through the peπpheral bus and bus bπdge

Tlie FTFO buffer produces interrupt signals which reflect the amount of the FIFO buffer currently in use for stoπng data These interrupt signals are used bv the CPU and the peπpheral device as an indication of when to retrieve data from tlie FTFO buffers Instead of using interrupts to indicate when the FIFO buffer contains data to be retneved for processing, the CPU mav monitor tlie level of data in the FTFO In response, the CPU mav adjust the effective processing rate so as to ensure tlie FTFO maintains an optimal level of data Finally, die CPU mav adjust tlie clock rate of tlie FIFO buffer to maintain an optimal data level

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent upon reading die following detailed descπption and upon reference to the accompanying drawings m which

Fig 1 is a block diagram representation of a typical pπor art computer svstem

Fig 2 is an exemplary block diagram of the parallel implementation of the prefeπed embodiment

Fig 3 A is a block diagram of the receive FIFO contained in the parallel implementation

Fig 3B is a block diagram of the transmit FIFO contained in the parallel implementation

Fig 4 is an exemplary block diagram of tlie seπal data implementation of the preferred embodiment

Fig 5A is a block diagram of the receive FTFO contained m the seπal implementation

Fig 5B is a block diagram of the transmit FIFO contained in the seπal implementation

Figs 6A-6D are exemplary block diagrams including registers for coπecting mismatched data rates

While die invention is susceptible to vaπous modifications and alternative forms, specific embodiments thereof are shown bv wav of example in the drawings and will herein be descπbed in detail It should be understood however, diat die drawing and detailed descπption diereto are not intended to limit the invention to tlie particular form disclosed, but on the contrary, die intention is to cover all modifications, equivalents and alternatives falling within the spiπt and scope of the present invention as defined bv die appended claims

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referπng now to Fig 2. a multimedia data controller is shown consistent with the prefeπed embodiment A central processing umt (CPU) core 100 is coupled to an LI cache svstem 150 and bus I O device 160 over a CPU local bus 80 Also attached to die CPU local bus is a transmit first-in-first-out buffer (TX FTFO) 300 and receive FIFO buffer (RX FIFO) 200 according to die present invention A parallel bus structure 175 couples die RX and TX FTFOs to the bus I O 160 Preferably, these components are integrated into a single processor chip, as indicated bv the dashed box 20

The bus I/O 160 connects the CPU local bus 80 to a svstem bus or memory bus 110 A memory control unit 120 also couples to die svstem bus 110 The memory control umt 120 couples to a memory device 130 which preferably includes dynamic random access memory (DRAM) L2 cache 70 couples to the memory control umt 120 and to the svstem bus 110

A bus bπdge 170 provides connectrvitv between the svstem bus 110 and a peπpheral bus 180 External devices 19 and multimedia devices 190 couple to die penpheral bus 180 Tlie penpheral bus 180 preferably compnses a PCI (Penpheral Component Interconnect) bus, but may compnse other bus types such those complying idi die IS A and EISA standards Thus, the penpheral bus 180 is not limited to anv particular bus architecture Multimedia device 190 represents such media devices as graphicsΛideo cars or svstems. audio cards or svstems. MPEG decoders/encoders. CD ROM svstems. video cassette recorders, video cameras, and the like. Data to and from die peπpheral devices 19 and multimedia device 190 mav flow along the path including the CPU core 100, CPU local bus 80 bus I/O 160. svstem bus 110. bus bπdge 170. peπpheral bus 180. and peπpheral device 19 or muldmedia device 190 Data mav flow in either direction-from die CPU core to die penpheral device and vice versa Data mav also be stored in and retrieved from the memory subsystem compπsmg die memory controller 120 and memory device 130 Thus, data from the multimedia device 190 mav be provided to die memorv 130 and the CPU 100 reads from die memorv to obtain the data

According to die present invention, data from die multimedia device 190 mav flow over the peπpheral bus 180. diroug die bus bπdge 170 to die system bus 110. through the bus I/O 160. and over the bus structure 175 to the RX FIFO 200 Once in the RX FTFO 200, the CPU retπeves the data over CPU local bus 80 Data to be transmitted to die multimedia device from die CPU core flows over the CPU local bus 80 to die TX FTFO 300 Subsequendv. die multimedia device retπeves the data from the TX FTFO 300 via die bus structure 175, bus I/O 160. svstem bus 110. bus bπdge 170. and peπpheral bus 180 The RX and TX FTFOs appear to the CPU 100 as if thev are LI cache units For example, die FIFO's have die same access πghts as cache memorv and generally are as fast as or faster than cache memorv Accesses to die FIFO's dius is faster than DRAM memorv accesses idi little of die latency problems inherent to DRAM memorv accesses In odier words. FIFO accesses bv die CPU 100 are similar to cache hits, and thus have reduced latency compared to main memorv accesses Muldmedia devices tvpicallv have real ϋme processing requirements and data rates Tlus is generally not true for odier tasks handled bv die CPU Processing rate also vanes among different mulUmedia devices Differences in these real time dependencies make data communication problemadc For example, data in die FIFO buffers may be ovenvπtten if die CPU stores data m the buffer faster than the multimedia device can retneve it Thus, in one embodiment die processor is programmed with the isochronous rate of the muldmedia device. Synchronizing processing rates between the CPU and the multimedia device efficiendv enables data to be written into a FIFO buffer at die same rate die data is retπeved Thus, valid data in the buffers will not be overwritten Tlus approach, however, places generally unacceptable limitations on the operating system and is further limited because the data rate mav change for a multimedia device duπng different modes of operation and certainly different multimedia devices have different data rates Accordingly, the prefeπed embodiment includes several wavs to overcome this problem including the use of interrupt signals, adjusting m real-time the effective data rate of the CPU. and adjusting the clock rate of die FIFO buffers

The embodiment including interrupt signals will now be descπbed Refemng now to Figs 2. 3 A. and 3B. die RX FIFO 200 and TX FIFO 300 preferably contain logic circuitry to generate interrupt signals In Fig 3 A. an embodiment of the RX FTFO 200 is shown As shown, the RX FIFO 200 includes a FIFO buffer 202 and a logic circuit 204 The FTFO buffer 202 is coupled to the CPU local bus 80 and the bus structure 175 Logic circuit 204 generates a plurality of signals shown collectively as signal 205 These signals preferably represent interrupt signals which are either received bv the svstem interrupt controller or provided to a pin. such as the NMI pin. of the CPU core 100 as descnbed below The logic circuit 204 generates one or more of the interrupt signais in response to the excess capacity signal 203 Excess capacity signal 203 monitors the excess storage capacity of the FTFO buffer 202 to indicate the amount of the FTFO buffer available for storage of new data Specifically, excess capacity signal 203 indicates whether onlv one memorv position in FIFO buffer 202 contains valid data, whether the FIFO buffer is half- full of data, whether the FTFO buffer is completely full of data, or whether some other number of memorv locaUons contains valid data This predetermined number of locations mav be programmable or fixed (/ e . hardwired) Based on the status of excess capacity signal 203, logic circuit 204 generates an appropπate interrupt Interrupt signal 210 is generated when the excess capacity signal 203 indicates onlv one position m the FTFO buffer 202 contains valid data Interrupt signal 220 is generated when the signal 203 indicates that one-half of the FIFO's memorv locadons are full Interrupt signal 230 is generated when the excess capacity signal indicates all of the FTFO is full of data Finally, interrupt signal 240 is generated upon a predetermined number of locations in FTFO buffer 202 becoming fiill

Similarly, in Fig 3B. logic circuit 304 generates a plurality of signals shown collectively as signal 305 These signals preferabl^y represent interrupt signals which are either received bv die svstem interrupt controller or provided to a pin. such as the NMI pin. of die CPU core 100 The CPU core first fills die FIFO buffer 302 The mulϋmedia device then begins retπevmg the data from the buffer Buffer level signal 303 indicates the amount of data stored in the buffer that lias vet to be retrieved bv the muldmedia device Based on the status of buffer level signal 303 logic circuit 304 generates one or more of the interrupt signals 310, 320. 330. and 340 Interrupt signal 310 is generated when the buffer level signal 303 indicates only one position m the FIFO buffer 302 contains valid data, that is. all but one memory positions of the buffer have been retπeved bv the multimedia device Interrupt signal 320 is generated when the buffer level signal 303 indicates that one-half of the FIFO's memorv have vet to be read bv die mulϋmedia device Finally, interrupt signal 330 is generated when die mulϋmedia device has retrieved enough data from the buffer so that onlv a predetermined number of memorv locaϋons in die buffer have yet to be retrieved Moreover, once die mulϋmedia device has retπeved enough data from the FIFO buffer so as to create one of these buffer level condiϋons. the coπesponding interrupt is generated and used bv the CPU 100 as an indication of when to store more data in die buffer

One or more of die interrupt signals may be used in a given implementation For example, die svstem designer mav desire to implement interrupt signal 220 to tngger e CPU core 100 to retneve data from the receive FIFO buffer 202 once the buffer becomes half-full of data from the mulϋmedia device The data can be retπeved and processed while the buffer is filling up idi new data On the transmit side, interrupt signal 310 mav be implemented exclusively to indicate to the CPU core when die multimedia device has retπeved all but one memorv positions, thereby signalling the CPU to store new data m the TX FTFO Factors such as the data rate, type of data, and processing power of the CPU relative to the mulϋmedia device influence the designer's choice of interrupt protocol The operation of the present invention will now be descπbed with reference to the prefeπed embodiment shown in Figs 2. 3 A. and 3B Mulϋmedia data communicaUon generally is bi-direcϋonal-from the mulUmedia device 190 to the CPU core 100. and vice versa When die multimedia device contains data to be processed by the CPU, the mulϋmedia device requests control of die peπpheral bus 180 from the bus bπdge 170 According to predetermined and commonlv known bus control schemes, die bus bndge 170 grants control of the penpheral bus to the mulϋmedia device 1 0 The mulϋmedia device then places its data (including address, data, and control bits) on the penpheral bus and the bus bπdge then transmits that data to the RX FTFO 200 via the svstem bus 110. bus I/O 160 and bus structure 175 The mulUmedia data preferably compπses addresses which are mapped to die RX FTFO 200

In Fig 3A. die multimedia data received on bus structure 175 from the svstem bus 110 is stored in FTFO buffer 202 When die FTFO buffer reaches some prefeπed level of capacity (/ e , onlv 1 position filled, half filled, completely filled, or X number of positions filled as descπbed above), excess capacity signal 203 signals die logic circuit 204 of this capacity condition In response, the logic circuit generates die corresponding interrupt signal 305 which is received bv the CPU core 100 This interrupt signal tnggers die CPU to retneve mulϋmedia data from die RX FTFO 200 over the CPU local 80 Figs 2 and 3B illustrate the preferred embodiment for communicating data from the CPU core 100 to die mulUmedia device 1 0 and follows a similar scheme to mat for mulϋmedia device-to-CPU communicaϋon descπbed above The CPU core 100 begins filling the TX FTFO buffer 302 with data targeted for the mulϋmedia device The multimedia device retπeves some or all of the data from the buffer through the bus I/O 160. svstem bus 110. bus bπdge 170 and penpheral bus 180 When the level of data m the buffer drops to a predetermined level, buffer level signal 303 directs the logic circuit 304 to generate an interrupt signal reflective of the buffer^'s data level (/ e . only 1 position filled, half filled, or X number of positions filled) Tlus interrupt signal is received preferably bv the CPU core 100 indicating a need for the CPU core to vvnte more data to the transmit FTFO buffer 304

In an alternative embodiment as shown in Figs 4, 5A. and 5B, mulϋmedia data mav be commumcated between mulUmedia device 190 and CPU core 100 through an RX FTFO 400 and TX FTFO 500 without passing dirough die bus I/O. svstem bus. and bus bπdge 170 Tlus architecture is beneficial when the data to an from die mulUmedia device constitutes a seπal stream of data, and not parallel as in the embodiment descπbed above

Seπal data from the mulUmedia device can be written direcdv into die RX FTFO 400 over signal line 192 and ultimately retπeved bv CPU core 100 via die CPU local bus 80 Data from the CPU core 100 can be written into die TX FIFO 500 and retπeved by die mulUmedia device 190 over seπal signal line 194 The parallel nature of the CPU local bus 80 necessitates the conversion of seπal multimedia data received over signal line 192 to parallel form Further, parallel data from die CPU core to be transmitted to the mulϋmedia device 190 must be converted to seπal form for transmission over senal signal line 194 The RX FTFO 400 and TX FIFO 500 preferably incorporate logic to convert data between seπal and parallel forms Parallel-to-seπai and seπal- to-parallel conversion blocks are shown in Fig 5A and 5B In Fig 5 A seπal-to-parallel converter 401 converts senal data received from mulUmedia device 190 over signal line 192 Tlie data is then placed on a bus 406 From this point on, the RX FTFO 400 performs identically to RX FIFO 200 with data being read from die FTFO buffer 402 over the CPU local bus 80 Excess capacity signal 403 is similar to excess capacity signal 203 in Fig 3 A Specifically, signal 403 reflects die excess capacity level of the FTFO buffer 402 Logic circuit 404 uses excess capacity signal 403 to generate one or more of the interrupts 41 . 20. 430. and 440 shown collectively as signal 405 The interrupt signals are used bv die CPU core 100 to indicate when to retneve data from die FTFO buffer Interrupt signal 410 represents the condition in which onlv one FTFO buffer position contains data Signal 420 represents die condition in which the buffer is half-full Signals 420 represents die condition in which die buffer completely full Finally, signal 440 represents die condition when X posmons contain data In Fig 5B TX FTFO 500 performs identically to TX FTFO 300 except that the parallel data read from a FIFO buffer 502 is placed on a parallel bus 507 and converted to a seπal stream of data by parallel-to-senal converter 506 Parallel-to-senal converter 506 m turn, outputs the seπal data stream on line 194 for transmission to die multimedia device 190 Tlie fiincuons of buffer level signal 503 and interrupt signal 505 compπsing signals 510. 520. and 530 correspond to buffer signal 303 and interrupt signals 305 in Fig 3B

Figs 6A-6D show an alternative to the embodiment of Figs 3 A. 3B, 5A. and 5B in which registers are used instead of interrupt signals to overcome die problems of mismatched data rates, therebv ensunng the efficient flow of data between the CPU core 100 and multimedia device 190 When using a register instead of interrupt signals, die CPU writes to and reads from the FTFO buffers at a predetermined nominal rate approximating the mulUmedia data rate

In Fig 6A. die RX FIFO's logic circuit 204 penodicallv updates a register 250 to indicate how full die FTFO buffer 202 is with data from the multimedia device For example, the logic circuit 204 mav store m the register a number mdicaϋng the percentage of die total buffer space free for die mulumedia device to store more data

Alternatively, the number stored in die register might reflect the percentage of the buffer space presendv containing data to be read bv the CPU In either case, the register provides a way for the CPU to infer how full die buffer has become so that the CPU can adjust its effective data rate if necessary For instance, if it is desired for the CPU to retneve data from the RX FTFO so that the buffer never becomes more dian 50% full and if the register 250. in fact. indicates die buffer is 70% full, the CPU will increase temporaπlv its effective data retneval rate A faster effective rate can be achieved either bv retπevmg the same quantity of data more often man the nominal rate or retπevmg less data at the same rate AlternaUvelv. if the buffer is onlv 5% full, it mav be desired for the CPU to slow down its effecϋve retneval rate to let the multimedia device 190 temporaπlv fill the buffer faster than the CPU 100 retneves die data Slower effective retπeval rates are achieved either bv reading die same quantity of data less often than die nominal rate or reading more data at the same nominal ratu

Fig 6B exemplifies die TX FTFO using a register 350 instead of interrupts The CPU 100 wπtes data to the TX FTFO buffer 302 at a nominal rate approximating die isochronous rate of the mulUmedia device To prevent die CPU 100 from overwriting data in die FTFO buffer when die mulUmedia does not retrieve data as fast as the CPU stores data in the buffer, die CPU penodicallv checks the status of register 350 Register 350 is updated bv logic circuit 304 to reflect die level of data the FTFO buffer From die status of register 350. the CPU core 100 can determine how much of die data has been retπeved by the multimedia device 1 0 and thus, whether the multimedia device is able to retneve data from die FIFO buffer at the same rate at which the CPU stores data If. for example, register 350 indicates die FTFO buffer is almost filled, the CPU can use that information to slow down its effective rate of stoπng data in the buffer Slowing die effecϋve rate is accomplished similar to that descπbed above for slowing die retπeval rate widi respect to the RX FIFO That is. die CPU core 100 can store die same quantity of data less often than the nominal rate or stoπng more data at the nominal rate Tlie function of registers 450 in Fig 6C and 550 in Fig 6D parallels that of registers 250 and 350. respectively, for die seπal embodiment of the present invention

An alternative embodiment to the use of interrupt signals or changing the effective data rate of die CPU is to dynamically change die TX or RX FTFO clock rate as needed to output more or less data depending on the amount of data stored in the FTFO

Numerous vaπauons and modifications will become apparent to those skilled in die art once die above disclosure is fiillv appreciated It is intended that the following claims be interpreted to embrace all such vaπauons and modifications

Claims

WHAT IS CLAIMED IS:

1 A svstem for processing data from a penpheral device compnsing

a central processing umt (CPU),

a bus input/output device coupled to said CPU

a svstem bus coupled to said bus input/output device.

a peπpheral bus coupled to said svstem bus

a peπpheral device coupled to said peπpheral bus, and

a memorv buffer coupled to said CPU and coupled to said bus input/output device, wherein said memorv buffer is adapted for onlv stonng data to be transfeπed to said penpheral device and data received from said peπpheral device.

wherein said penpheral device and said CPU exchange information dirough said memorv buffer

2 The svstem of claim 1. wherein informauon is stored in said memorv buffer bv said peπpheral device, wherein said information stored in said memorv buffer bv said peπpheral device is retπeved bv said CPU

3 The svstem of claim 1. wherein information is stored in said memorv buffer bv said CPU. wherein said informauon stored in said memorv buffer bv said CPU is retπeved bv said penpheral device

4 Tlie svstem of claim 1. further compπsing

a main memorv coupled to said svstem bus for stoπng code and data, and

a cache svstem coupled to said CPU for stonng a portion of said code and data stored m said main memorv

5 The svstem of claim 1 , w herein said memorv buffer produces a first signal lndicaUv e of the amount of data stored in said memorv buffer bv the peπpheral device that has not been retneved bv the CPU

6 The svstem of claim 5 vv herein die first signal indicative of die amount of data stored in said memorv buffer bv die penpheral device compπses a first interrupt signal, and wherein said CPU uses said first interrupt signal to initiate retrieving data from said memorv buffer stored in said memorv buffer bv said peπpheral device

7 The svstem of claim 5, w herein said memorv buffer produces a second signal indicative of the amount of data stored in said memorv buffer bv the CPU diat has not been retπeved bv the peπpheral device 8 Tlie svstem of claim 7 w herein die second signal indicative of the amount of data stored in said memorv buffer bv die CPU compnses a second interrupt signal, and wherein said CPU uses said second interrupt signal to initiate stonng more data m said memorv buffer for retπeval bv said peπpheral device

9 The svstem of claim 1 vv herein said memorv buffer compnses a receive buffer and a transmit buffer. wherein die receive buffer stores information received from the peπpheral device and destined for die CPU and the transmit FIFO buffer stores informauon received from the CPU and destined for die peπpheral device

1 The svstem of claim 1. herein said penpheral device compnses a multimedia device, and wherein said informauon compnses real-Ume data

11 The svstem of claim 1 vv herein said memorv buffer is a FTFO memorv buffer

12 A computer svstem compnsing.

a CPU

a memorv buffer coupled to said CPU

a peπpheral bus.

an external device coupled to said memorv buffer.

a penpheral device coupled to said penpheral bus. wherein said peπpheral device includes a senai input/output port.

a seπal data line coupled to said seπal input/output port and to said CPU.

wherein seπal data from die penpheral device is stored in die memorv buffer for retneval bv said CPU. and

wherein data stored in die memorv buffer bv die CPU is transmitted to the penpheral device in senal form

13 The computer svstem of claim 12 wherein said memory buffer converts the seπal data receiv ed from die external device to parallel form for transmission to die CPU

14 The system of claim 12 vv herein said memory buffer produces a first signal lndicauv e of die amount of data stored m said memorv buffer bv die external device diat has not been retneved by the CPU

15 The svstem of claim 14 wherein the first signal indicative of die amount of data stored in said memorv buffer bv the external device compπses an interrupt signal

16 Tlie system of claim 15 herein said CPU uses said interrupt signal to initiate retπeving data from said memory buffer stored in said buffer bv said external device 17 The system of claim 12. wherein said memorv buffer produces a second signal mdicauve of the amount of data stored in said memorv buffer bv die CPU that has not been retπeved bv the external device

18 The system of claim 17 v herein die second signal mdicauve of die amount of data stored in said memory buffer bv die CPU compπses an interrupt signal

19 The system of clam 18. wherein said CPU uses said interrupt signal to initiate stonng more data in said memorv buffer for retneval bv said external device

20 The computer svstem of claim 12 vv herein die memory buffer compπses a receive buffer and a transnut buffer wherein die receive buffer stores die information received from die external device and the transmit buffer stores informauon received from the CPU

21 The computer svstem of claim 20. w herein die transmit buffer converts die data stored in the memorv buffer bv said CPU to a seπal suing of data for retπeval bv die external device

22 The computer svstem of claim 12. wherein said external device compnses a multimedia device

23 The computer svstem of claim 22. herein said informauon compπses reai-ume data

24 The computer svstem of claim 12. herein die memorv buffer is a FIFO memory buffer

25 A svstem for processing data from a peπpheral device compnsing

a central processing umt (CPU).

a CPU local bus coupled to said CPU

a bus input/out device coupled to said CPU local bus.

a system bus coupled to said bus input/output device.

a peπpheral device coupled to a peπpheral bus.

a bus bπdge device for coupling said system bus to said penpheral bus.

and a FIFO memorv buffer coupled to said CPU and coupled to said bus input/output device herein said FIFO memory buffer compπses a transmit FTFO buffer for stoπng data from die CPU to be retneved bv die penpheral device and said FTFO memorv buffer compnses a receive FIFO buffer for stoπng data received from die peπpheral device to be retneved bv the CPU

26 The system of claim 25. wherein said data first stored in said receive FTFO buffer bv said peπpheral device is retπeved bv said CPU before odier data stored in said receive FIFO buffer is retneved 27 The svstem of claim 26. wherein said data first stored in said transmit FIFO buffer bv said CPU is retneved bv said penpheral device before other data stored in said transmit FIFO buffer is retneved

28 The svstem of claim 27. wherein die receive FIFO buffer compnses a register that is updated bv die receive 5 FIFO buffer to indicate the amount of die FIFO buffer containing data from the penpheral device yet to be retneved by die CPU

29 The system of claim 27. w herein die transmit FIFO buffer compnses a register that is updated bv die transmit FIFO buffer to indicate die amount of data stored in die transmit FTFO buffer by die CPU that has vet to be ( ) retneved bv die peπpheral device

30 The svstem of claim 28. wherein die transmit FIFO buffer compnses a register mat is updated bv die transmit FIFO buffer to indicate die amount of data stored in the transmit FTFO buffer bv the CPU that has vet to be retneved bv die peπpheral device 5

31 The svstem of claim 30 wherein data is commumcated between die FTFO memorv buffer and die penpheral device dirough a bus input/output device, a svstem bus wherein die bus input/output device couples die CPU local bus to die svstem bus. a peπpheral bus. and a bus bπdge device diat couples the svstem bus to die peπpheral bus

0 32 The svstem of claim 30. herein data is commumcated in senal form between the FIFO memorv buffer and the penpheral device over senal signal lines coupled between die FIFO memorv buffer and the peπpheral device

33 The svstem of claim 28. w erein said peπpheral device compπses a multimedia device

5 34 The svstem of claim 33 wherein said informauon compnses real-time data