EP0927462A1 - Dispositif pour reduire l'amplitude des courts-circuits d'un semi-conducteur de puissance commande par circuit mos, deconnectable, sans verrouillage - Google Patents

Dispositif pour reduire l'amplitude des courts-circuits d'un semi-conducteur de puissance commande par circuit mos, deconnectable, sans verrouillage

Info

Publication number
EP0927462A1
EP0927462A1 EP97944696A EP97944696A EP0927462A1 EP 0927462 A1 EP0927462 A1 EP 0927462A1 EP 97944696 A EP97944696 A EP 97944696A EP 97944696 A EP97944696 A EP 97944696A EP 0927462 A1 EP0927462 A1 EP 0927462A1
Authority
EP
European Patent Office
Prior art keywords
emitter
collector
circuit
power semiconductor
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97944696A
Other languages
German (de)
English (en)
Inventor
Manfred Bruckmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0927462A1 publication Critical patent/EP0927462A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0828—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in composite switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6877—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the control circuit comprising active elements different from those used in the output circuit

Definitions

  • the invention relates to a device for reducing the short-circuit amplitude of a switchable, non-latching, MOS-controlled power semiconductor according to the preamble of claim 1.
  • Power semiconductor switches with a MOS control input which have a purely capacitive control input as a common feature, are preferably used in power converters, for example for speed-controlled drives and uninterruptible power supply systems. These components enable high switching frequencies and require very little control power, since only the input capacity is reloaded for switching. Because of the favorable short-circuit properties of such power semiconductor switches, simple protection concepts can be implemented which allow short-circuit currents to be switched off via the control input.
  • the power semiconductor switch In the event of a short circuit, e.g. can be caused by a short circuit at the inverter output, the power semiconductor switch is loaded with a short-circuit current amplitude, which depends essentially on the amplification characteristic of the component and thus on the level of the control voltage acting at the control input. In the event of a short circuit, ten times the nominal current of the component can easily be achieved.
  • the trench IGBT is an example of this. Due to the finer structuring of the MOS portion of the IGBT, the on-resistance of the MOS-FET is reduced and almost diode-like transmission properties can be achieved. On the other hand, the short-circuit properties of these components, which are optimized for passage, deteriorate because a much higher short-circuit current is established. With the voltage present in the event of a fault, this causes the silicon chip to heat up more than in the previously used components. If no further precaution is taken, the component must be switched off again quickly from this fault.
  • the maximum short-circuit time is roughly reduced by the factor with which the short-circuit amplitude has increased. With the trench IGBT, the duration of the short circuit must therefore be reduced to one third to one fifth of the remaining time. In the worst case, this is 2 ⁇ sec.
  • the short-circuit case is determined by means of a protective circuit, a so-called desaturation monitor.
  • the power semiconductor is opened with such a protective circuit
  • Desaturation is monitored, ie it is checked whether a collector-emitter voltage exceeds the value that occurs when the power semiconductor is saturated. If the short-circuit case is detected, the shutdown must be initiated by means of a control element. This creates a period of time or a critical table time slot, due to the dead time of the special circuit measures in which or in which the MOS-controlled power semiconductor cannot be protected.
  • a control method for improving the overcurrent switch-off behavior of power semiconductor switches with a MOS control input is known from German patent 39 05 645.
  • the control voltage is generally lowered at the end of each conductive phase by rapidly partially discharging the input capacitance of the power semiconductor switch. This ensures that occurring short-circuit currents before the actual switch-off, namely the rapid reversal of the power semiconductor switch from the conductive to the blocking state, are first reduced to a small, near the operationally occurring maximum value with low current steepness, at which the power semiconductor switch can then be safely switched off .
  • the control of the MOS-controlled power semiconductor takes place with auxiliary voltage sources which are connected to the Load potential (emitter of the power semiconductor) are connected (FIG 4 of this German patent).
  • auxiliary voltage sources which are connected to the Load potential (emitter of the power semiconductor) are connected (FIG 4 of this German patent).
  • two voltage sources are provided in the usual way, the positive control voltage from the first voltage source for switching on the MOS-controlled power semiconductor being activated by driving a switch-on transistor of a driver stage and the negative control voltage from the second voltage source for switching off by driving a switch-off transistor of this driver stage of the MOS-controlled power semiconductor are placed on the gate-emitter path.
  • a discharge network consisting of a zener diode and a discharge transistor is provided between the gate connection and the emitter connection in this circuit arrangement.
  • the discharge transistor is turned on for a short time immediately after the activation of the drive transistor until the input capacitance of the gate-emitter path has discharged via the Zener diode to a voltage approximately the threshold voltage of the Zener diode.
  • the switch-off transistor of the driver stage is then switched on to switch off the MOS-controlled power semiconductor.
  • this discharge network Since the input capacity of the power semiconductor is quickly partially discharged, the components of this discharge network must be designed for the high discharge current.
  • This discharge network is also activated by changing from a conducting to a blocking phase. That is, by means of a further circuit, it must first be recognized that a short circuit has occurred. Then the switch-on transistor of the driver stage must be blocked. Immediately after this transistor has been blocked, the discharge transistor of the discharge network is turned on, and this becomes conductive with a delay time. Thus, because of the critical time slot that occurs, a MOS-controlled power semiconductor optimized for transmission cannot be protected.
  • a control device for a MOS-controlled power semiconductor is known from European laid-open specification 0 190 925, which has a driver stage, a voltage source and a circuit for reducing the control voltage (FIG. 12 of this laid-open specification).
  • This circuit for reducing the control voltage has a transistor and a resistor, which are connected as emitter followers.
  • the input of this circuit to reduce the tax voltage is connected to an output of a circuit for monitoring the collector-emitter voltage of the MOS-controlled power semiconductor.
  • This circuit has a voltage divider consisting of two resistors and a Zener diode which is electrically connected in parallel with the second resistor.
  • the power loss of the control device increases with the immunity to interference.
  • the short-circuit amplitude of a MOS-controlled power semiconductor switch optimized for transmission cannot be quickly reduced with this circuit arrangement, since the collector-emitter voltage is observed at high potential. That is, as soon as it is recognized that there is an overload or short circuit depending on the collector-emitter voltage, the short-circuit amplitude has reached a value at which a reduction would no longer achieve anything with regard to the protective effect.
  • a device for reducing the short-circuit amplitude of a switchable, non-latching, MOS-controlled power semiconductor according to the preamble of claim 1 is known from EP 0 467 682 A2. This known device is approximately shown in FIG. 1 and is described in the following:
  • this known device has a limiting circuit 6 and a collector-emitter monitoring 8.
  • This device is arranged in a control unit assigned to the MOS-controlled power semiconductor TLI, of which only one driver stage 10 and two control voltage sources UH1 and UH2 are shown for the sake of clarity.
  • the collector-emitter monitoring 8 is linked on the input side via a decoupling diode Dl to the collector terminal C of the non-latching, MOS-controlled power semiconductor TLI which can be switched off.
  • this decoupling diode D1 is connected to a positive terminal of the first control voltage source UH1 by means of a resistor R1.
  • control voltage source UH1 is linked to the emitter terminal E of the power semiconductor TLI, the emitter potential forming the reference potential M of the control circuit for the control voltage U sc .
  • the second control voltage source UH2 is connected with its positive connection to the emitter connection E of the power semiconductor TLI, its negative connection being a negative one
  • Reference potential "-” forms “+” compared to the positive reference potential, which is formed by the positive connection of the first voltage source UHL.
  • the driver stage 10 which has complementary transistors T2 and T3, is connected between these two reference potentials “+” and “-” of the control unit.
  • the transistor T2 is an npn transistor which is driven when the power semiconductor TLI is switched on.
  • the transistor T3 is a pnp transistor which is driven when the power semiconductor TLI is switched off.
  • the common base connection 12 of these two complementary transistors T2, T3 form the control connection 14 of the driver stage 10, a base resistor R4 for basic current setting being connected between this control connection 14 and the common base connection 12 of the complementary transistors T2, T3.
  • this driver stage 10 At the control input of this driver stage 10 there is a control voltage U st based on the reference potential M of the control unit.
  • the driver stage 10 On the output side, the driver stage 10 is electrically conductively connected to the gate terminal G of the MOS-controlled power semiconductor TLI via a resistor RG.
  • This resistor is also called the control circuit resistor or referred to as a gate resistor.
  • the level of the control current pulses occurring when switching on and off is determined as a function of the voltage value of the control voltage sources UH1 and UH2.
  • the voltage value of the first voltage source UH1 is, for example, between 15 to 20 V
  • the voltage value of the second control voltage source UH2 is, for example, 0 to 15 V.
  • the collector-emitter monitoring 8 consists of a Zener diode D2 and a resistor R2, which are electrically connected in series. The connection point of these two components D2 and R2 form the output 16 of the collector-emitter monitoring 8.
  • the reference voltage Uc ⁇ ref of the collector-emitter voltage U CE of the MOS -controlled power semiconductor TLI set.
  • the limiting circuit 6, which is arranged between the base terminal 12 of the driver stage 10 and the negative reference potential "-", consists of a transistor T4 and a Zener diode D3, which are electrically connected in series.
  • the base connection of the transistor T4 forms the input of the limiting circuit 6, which is linked to the output of the collector-emitter monitoring 8.
  • the value of the control voltage U st during the lowering is determined by means of the Zener voltage of the Zener diode D3.
  • the gate connection G of the MOS-controlled power semiconductor TLI is connected by means of the transistor T2 to the positive reference potential "+", so that depending on the voltage value of the first control voltage source UH1 and of the control resistor RQ the amount of the current pulse is determined. Since the collector terminal C of the MOS-controlled power semiconductor TLI is connected to the intermediate circuit rail 2, the voltage value of the collector-emitter voltage UC E is equal to the value of the intermediate circuit voltage + U Z , that is to say when the collector-emitter voltage U CE is switched on, it is greater than his Reference voltage Uc ⁇ r ef • This is recognized by the collector-emitter monitoring 8 and the limiting circuit 6 is switched on.
  • the control voltage U st is reduced to a value determined by the Zener diode D3 and the power semiconductor TLI is switched on with a reduced charging current.
  • the collector-emitter voltage U CE has dropped below its reference value U CEr ef, there is no short circuit. That is, the output signal of the collector-emitter monitoring 8 changes its level, whereby the limiting circuit 6 is switched off.
  • the full voltage is now applied to the gate G of the MOS-controlled power semiconductor TLI in order to reduce the flow losses.
  • the power semiconductor TLI is loaded with a short-circuit amplitude which is essentially dependent on the amplification characteristic of the power semiconductor TLI and thus on the level of the control voltage acting at the gate connection G. U st depends. If no measures are taken to limit the short-circuit current amplitude or to switch off the power semiconductor TLI, the short-circuit amplitude can reach ten times the nominal current of the power semiconductor TLI. Such an overload, however, can be modern power semiconductors, especially power optimized for transmission. semiconductor, only endure for a short time (2 ⁇ ec). In the case of power semiconductor switches optimized for passage, this time is so short that switch-off measures cannot take effect in good time.
  • the short-circuit amplitude increases with a circuit rate-dependent current rise rate. With this current increase, the value of the collector-emitter voltage U CE of the MOS-controlled power semiconductor TLI also increases. As soon as the collector-emitter voltage U CE is equal to its reference voltage UcEref, the control voltage U sc is suddenly lowered to the voltage defined by the Zener diode D3, so that the gate voltage is also reduced accordingly. As a result, the short-circuit amplitude can no longer increase to approximately ten times the nominal current of the power semiconductor TLI, but is limited to approximately two to four times the nominal current.
  • the limiting circuit 6 operates during the switch-on process until the collector-emitter voltage U CE is equal to its reference voltage UcEref. If the switching speed of the power semiconductor TLI is not to change, the control circuit resistance R G must be reduced in accordance with the voltage reduction. So that the limiting circuit 6 is not yet active during the switch-on process, a capacitor is provided in the device according to EP 0 467 682 A2, which, together with the resistor R2, defines a delay time. This delay time is so chooses that the limiting circuit 6 can only become active when the power semiconductor TLI is switched on. This measure has some disadvantages, which are mentioned and remedied in this European publication.
  • the invention is based on the object of further developing this device for reducing the short-circuit amplitude of a switchable, non-latching MOS-controlled power semiconductor in such a way that the aforementioned disadvantages no longer occur.
  • the disadvantage of the changing switching speed does not occur with a driver stage which is designed as a current source for the switching process.
  • a driver stage which is designed as a current source for the switching process.
  • an additional transistor and a resistor are provided, which are arranged according to the characterizing part of claim 1 when the transistor of the driver stage is switched on.
  • the control circuit resistance is bridged by means of a diode when switching on.
  • the limiting circuit has a second transistor which is connected to an output of a gate-emitter monitor which is connected on the input side via a resistor to the gate connection of the power semiconductor.
  • a gate-emitter monitor which is connected on the input side via a resistor to the gate connection of the power semiconductor.
  • the decoupling diode is connected on the anode side via the resistor to the first control voltage source to the gate terminal of the switchable, non-latching, MOS-controlled power semiconductor. This also evaluates the gate-emitter voltage for reducing the short-circuit amplitude. In this embodiment, a limit for the collector-emitter voltage and for the gate-emitter voltage is shared. Compared to the second embodiment of the device according to the invention, this gives a particularly simple embodiment of the device according to the invention.
  • a capacitor is provided between the output of the collector-emitter monitor and the collector of the transistor of the limiting circuit or between the base and emitter of the transistor of the limiting circuit.
  • a resistor is provided between the output of the collector-emitter monitoring and the first control voltage source.
  • this resistor together with a resistor of the collector-emitter monitoring, forms a voltage divider which reduces the voltage of the control voltage source in such a way that the transistor of the limiting circuit is just not yet open. The undesired delay time of the transistor of the limiting circuit is thus eliminated and the reduction in the control voltage begins immediately.
  • FIGS. 5 and 6 each show an advantageous embodiment of the first and third devices according to the invention, whereas the
  • FIGS. 9 and 10 each show a variant of a further advantageous embodiment of the third device according to the invention.
  • FIGS. 1 to 10 each show the turn-off, non-latching, MOS-controlled power semiconductor TLI, which is connected with its collector connection C to a positive DC link rail 2, which carries a positive DC link voltage + U 2 and the like Emitter connection E on the one hand with an AC connection 4 and on the other hand with a collector connection of another power semiconductor, which is not shown for reasons of clarity, drawn with a wider line width for better identification. This is intended to show that this part of the illustrations in FIGS. 1 to 10 represents the power part.
  • driver stage 10 which is designed as a current source for the switch-on process, this disadvantage is no longer noticeable.
  • driver stage 10 is the
  • FIG 2 shown.
  • An additional transistor T5 and a resistor R5 are provided so that the effect of a current source results during the E switching.
  • the additional transistor T5 is electrically connected with its collector-emitter path parallel to the base-emitter path of the complementary transistor T2.
  • the resistor R5 is connected between the base and the emitter of the additional transistor T5.
  • the MOS-controlled power semiconductor TLI is switched on by means of a current source by means of this additional transistor T5 and the resistor R5. Therefore, the control circuit resistance R G is no longer required for the switch-on process.
  • the resistor RG is bridged by a diode D4 for the switch-on process in such a way that this resistor R G is only effective for the switch-off process.
  • FIG. 3 shows a second device according to the invention with a control unit according to FIG. 1.
  • the limiting circuit 6 has a second transistor T8, whose base connection is connected to an output 18 of a gate-emitter monitoring 20 is.
  • This gate-emitter monitoring 20 is linked on the input side by means of a resistor R8 to the gate terminal G of the MOS-controlled power semiconductor TLI.
  • This gate-emitter monitor 20 consists of a series connection of a Zener diode D5 and a resistor R9. The connection point of these two components D5 and R9 form the output 18 of the gate-emitter monitoring 20.
  • the reference voltage U GE re f can be set for the gate-emitter voltage U GE become.
  • the second transistor T8 of the limiting circuit 6 is electrically connected in series with the transistor T4 of this circuit 6.
  • the gate-emitter voltage U GE is also evaluated here.
  • the limiting circuit 6 is only activated when the collector-emitter voltage UC E is equal to its reference voltage Uc ⁇ re f and the gate-emitter voltage U GE is equal to its reference voltage UcEre.
  • the limiting circuit 6 is not activated, as in the first embodiment according to FIG. 1, but only when a short circuit has occurred. This eliminates the need to reduce the value of the control circuit resistance RQ.
  • FIG. 4 shows a third device according to the invention, which differs from the known device according to FIG. 1 in that the decoupling diode D1 on the anode side via the resistor R1 instead of the first control voltage source UH1 now has the gate terminal G of the MOS-controlled power semiconductor TLI is connected. It is thereby achieved that the limiting circuit 6 is only activated when the gate emitter voltage U GE and the collector emitter voltage U CE are each equal to a reference voltage. Compared to the embodiment according to FIG. 3, no additional components are needed to evaluate the gate emitter voltage U GE .
  • the current gain of a transistor T2 or T3 of the driver stage 10 is not sufficient to be able to switch on a MOS-controlled power semiconductor TLI.
  • the transistor T2 or T3 can be connected upstream of an emitter follower.
  • the Darlington circuit thus created can be regarded as a transistor. But you can also connect two complementary transistors T6 and T2 or T7 and T3 to a Darlington circuit, as shown in FIG 5.
  • the transistor T6 or T7 essentially determines the function, while the transistor T2 or T3 merely amplifies the current. So that the transistor T6 or T7 becomes the emitter follower, a resistor R6 or R7 according to FIG. 5 is provided.
  • the driver stage 10 is provided with complementary Darlington circuits T6, R6, T2 and T, R7, T3 instead of with complementary transistors T2 and T3.
  • FIG. 6 shows the third device according to the invention with a control unit with a driver stage 10 according to FIG. 5 in more detail.
  • FIG. 7 shows a first variant of an advantageous embodiment of the third device according to the invention according to FIG. 4, FIG. 8 showing a second variant of this advantageous embodiment of the third device according to the invention.
  • This first variant of the advantageous embodiment differs from the embodiment according to FIG. 4 in that a capacitor C1 is provided between the output 16 of the collector-emitter monitoring 8 and the collector of the transistor T4 of the limiting circuit 6.
  • the capacitor Cl is provided between the base and emitter of the transistor T4 of the limiting circuit 6 (FIG 8).
  • This capacitor C1 forms, together with the resistors R1 and R2, a timing element whose time constant indicates the change in the reduction in the control voltage U st .
  • the control voltage U st is reduced along a straight line with a negative slope, the time constant indicating the negative slope.
  • the control voltage U St is reduced along a hyperbola. That is, with this connection of the transistor T4 of the limiting circuit T6, a time function of the collector ⁇ mitter voltage of this transistor T4 is achieved, whereby a sof switching on of the limiting circuit 6 is achieved, which does not result in a sudden change in the gate-emitter voltage, as a result of which overvoltage occurring when the short-circuit current is switched off is limited.
  • FIGS. 9 and 10 each show a first and a second variant of a further advantageous embodiment of the third device according to the invention according to FIG. 4.
  • the embodiment according to FIG. 9 or 10 differs from the embodiment according to FIG. 7 or 8 in that a resistor R11 is provided between the output 16 of the collector-emitter monitoring 8 and the positive reference potential "+" of the control unit.
  • This resistor R11 forms a voltage divider with the resistor R2 of the collector-emitter monitoring 8.
  • This voltage divider is dimensioned such that the transistor T4 of the limiting circuit 6 is not yet turned on. This avoids that an unnecessarily long time passes until the control voltage of the transistor T4 has reached the threshold value at which it switches on, that is to say the desired effect of the limiting circuit 6 occurs.
  • the collector-emitter monitoring 8 and the limiting circuit 6 are related to the negative reference potential “-” of the control unit. However, there is also the possibility of referring these units 8 and 6 of the device to the reference potential M of the control unit without the mode of operation changing.

Landscapes

  • Electronic Switches (AREA)
  • Power Conversion In General (AREA)

Abstract

L'invention concerne un dispositif destiné à réduire l'amplitude des courts-circuits d'un semi-conducteur de puissance (TL1) commandé par circuit MOS, déconnectable, sans verrouillage, comprenant une unité de commande présentant un étage d'attaque (10) comportant deux transistors complémentaires (T2, T3), un contrôle collecteur-émetteur (8) et un montage de limitation (6) qui est prévu entre une entrée (12) et un potentiel de référence ('-') de l'étage d'attaque (10), dans lequel ce montage de limitation (6) est lié, côté entrée, avec une sortie (16) du contrôle collecteur-émetteur (8), laquelle est connectée, côté entrée, via une diode de découplage (D1), avec la connexion collecteur (C) du semi-conducteur de puissance (TL1). Cette diode de découplage (D1) est reliée, côté anode, via une résistance (R1), avec une borne positive d'une première source de tension de commande (UH1) de l'étage d'attaque (10). Conformément à l'invention, il est prévu un transistor supplémentaire (T5) et une résistance (R5), ce transistor supplémentaire (T5) étant monté électriquement en parallèle avec son segment collecteur-émetteur par rapport au secteur base-émetteur du transistor de mise en circuit (T2) de l'étage d'attaque (10), et la résistance (R5) étant montée entre la base et l'émetteur dudit transistor supplémentaire (T5). La résistance (RG) du circuit de commande est shuntée au moyen d'une diode (D4). De cette façon, le dispositif connu de réduction de l'amplitude de courts-circuits d'un semi-conducteur de puissance (TL1) du type précité se trouve amélioré de telle sorte que sa vitesse de commutation ne soit plus modifiée.
EP97944696A 1996-09-20 1997-09-10 Dispositif pour reduire l'amplitude des courts-circuits d'un semi-conducteur de puissance commande par circuit mos, deconnectable, sans verrouillage Withdrawn EP0927462A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19638619 1996-09-20
DE1996138619 DE19638619A1 (de) 1996-09-20 1996-09-20 Vorrichtung zur Verminderung der Kurzschlußamplitude eines abschaltbaren, nichteinrastenden, MOS-gesteuerten Leistungshalbleiters
PCT/DE1997/002020 WO1998012816A1 (fr) 1996-09-20 1997-09-10 Dispositif pour reduire l'amplitude des courts-circuits d'un semi-conducteur de puissance commande par circuit mos, deconnectable, sans verrouillage

Publications (1)

Publication Number Publication Date
EP0927462A1 true EP0927462A1 (fr) 1999-07-07

Family

ID=7806366

Family Applications (1)

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EP97944696A Withdrawn EP0927462A1 (fr) 1996-09-20 1997-09-10 Dispositif pour reduire l'amplitude des courts-circuits d'un semi-conducteur de puissance commande par circuit mos, deconnectable, sans verrouillage

Country Status (3)

Country Link
EP (1) EP0927462A1 (fr)
DE (1) DE19638619A1 (fr)
WO (1) WO1998012816A1 (fr)

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DE19918966A1 (de) * 1999-04-27 2000-11-02 Daimler Chrysler Ag Verfahren zur Überstromabschaltung eines Bipolartransistors mit isoliert angeordneter Gateelektrode und Vorrichtung zur Durchführung des Verfahrens
DE10143487C2 (de) * 2001-09-05 2003-07-24 Siced Elect Dev Gmbh & Co Kg Schalteinrichtung mit einem gegen Überlast gesicherten Leistungsschaltelement
DE10236532C1 (de) * 2002-08-09 2003-08-14 Semikron Elektronik Gmbh Schaltungsanordnung zur Ansteuerung von Leistungstransistoren
DE202006002762U1 (de) * 2006-02-21 2006-05-04 Patent-Treuhand-Gesellschaft für elektrische Glühlampen mbH Schaltung zum Schalten eines spannungsgesteuerten Transistors
DE102016212211B4 (de) * 2016-07-05 2019-02-21 Siemens Aktiengesellschaft Kurzschlusserkennung
DE102022207192A1 (de) * 2022-07-14 2024-01-25 Robert Bosch Gesellschaft mit beschränkter Haftung Überwachungsvorrichtung und Verfahren zur Überwachung eines Sperrwandlers, Sperrwandler

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KR900008276B1 (ko) * 1985-02-08 1990-11-10 가부시끼가이샤 도시바 2단계차단동작을이용한절연게이트바이폴라트랜지스터용보호회로
EP0354435B1 (fr) * 1988-08-12 1995-12-20 Hitachi, Ltd. Circuit d'attaque pour transistor à grille isolée; et son utilisation dans un circuit de commutation, dans un dispositif de commutation de courant, et dans un système à moteur à induction
DE3905645A1 (de) * 1989-02-21 1990-08-23 Licentia Gmbh Ansteuerverfahren zur verbesserung des ueberstromabschaltverhaltens von leistungshalbleiterschaltern mit mos-steuereingang
DE4012382A1 (de) * 1990-04-18 1991-10-24 Licentia Gmbh Verfahren und anordnung zum abschalten eines leistungshalbleiterschalters mit mos-steuereingang bei ueberstroemen
JP2669117B2 (ja) * 1990-07-19 1997-10-27 富士電機株式会社 電圧駆動形半導体素子の駆動回路

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Also Published As

Publication number Publication date
WO1998012816A1 (fr) 1998-03-26
DE19638619A1 (de) 1998-04-02

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