EP0919026A1 - Vorrichtung und verfahren zur änderung von befehlssequenzen - Google Patents

Vorrichtung und verfahren zur änderung von befehlssequenzen

Info

Publication number
EP0919026A1
EP0919026A1 EP98930843A EP98930843A EP0919026A1 EP 0919026 A1 EP0919026 A1 EP 0919026A1 EP 98930843 A EP98930843 A EP 98930843A EP 98930843 A EP98930843 A EP 98930843A EP 0919026 A1 EP0919026 A1 EP 0919026A1
Authority
EP
European Patent Office
Prior art keywords
program
sequence
memory
address
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98930843A
Other languages
English (en)
French (fr)
Inventor
Azad Nassor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CP8 Technologies SA
Original Assignee
Bull CP8 SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull CP8 SA filed Critical Bull CP8 SA
Publication of EP0919026A1 publication Critical patent/EP0919026A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/66—Updates of program code stored in read-only memory [ROM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs

Definitions

  • the present invention relates to a method for modifying code sequences and the associated device.
  • the present invention makes it possible to mask certain so-called sensitive operations carried out by the central unit.
  • the address windows [Adrdeb_i, Adrfin_1] are stored by increasing addresses, this facilitating the reading of the table. Consequently, the values located in the intervals] Adrfin_i, Adrdeb_i + 1 [are address values of the non-sensitive program.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Storage Device Security (AREA)
EP98930843A 1997-06-13 1998-06-12 Vorrichtung und verfahren zur änderung von befehlssequenzen Withdrawn EP0919026A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9707321 1997-06-13
FR9707321A FR2764716B1 (fr) 1997-06-13 1997-06-13 Procede de modification de sequences de code et dispositif associe
PCT/FR1998/001228 WO1998057255A1 (fr) 1997-06-13 1998-06-12 Procede de modification de sequences de code et dispositif associe

Publications (1)

Publication Number Publication Date
EP0919026A1 true EP0919026A1 (de) 1999-06-02

Family

ID=9507918

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98930843A Withdrawn EP0919026A1 (de) 1997-06-13 1998-06-12 Vorrichtung und verfahren zur änderung von befehlssequenzen

Country Status (5)

Country Link
US (1) US6536034B1 (de)
EP (1) EP0919026A1 (de)
JP (1) JP3563412B2 (de)
FR (1) FR2764716B1 (de)
WO (1) WO1998057255A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2995030B2 (ja) * 1998-03-31 1999-12-27 三洋電機株式会社 コンピュータシステム、並びにコンピュータシステムにおけるプログラム及びデータの修正方法
US6260157B1 (en) 1999-02-16 2001-07-10 Kurt Schurecht Patching of a read only memory
GB2349485B (en) * 1999-04-23 2003-12-10 Ibm Application management
FR2795838B1 (fr) * 1999-06-30 2001-08-31 Bull Cp8 Procede de securisation du traitement d'une information sensible dans un module de securite monolithique, et module de securite associe
US7152224B1 (en) * 2000-11-21 2006-12-19 Microsoft Corporation Versioned project associations
FR2818766A1 (fr) * 2000-12-21 2002-06-28 Bull Cp8 Procede de securisation de l'execution d'un programme implante dans un module electronique a microprocesseur, ainsi que le module electronique et la carte a microcircuit associes
JP2005332221A (ja) * 2004-05-20 2005-12-02 Renesas Technology Corp 記憶装置
JP4038216B2 (ja) * 2005-05-10 2008-01-23 ファナック株式会社 シーケンスプログラム編集装置
US9348730B2 (en) * 2007-01-31 2016-05-24 Standard Microsystems Corporation Firmware ROM patch method
FR2928754B1 (fr) * 2008-03-13 2012-05-18 Sagem Securite Carte a circuit integre ayant un programme d'exploitation modifiable et procede de modification correspondant
US9348597B2 (en) * 2008-06-30 2016-05-24 Infineon Technologies Ag Device and method for bypassing a first program code portion with a replacement program code portion
US8200888B2 (en) * 2008-06-30 2012-06-12 Intel Corporation Seek time emulation for solid state drives
US8930894B2 (en) * 2008-10-08 2015-01-06 Oracle America, Inc. Method and system for executing an executable file
FR2999845A1 (fr) * 2012-12-14 2014-06-20 Thomson Licensing Methode d'activation d'un mode de maintenance dans un dispositif electronique et dispositif associe
DE102015211458A1 (de) * 2015-06-22 2016-12-22 Robert Bosch Gmbh Verfahren und Vorrichtung zum Absichern einer Programmzählerstruktur eines Prozessorsystems und zum Überwachen der Behandlung einer Unterbrechungsanfrage
US9892024B2 (en) 2015-11-02 2018-02-13 Sony Interactive Entertainment America Llc Backward compatibility testing of software in a mode that disrupts timing
CN116643140A (zh) * 2022-02-15 2023-08-25 华为技术有限公司 集成电路及集成电路的测试方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4542453A (en) * 1982-02-19 1985-09-17 Texas Instruments Incorporated Program patching in microcomputer
JPS5969749A (ja) * 1982-10-14 1984-04-20 Sharp Corp 電子写真複写機の光学装置
US4831517A (en) * 1986-10-10 1989-05-16 International Business Machines Corporation Branch and return on address instruction and methods and apparatus for implementing same in a digital data processing system
US5623665A (en) * 1992-01-13 1997-04-22 Sony Corporation Electronic apparatus for patching a read-only memory
US5748981A (en) * 1992-10-20 1998-05-05 National Semiconductor Corporation Microcontroller with in-circuit user programmable microcode
US5485629A (en) * 1993-01-22 1996-01-16 Intel Corporation Method and apparatus for executing control flow instructions in a control flow pipeline in parallel with arithmetic instructions being executed in arithmetic pipelines

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9857255A1 *

Also Published As

Publication number Publication date
JP2000500897A (ja) 2000-01-25
US6536034B1 (en) 2003-03-18
FR2764716A1 (fr) 1998-12-18
JP3563412B2 (ja) 2004-09-08
WO1998057255A1 (fr) 1998-12-17
FR2764716B1 (fr) 2001-08-17

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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