EP0916450A1 - Method and apparatus for polishing semiconductor wafers - Google Patents
Method and apparatus for polishing semiconductor wafers Download PDFInfo
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- EP0916450A1 EP0916450A1 EP98119004A EP98119004A EP0916450A1 EP 0916450 A1 EP0916450 A1 EP 0916450A1 EP 98119004 A EP98119004 A EP 98119004A EP 98119004 A EP98119004 A EP 98119004A EP 0916450 A1 EP0916450 A1 EP 0916450A1
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- Prior art keywords
- polishing
- radial
- areas
- semiconductor wafers
- temperatures
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- 238000005498 polishing Methods 0.000 title claims abstract description 122
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 235000012431 wafers Nutrition 0.000 title claims description 63
- 238000000034 method Methods 0.000 title claims description 15
- 239000004744 fabric Substances 0.000 claims description 11
- 238000005496 tempering Methods 0.000 claims description 8
- 238000007517 polishing process Methods 0.000 claims description 6
- 238000005259 measurement Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 101100298222 Caenorhabditis elegans pot-1 gene Proteins 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000265 homogenisation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
- 238000012549 training Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/11—Lapping tools
- B24B37/12—Lapping plates for working plane surfaces
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/005—Control means for lapping machines or devices
- B24B37/015—Temperature control
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
Definitions
- the invention relates to a method for polishing Semiconductor wafers with at least one side at least a semiconductor wafer against one covered with a polishing cloth Polishing plate is pressed and polished, the Semiconductor wafer and the polishing plate a relative movement To run.
- the invention also relates to a device which is suitable for performing the method.
- planarization of a semiconductor wafer using a chemo-mechanical Polishing is an important processing step in the process flow for the production of a flat, defect-free and smooth semiconductor wafer.
- This polishing step provides the final form in many production processes and thus decisively determining the surface properties Step before reusing the semiconductor wafer as raw material for the production of electrical, electronic and microelectronic components.
- Objectives of Polishing processes are particularly high Flatness and parallelism of the two disc sides, the removal pretreatment of damaged surface layers ("damage removal") and the reduction of the microroughness of the Semiconductor wafer.
- polishing processes When polishing a group of several semiconductor wafers (“single side batch polishing") the semiconductor wafers with one side on the front a carrier plate mounted by between the side and the carrier plate has a positive and non-positive connection, for example by adhesion, gluing, kitten or vacuum application, will be produced.
- the semiconductor wafers mounted on the carrier plate so that it is a Form a pattern of concentric rings.
- the free sides of the disc are fed with a polishing agent against a polishing plate over which a polishing cloth is stretched is pressed with a certain polishing force and polished.
- the carrier plate and the polishing plate are thereby usually rotated at different speeds.
- the necessary polishing force is provided by a pressure stamp hereinafter referred to as "polishing head” transfer the back of the carrier plate.
- a variety of used polishing machines are designed so that they over have several polishing pots and accordingly several carrier plates be able to record.
- Double side polishing With double side polishing (DSP) the front and back are polished simultaneously by several semiconductor wafers between two covered with polishing cloths, upper and lower polishing plates.
- the semiconductor wafers lie in thin guide cages ("wafer carrier"), which are referred to as rotor disks and in a similar form when lapping semiconductor wafers be used.
- wafer carrier thin guide cages
- Double-sided polishing processes and devices are always for the treatment of groups of semiconductor wafers designed ("batch polishing").
- Polished semiconductor wafers often have pages that are not parallel to each other but in cross-section the shape of a wedge take in.
- the shape of the wedge can be described with the term linear thickness variation describe.
- the linear thickness variation is the largest measured difference in thickness between two measuring points, the on the same diameter symmetrical to the center of the semiconductor wafer lie.
- the measuring points are usually symmetrical on a circle that is a distance of, for example 6 mm from the edge of the wafer of the semiconductor wafer. Is the edge the semiconductor wafer, which faces the edge of the carrier plate, thicker (thinner) than the edge of the pane, towards the center of the carrier plate shows, one speaks of a positive (negative) linear Wedging.
- TTV total thickness variation
- a wedge of a semiconductor wafer caused by the polish is ultimately the result of an uneven Material removal. It can arise if the carrier plate radially deformed during polishing by its own weight or a certain radial wedge, due to the manufacturing process Has. Sometimes there is also wear and tear of the polishing cloth cause that the disc geometry deteriorated in the course of several polishing runs.
- a certain one Basic wedge results even when used ideally level Carrier plates because of the kinematic conditions in the Single disc polishing, which is an inhomogeneous material removal promote.
- EP-4033 A1 proposes intermediate layers made of soft elastic bodies between the polishing pot and the back insert the carrier plate, thereby the carrier plate is deliberately curved a little radially symmetrically.
- the carrier plate In order to can be prevented to a certain extent from the semiconductor wafers be wedge-polished.
- this procedure is cannot be automated and prone to errors, since its success is largely from the experience and care of the operators depends on the width of the liners must select and insert. But even if there are no mistakes made, the wedge of the polished semiconductor wafers remains above a certain limit.
- the present invention solves the problem in polishing of semiconductor wafers an improved uniformity of the To achieve polishing removal, so that in particular the wedge the polished semiconductor wafers is low.
- the invention relates to a method for polishing Semiconductor wafers with at least one side at least a semiconductor wafer against one covered with a polishing cloth Polishing plate is pressed and polished, the Semiconductor wafer and the polishing plate a relative movement execute, characterized in that the semiconductor wafer at least two areas on the polishing plate during polishing sweeps that have certain radial widths and have different temperatures, and tempering agents are provided in the polishing plate, with the aid of which the number, the radial latitudes and the temperatures of the areas before Polishing the semiconductor wafers can be determined.
- the invention further relates to a device for Implementation of the procedure, which is characterized by a Chamber system made of concentric in the polishing plate arranged annular chambers through which a tempering medium flows that a certain, adjustable in each annular chamber Temperature.
- polishing occurs a radially convex temperature profile on the polishing plate, this is partly responsible for the wedge shape of polished semiconductor wafers is.
- the temperature profile causes an inhomogeneous Material removal through the use of the above elastic intermediate layers (e.g. when using ceramic carrier plates that are practically not arched may) or not sufficient (when using carrier plates less rigid material) can be compensated.
- Such compensation is provided by the present invention possible because of the creation of tempered areas specified a radial temperature profile of the polishing plate that decisively determines the material removal.
- the invention allowed to polish the wedge shape of semiconductor wafers set within comparatively wide limits. By the invention can produce semiconductor wafers, which are specifically positive or negative wedge.
- the invention is used for kinematic influences and influences of the carrier plate or the polishing cloth, which too Wedges would lead to compensate and for example an extension of the service life of the polishing cloth to reach.
- the invention can be used both for one-sided polishing (one and Multi-disc polish), as well as for double-sided polish become.
- the invention is illustrated below using the example multi-disc single-side polishing (single-side batch polishing) explained in more detail.
- the semiconductor wafers at least two areas during polishing paint over the polishing plate, which is caused by temperature control in the Polishing pads are kept at certain temperatures.
- the Areas are preferably laid out in concentric rings, taking temperatures from at least two of the ranges differentiate. The number, the radial latitudes and the temperatures the areas are determined before a polishing run. Not excluded is the temperature at which the areas be held during a polishing run change.
- the polishing cloth wears during polishing Semiconductor wafers on a conventional polishing plate are not homogeneous Temperature before.
- the temperature often increases from the edge r / 2 of the polishing plate (r is the radius of the polishing plate) and drops to the center of the polishing plate, making a radial convex temperature profile results.
- r is the radius of the polishing plate
- a homogenization of the temperature profile can be achieved.
- a radially convex temperature profile should be at least two tempered areas can be set up on the polishing plate.
- radial temperature profile are made uniform.
- the number of areas, their radial latitude and the temperatures, on which they are held are before polishing of the semiconductor wafers.
- the basis for the determination can data from an analysis of the geometry previously polished Semiconductor wafers are used, for example the linear thickness variation determined for these semiconductor wafers. Measurement data of the radial temperature profile can also form the basis of the polishing plate during a previous one Polishing run were determined.
- the functional relationship between that after a polish too expected geometry of the semiconductor wafers and the one to be determined Number, width and temperatures of the areas on the The polishing plate is expediently carried out by routine experimentation determined. In such experiments, the number is radial Systematic changes in width and temperature of the areas and the effects on the geometry of the polished semiconductor wafers examined.
- a host computer receives as input data the radial temperature profile, which during a previous polishing run or data on the geometry (for example on the wedge shape) of semiconductor wafers, which polished on a previous polishing run were and is based on the empirically found connection those to achieve a desired one Disc geometry necessary parameters (number, radial width and temperature of the areas).
- FIG. 1 is a preferred embodiment of the claimed device shown schematically.
- the figure shows a vertical section through the device in side view.
- Figure 2 is a horizontal section through the polishing plate the device shown in plan view.
- 3a, 3b and 4a, 4b is shown schematically as the Geometry of semiconductor wafers through the application of the invention can be influenced. Below is only on characteristics pointed out that necessary to illustrate the invention are. Similar features are used in the figures pointed out the same reference numerals.
- FIG. 1 In the shown Embodiment is a single side polishing machine with several polishing pots, one of which can be seen is.
- the polishing pot 1 presses a carrier plate 2 with a polishing force K against a polishing plate covered with a polishing cloth 3 4.
- the carrier plate is, for example, vacuum suction held on the polishing pot.
- the semiconductor wafers 5 are on the front of the carrier plate facing the polishing cloth 3 2 fixed.
- Essential characteristic of the Device are in the polishing plate in concentric Orbital ring chambers through which a tempering medium flows.
- Each annulus becomes independent of one others from a temperature control medium, for example water, flows through, the tempering medium in each annular chamber has certain temperature and the temperatures are different could be.
- the temperature control medium is through flow lines VZ1 to VZ5 pumped into the respective ring chambers and leaves this again through return lines RZ1 to RZ5.
- the Flow and return lines run through a rotating union 6, which is attached to the underside of the polishing plate 4. For the sake of clarity, the supply and return lines are shown interrupted.
- the temperature control medium is from a thermostat 7 at a desired temperature held.
- the thermostat is operated by one Control computer 8 controlled, the target temperatures SZ1 to SZ5 specifies for the temperature control medium in the annular chambers Z1 to Z5.
- the master computer accesses a data store 9 back, stored in the measurement data of previous polishing runs and automatically calculates the Target temperatures.
- the temperature control medium holds a certain one in each annular chamber Temperature upright, so that on the polishing plate radially symmetrical Areas with a characteristic temperature arise that sweep over the semiconductor wafers during polishing.
- the number of available areas depends on the number of the provided ring chambers.
- the radial widths of the areas are of the chosen radial widths of the annular chambers and depending on the temperature of the temperature control medium flows through the annular chambers.
- FIG 2 is a horizontal section through the polishing plate the device shown in Figure 1 in plan view. If the temperature of the temperature control medium in each ring chamber Z1 to Z5 of the temperatures of the tempering medium in the rest Differentiates annular chambers, produce the annular chambers the polishing plate corresponds to the number of annular chambers Number of annular areas. These areas are on a Temperature maintained, which is essentially the temperature of the Temperature control medium in the associated ring chamber corresponds. The Number of areas is correspondingly lower when the temperature of the temperature control medium in two or more neighboring ones Annular chambers is the same.
- Is the temperature of the temperature control medium the same in two adjacent ring chambers results from this an area on the polishing plate whose radial width is approximately the sum of the radial widths of these annular chambers corresponds. 2 to 5 annular chambers are preferred provided.
- the radial widths of the annular chambers are preferably 25 to 120% of the diameter of the to be polished Semiconductor wafers.
- the annular chambers can deviate from the illustration in Fig. 2 also be structured in itself (for example meandering).
- the specification of a certain radial temperature profile the polishing plate by providing areas with a certain temperature can also be considered other than described above can be achieved, for example by the integration of heating and cooling elements in the polishing plate. These can be done inductively or through a likewise in the polishing plate housed power supply are operated.
- FIGS. 3a, 3b and 4a, 4b show schematically like the geometry of semiconductor wafers through the application the invention can be influenced.
- the figures reflect that Result of exemplary embodiments.
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- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
Gegenstand der Erfindung ist ein Verfahren zum Polieren von Halbleiterscheiben, bei dem mindestens eine Seite mindestens einer Halbleiterscheibe gegen einen mit einem Poliertuch bespannten Polierteller gedrückt und poliert wird, wobei die Halbleiterscheibe und der Polierteller eine Relativbewegung ausführen. Die Erfindung betrifft auch eine Vorrichtung, die zur Durchführung des Verfahrens geeignet ist.The invention relates to a method for polishing Semiconductor wafers with at least one side at least a semiconductor wafer against one covered with a polishing cloth Polishing plate is pressed and polished, the Semiconductor wafer and the polishing plate a relative movement To run. The invention also relates to a device which is suitable for performing the method.
Die Planarisierung einer Halbleiterscheibe mittels eines chemo-mechanischen Polierverfahrens bildet einen wichtigen Bearbeitungsschritt im Prozeßablauf zur Herstellung einer ebenen, defektfreien und glatten Halbleiterscheibe. Dieser Polierschritt stellt in vielen Fertigungsabläufen den letzten formgebenden und somit die Oberflächeneigenschaften maßgeblich bestimmenden Schritt vor der Weiterverwendung der Halbleiterscheibe als Ausgangsmaterial für die Herstellung elektrischer, elektronischer und mikroelektronischer Bauteile dar. Ziele des Polierverfahrens sind insbesondere das Erreichen einer hohen Ebenheit und Parallelität der beiden Scheibenseiten, der Abtrag durch Vorbehandlungen geschädigter Oberflächenschichten ("damage removal") und die Reduktion der Mikrorauhigkeit der Halbleiterscheibe.The planarization of a semiconductor wafer using a chemo-mechanical Polishing is an important processing step in the process flow for the production of a flat, defect-free and smooth semiconductor wafer. This polishing step provides the final form in many production processes and thus decisively determining the surface properties Step before reusing the semiconductor wafer as raw material for the production of electrical, electronic and microelectronic components. Objectives of Polishing processes are particularly high Flatness and parallelism of the two disc sides, the removal pretreatment of damaged surface layers ("damage removal") and the reduction of the microroughness of the Semiconductor wafer.
Üblicherweise werden Einseiten- und Doppelseiten-Polierverfahren eingesetzt. Bei der Einseitenpolitur einer Gruppe von mehreren Halbleiterscheiben ("single side batch polishing") werden die Halbleiterscheiben mit einer Seite auf die Vorderseite einer Trägerplatte montiert, indem zwischen der Seite und der Trägerplatte eine form- und kraftschlüssige Verbindung, beispielsweise durch Adhäsion, Kleben, Kitten oder Vakuumanwendung, hergestellt wird. In der Regel werden die Halbleiterscheiben so auf die Trägerplatte montiert, daß sie ein Muster von konzentrischen Ringen ausbilden. Nach der Montage werden die freien Scheibenseiten unter Zuführung eines Poliermittels gegen einen Polierteller, über den ein Poliertuch gespannt ist, mit einer bestimmten Polierkraft gedrückt und poliert. Die Trägerplatte und der Polierteller werden dabei üblicherweise mit unterschiedlicher Geschwindigkeit gedreht. Die notwendige Polierkraft wird von einem Druckstempel, der nachfolgend Poliertopf ("polishing head") genannt wird, auf die Rückseite der Trägerplatte übertragen. Eine Vielzahl der verwendeten Poliermaschinen sind so konstruiert, daß sie über mehrere Poliertöpfe verfügen und dementsprechend mehrere Trägerplatten aufnehmen können.Commonly used are single-sided and double-sided polishing processes used. When polishing a group of several semiconductor wafers ("single side batch polishing") the semiconductor wafers with one side on the front a carrier plate mounted by between the side and the carrier plate has a positive and non-positive connection, for example by adhesion, gluing, kitten or vacuum application, will be produced. As a rule, the semiconductor wafers mounted on the carrier plate so that it is a Form a pattern of concentric rings. After assembly the free sides of the disc are fed with a polishing agent against a polishing plate over which a polishing cloth is stretched is pressed with a certain polishing force and polished. The carrier plate and the polishing plate are thereby usually rotated at different speeds. The necessary polishing force is provided by a pressure stamp hereinafter referred to as "polishing head" transfer the back of the carrier plate. A variety of used polishing machines are designed so that they over have several polishing pots and accordingly several carrier plates be able to record.
Bei der Doppelseitenpolitur ("double side polishing", DSP) werden Vorderseite und Rückseite gleichzeitig poliert, indem mehrere Halbleiterscheiben zwischen zwei mit Poliertüchern bespannten, oberen und unteren Poliertellern geführt werden. Dabei liegen die Halbleiterscheiben in dünnen Führungskäfigen ("wafer carrier"), die als Läuferscheiben bezeichnet werden und in ähnlicher Form auch beim Läppen von Halbleiterscheiben verwendet werden. Doppelseiten-Polierverfahren und -Vorrichtungen sind stets für die Behandlung von Gruppen von Halbleiterscheiben ausgelegt ("batch polishing").With double side polishing (DSP) the front and back are polished simultaneously by several semiconductor wafers between two covered with polishing cloths, upper and lower polishing plates. Here the semiconductor wafers lie in thin guide cages ("wafer carrier"), which are referred to as rotor disks and in a similar form when lapping semiconductor wafers be used. Double-sided polishing processes and devices are always for the treatment of groups of semiconductor wafers designed ("batch polishing").
Mehrere Faktoren machen es schwierig, die angestrebte Ebenheit und Parallelität der Halbleiterscheiben, nachfolgend angestrebte Geometrie genannt, zu erreichen. Polierte Halbleiterscheiben weisen oftmals Seiten auf, die nicht parallel zueinander liegen, sondern im Querschnitt die Form eines Keils einnehmen.Several factors make it difficult to achieve the desired flatness and parallelism of the semiconductor wafers, subsequently sought Called geometry. Polished semiconductor wafers often have pages that are not parallel to each other but in cross-section the shape of a wedge take in.
Die Form des Keils läßt sich mit dem Begriff lineare Dickenvariation beschreiben. Die lineare Dickenvariation ist der größte gemessene Dickenunterschied zwischen zwei Meßstellen, die auf gleichem Durchmesser symmetrisch zum Mittelpunkt der Halbleiterscheibe liegen. Üblicherweise liegen die Meßstellen symmetrisch auf einem Kreis, der einen Abstand von beispielsweise 6 mm vom Scheibenrand der Halbleiterscheibe hat. Ist der Rand der Halbleiterscheibe, der zum Trägerplattenrand zeigt, dicker (dünner), als der Scheibenrand, der zur Trägerplattenmitte zeigt, spricht man von einer positiven (negativen) linearen Keiligkeit. The shape of the wedge can be described with the term linear thickness variation describe. The linear thickness variation is the largest measured difference in thickness between two measuring points, the on the same diameter symmetrical to the center of the semiconductor wafer lie. The measuring points are usually symmetrical on a circle that is a distance of, for example 6 mm from the edge of the wafer of the semiconductor wafer. Is the edge the semiconductor wafer, which faces the edge of the carrier plate, thicker (thinner) than the edge of the pane, towards the center of the carrier plate shows, one speaks of a positive (negative) linear Wedging.
Ein anderes Maß für die Keiligkeit von Halbleiterscheiben ist der sogenannte TTV-Wert (TTV = total thickness variation). Dieser Wert gibt die Differenz zwischen der dicksten und der dünnsten Stelle auf der Halbleiterscheibe an.Another measure of the wedge shape of semiconductor wafers is the so-called TTV value (TTV = total thickness variation). This value gives the difference between the thickest and the thinnest point on the semiconductor wafer.
Eine durch die Politur verursachte Keiligkeit einer Halbleiterscheibe ist letztlich das Resultat eines ungleichmäßigen Materialabtrags. Sie kann entstehen, wenn die Trägerplatte während der Politur durch ihr Eigengewicht radial deformiert wird oder eine bestimmte, herstellungsbedingte radiale Keiligkeit hat. Manchmal ist auch eine sich einstellende Abnutzung des Poliertuchs Ursache dafür, daß sich die Scheibengeometrie im Verlauf mehrerer Polierfahren verschlechtert. Eine gewisse Grundkeiligkeit resultiert selbst bei Verwendung ideal ebener Trägerplattten wegen der kinematischen Verhältnisse bei der Einzelscheibenpolitur, die einen inhomogenen Materialabtrag fördern.A wedge of a semiconductor wafer caused by the polish is ultimately the result of an uneven Material removal. It can arise if the carrier plate radially deformed during polishing by its own weight or a certain radial wedge, due to the manufacturing process Has. Sometimes there is also wear and tear of the polishing cloth cause that the disc geometry deteriorated in the course of several polishing runs. A certain one Basic wedge results even when used ideally level Carrier plates because of the kinematic conditions in the Single disc polishing, which is an inhomogeneous material removal promote.
In der EP-4033 A1 wird vorgeschlagen, Zwischenlagen aus weichen elastischen Körpern zwischen den Poliertopf und der Rückseite der Trägerplatte einzulegen, wodurch die Trägerplatte absichtlich ein wenig radialsymmetrisch gewölbt wird. Damit kann zu einem gewissen Maß verhindert werden, daß die Halbleiterscheiben keilig poliert werden. Dieses Verfahren ist jedoch nicht automatisierbar und fehleranfällig, da sein Erfolg größtenteils von der Erfahrung und der Umsicht des Bedienungspersonals abhängt, das die Zwischenlagen an Hand deren Breite auswählen und einlegen muß. Aber auch wenn dabei keine Fehler gemacht werden, bleibt die Keiligkeit der polierten Halbleiterscheiben über einem bestimmten Grenzwert.EP-4033 A1 proposes intermediate layers made of soft elastic bodies between the polishing pot and the back insert the carrier plate, thereby the carrier plate is deliberately curved a little radially symmetrically. In order to can be prevented to a certain extent from the semiconductor wafers be wedge-polished. However, this procedure is cannot be automated and prone to errors, since its success is largely from the experience and care of the operators depends on the width of the liners must select and insert. But even if there are no mistakes made, the wedge of the polished semiconductor wafers remains above a certain limit.
Die vorliegende Erfindung löst die Aufgabe, bei der Politur von Halbleiterscheiben eine verbesserte Vergleichmäßigung des Polierabtrages zu erreichen, so daß insbesondere die Keiligkeit der polierten Halbleiterscheiben gering ist. The present invention solves the problem in polishing of semiconductor wafers an improved uniformity of the To achieve polishing removal, so that in particular the wedge the polished semiconductor wafers is low.
Gegenstand der Erfindung ist ein Verfahren zum Polieren von Halbleiterscheiben, bei dem mindestens eine Seite mindestens einer Halbleiterscheibe gegen einen mit einem Poliertuch bespannten Polierteller gedrückt und poliert wird, wobei die Halbleiterscheibe und der Polierteller eine Relativbewegung ausführen, dadurch gekennzeichnet, daß die Halbleiterscheibe während des Polierens mindestens zwei Bereiche auf dem Polierteller überstreicht, die bestimmte radiale Breiten aufweisen und unterschiedliche Temperaturen haben, und Temperiermittel im Polierteller vorgesehen sind, mit deren Hilfe die Anzahl, die radialen Breiten und die Temperaturen der Bereiche vor dem Polieren der Halbleiterscheiben festgelegt werden.The invention relates to a method for polishing Semiconductor wafers with at least one side at least a semiconductor wafer against one covered with a polishing cloth Polishing plate is pressed and polished, the Semiconductor wafer and the polishing plate a relative movement execute, characterized in that the semiconductor wafer at least two areas on the polishing plate during polishing sweeps that have certain radial widths and have different temperatures, and tempering agents are provided in the polishing plate, with the aid of which the number, the radial latitudes and the temperatures of the areas before Polishing the semiconductor wafers can be determined.
Gegenstand der Erfindung ist ferner eine Vorrichtung zur Durchführung des Verfahrens, die gekennzeichnet ist durch ein im Polierteller untergebrachtes Kammersystem aus konzentrisch angeordenten Ringkammern, durch die ein Temperiermedium strömt, das in jeder Ringkammer eine bestimmte, einstellbare Temperatur aufweist.The invention further relates to a device for Implementation of the procedure, which is characterized by a Chamber system made of concentric in the polishing plate arranged annular chambers through which a tempering medium flows that a certain, adjustable in each annular chamber Temperature.
Untersuchungen der Erfinder zufolge stellt sich beim Polieren ein radial konvexes Temperaturprofil auf dem Polierteller ein, das für die Keiligkeit polierter Halbleiterscheiben mitverantwortlich ist. Das Temperaturprofil verursacht einen inhomogenen Materialabtrag, der durch den Einsatz der oben genannten elastischen Zwischenlagen nicht (beispielsweise bei Verwendung keramischer Trägerplatten, die praktisch nicht gewölbt werden können) oder nicht ausreichend (bei Verwendung von Trägerplatten aus weniger steifem Material) kompensiert werden kann. Durch die vorliegende Erfindung ist eine solche Kompensation möglich, weil durch die Schaffung von temperierten Bereichen ein radiales Temperaturprofil des Poliertellers vorgegeben wird, das den Materialabtrag entscheidend mitbestimmt. Die Erfindung erlaubt, durch Polieren die Keiligkeit von Halbleiterscheiben in vergleichsweise weiten Grenzen einzustellen. Durch die Erfindung können Halbleiterscheiben hergestellt werden, die gezielt positiv oder negativ keilig sind. In erster Linie wird die Erfindung jedoch genutzt, um kinematische Einflüsse und Einflüsse der Trägerplatte oder des Poliertuchs, die zu Keiligkeiten führen würden, zu kompensieren und beispielsweise eine Verlängerung der Nutzungsdauer des Poliertuches zu erreichen.Investigations by the inventors have shown that polishing occurs a radially convex temperature profile on the polishing plate, this is partly responsible for the wedge shape of polished semiconductor wafers is. The temperature profile causes an inhomogeneous Material removal through the use of the above elastic intermediate layers (e.g. when using ceramic carrier plates that are practically not arched may) or not sufficient (when using carrier plates less rigid material) can be compensated. Such compensation is provided by the present invention possible because of the creation of tempered areas specified a radial temperature profile of the polishing plate that decisively determines the material removal. The invention allowed to polish the wedge shape of semiconductor wafers set within comparatively wide limits. By the invention can produce semiconductor wafers, which are specifically positive or negative wedge. Primarily However, the invention is used for kinematic influences and influences of the carrier plate or the polishing cloth, which too Wedges would lead to compensate and for example an extension of the service life of the polishing cloth to reach.
Die Erfindung kann sowohl bei der Einseitenpolitur (Ein- und Mehrscheibenpolitur), als auch bei der Doppelseitenpolitur angewendet werden. Die Erfindung wird nachstehend am Beispiel der Mehrscheiben-Einseitenpolitur (single-side-batch-polishing) näher erläutert.The invention can be used both for one-sided polishing (one and Multi-disc polish), as well as for double-sided polish become. The invention is illustrated below using the example multi-disc single-side polishing (single-side batch polishing) explained in more detail.
Gemäß der Erfindung wird sichergestellt, daß die Halbleiterscheiben während des Polierens mindestens zwei Bereiche auf dem Polierteller überstreichen, die durch Temperiermittel im Polierteller auf bestimmten Temperaturen gehalten werden. Die Bereiche sind vorzugsweise in konzentrischen Ringen angelegt, wobei sich die Temperaturen von mindestens zwei der Bereiche unterscheiden. Die Anzahl, die radialen Breiten und die Temperaturen der Bereiche werden vor einer Polierfahrt festgelegt. Nicht ausgeschlossen ist, die Temperaturen, auf denen die Bereiche gehalten werden, während einer Polierfahrt zu verändern.According to the invention it is ensured that the semiconductor wafers at least two areas during polishing paint over the polishing plate, which is caused by temperature control in the Polishing pads are kept at certain temperatures. The Areas are preferably laid out in concentric rings, taking temperatures from at least two of the ranges differentiate. The number, the radial latitudes and the temperatures the areas are determined before a polishing run. Not excluded is the temperature at which the areas be held during a polishing run change.
Aufgrund von Einflüssen der Polierkinematik, der Verwendung nicht vollkommen ebener Trägerplatten und einer inhomogenen Abnutzung des Poliertuches herrscht während des Polierens von Halbleiterscheiben auf einem üblichen Polierteller keine homogene Temperatur vor. Die Temperatur nimmt häufig vom Rand bis r/2 des Poliertellers zu (r ist der Radius des Poliertellers) und fällt zum Zentrum des Poliertellers ab, so daß ein radial konvexes Temperaturprofil resultiert. Durch die Einrichtung von Bereichen auf dem Polierteller, die von im Polierteller untergebrachten Temperiermitteln auf bestimmten Temperaturen gehalten werden können, kann eine Homogenisierung des Temperaturprofils erreicht werden. Zur Vermeidung der Ausbildung eines radial konvexen Temperaturprofils sollten mindestens zwei temperierte Bereiche auf dem Polierteller eingerichtet werden. Geeignet sind beispielsweise drei Bereiche in der Form konzentrischer Ringe, wobei der äußere und der innere auf einer höheren Temperatur gehalten werden als der mittlere Bereich. Dadurch wird Wärme, die im Zentrumsbereich des Poliertellers während des Polierens von Halbleiterscheiben entsteht, über das Temperiermittel abgeführt. Der äußere und innere Ring und somit die randnahen Teile des Poliertellers erhalten hingegen zusätzlich Wärmeenergie, so daß insgesamt ein flacheres radiales Temperaturprofil resultiert. Grundsätzlich kann durch die Erfindung jedes beliebige, sich beim Polieren einstellende, radiale Temperaturprofil vergleichmäßigt werden.Due to influences of the polishing kinematics, the use not completely flat carrier plates and an inhomogeneous one The polishing cloth wears during polishing Semiconductor wafers on a conventional polishing plate are not homogeneous Temperature before. The temperature often increases from the edge r / 2 of the polishing plate (r is the radius of the polishing plate) and drops to the center of the polishing plate, making a radial convex temperature profile results. By the establishment from areas on the polishing plate, from areas in the polishing plate housed temperature control agents at certain temperatures can be maintained, a homogenization of the temperature profile can be achieved. To avoid training a radially convex temperature profile should be at least two tempered areas can be set up on the polishing plate. For example, three areas in the shape are suitable concentric rings, the outer and the inner on one higher temperature than the middle range. This creates heat in the center area of the polishing plate arises during the polishing of semiconductor wafers, dissipated via the temperature control. The outer and inner ring and thus preserve the parts of the polishing plate near the edge additional thermal energy, so that overall a flatter radial temperature profile results. Basically, by the invention of any polishing process radial temperature profile are made uniform.
Die Anzahl der Bereiche, ihre radiale Breite und die Temperaturen, auf denen sie gehalten werden, werden vor dem Polieren der Halbleiterscheiben festgelegt. Als Grundlage für die Festlegung können Daten von einer Analyse der Geometrie zuvor polierter Halbleiterscheiben verwendet werden, beispielsweise die bei diesen Halbleiterscheiben ermittelte lineare Dickenvariation. Grundlage können auch Meßdaten des radialen Temperaturprofils des Poliertellers sein, die während einer vorangegangenen Polierfahrt ermittelt wurden.The number of areas, their radial latitude and the temperatures, on which they are held are before polishing of the semiconductor wafers. As the basis for the determination can data from an analysis of the geometry previously polished Semiconductor wafers are used, for example the linear thickness variation determined for these semiconductor wafers. Measurement data of the radial temperature profile can also form the basis of the polishing plate during a previous one Polishing run were determined.
Der Funktionszusammenhang zwischen der nach einer Politur zu erwartenden Geometrie der Halbleiterscheiben und der festzulegenden Anzahl, Breite und Temperaturen der Bereiche auf dem Polierteller wird zweckmäßigerweise durch Routineexperimete ermittelt. Bei solchen Experimenten werden die Anzahl, radiale Breite und Temperaturen der Bereiche systematisch verändert und die Auswirkungen auf die Geometrie der polierten Halbleiterscheiben untersucht.The functional relationship between that after a polish too expected geometry of the semiconductor wafers and the one to be determined Number, width and temperatures of the areas on the The polishing plate is expediently carried out by routine experimentation determined. In such experiments, the number is radial Systematic changes in width and temperature of the areas and the effects on the geometry of the polished semiconductor wafers examined.
Nach Abschluß solcher Experimente kann das Polierverfahren auf einfache Weise automatisiert werden. Ein Leitrechner erhält als Eingangsdaten das radiale Temperaturprofil, das während einer vorangegangenen Polierfahrt ermittelt wurde oder Daten zur Geometrie (beispielsweise zur Keiligkeit) von Halbleiterscheiben, die bei einer vorhergehenden Polierfahrt poliert wurden und legt auf der Grundlage des empirisch gefundenen Zusammenhangs die zum Erreichen einer gewünschten Scheibengeometrie notwendigen Parameter (Anzahl, radiale Breite und Temperatur der Bereiche) fest.After completing such experiments, the polishing process can be started be automated easily. A host computer receives as input data the radial temperature profile, which during a previous polishing run or data on the geometry (for example on the wedge shape) of semiconductor wafers, which polished on a previous polishing run were and is based on the empirically found connection those to achieve a desired one Disc geometry necessary parameters (number, radial width and temperature of the areas).
Die Erfindung wird nachfolgend anhand von Figuren näher beschrieben. In Figur 1 ist eine bevorzugte Ausführungsform der beanspruchten Vorrichtung schematisch dargestellt. Die Figur zeigt einen Vertikalschnitt durch die Vorrichtung in Seitenansicht. In Figur 2 ist ein Horizontalschnitt durch den Polierteller der Vorrichtung in Draufsicht dargestellt. In den Figuren 3a, 3b und 4a, 4b ist schematisch dargestellt, wie die Geometrie von Halbleiterscheiben durch die Anwendung der Erfindung beeinflußt werden kann. Nachfolgend wird nur auf Merkmale hingewiesen, die zur Verdeutlichung der Erfindung notwendig sind. In den Figuren wird auf gleichartige Merkmale mit denselben Bezugszeichen hingewiesen.The invention is described in more detail below with reference to figures. In Figure 1 is a preferred embodiment of the claimed device shown schematically. The figure shows a vertical section through the device in side view. In Figure 2 is a horizontal section through the polishing plate the device shown in plan view. In the figures 3a, 3b and 4a, 4b is shown schematically as the Geometry of semiconductor wafers through the application of the invention can be influenced. Below is only on characteristics pointed out that necessary to illustrate the invention are. Similar features are used in the figures pointed out the same reference numerals.
Zunächst wird auf die Figur 1 Bezug genommen. Bei der gezeigten
Ausführungsform handelt es sich um eine Einseitenpoliermaschine
mit mehreren Poliertöpfen, von denen einer zu sehen
ist. Der Poliertopf 1 drückt eine Trägerplatte 2 mit einer Polierkraft
K gegen einen mit einem Poliertuch 3 bespannten Polierteller
4. Die Trägerplatte wird beispielsweise über Vakuumansaugung
am Poliertopf gehalten. Die Halbleiterscheiben 5
sind auf der zum Poliertuch 3 weisenden Vorderseite der Trägerplatte
2 fixiert. Während des Polierens rotiert sowohl die
Trägerplatte als auch der Polierteller mit einer bestimmten
Geschwindigkeit und Drehrichtung. Wesentliches Merkmal der
Vorrichtung sind im Polierteller in konzentrisch angelegten
Bahnen laufende Ringkammern, durch die ein Temperiermedium
strömt. Im dargestellten Polierteller sind fünf Ringkammern Z1
bis Z5 vorgesehen. Jede Ringkammer wird unabhängig von einer
anderen von einem Temperiermedium, beispielsweise Wasser,
durchströmt, wobei das Temperiermedium in jeder Ringkammer eine
bestimmte Temperatur hat und die Temperaturen unterschiedlich
sein können. Das Temperiermedium wird durch Vorlaufleitungen
VZ1 bis VZ5 in die jeweiligen Ringkammern gepumpt und
verläßt diese wieder durch Rücklaufleitungen RZ1 bis RZ5. Die
Vor- und Rücklaufleitungen laufen durch eine Drehdurchführung
6, die an der Unterseite des Poliertellers 4 befestigt ist.
Der Übersichtlichkeit wegen sind die Vorlauf- und Rücklaufleitungen
unterbrochen dargestellt. Das Temperiermedium wird von
einer Thermostatisier-Einrichtung 7 auf einer gewünschten Temperatur
gehalten. Die Thermostatisier-Einrichtung wird von einem
Leitrechner 8 gesteuert, der die Soll-Temperaturen SZ1 bis
SZ5 für das Temperiermedium in den Ringkammern Z1 bis Z5 vorgibt.
Der Leitrechner greift wiederum auf einen Datenspeicher
9 zurück, in dem Meßdaten vorangegangener Polierfahrten abgelegt
sind und berechnet daraus automatisch die
Soll-Temperaturen.First, reference is made to FIG. 1. In the shown
Embodiment is a single side polishing machine
with several polishing pots, one of which can be seen
is. The polishing
Das Temperiermedium hält in jeder Ringkammer eine bestimmte Temperatur aufrecht, so daß auf dem Polierteller radialsymmetrische Bereiche mit charakteristischer Temperatur entstehen, die die Halbleiterscheiben beim Polieren überstreichen. Die Anzahl der verfügbaren Bereiche richtet sich nach der Anzahl der bereitgestellten Ringkammern. Die radialen Breiten der Bereiche sind von den gewählten radialen Breiten der Ringkammern und von der Temperatur des Temperiermediums abhängig, das durch die Ringkammern strömt.The temperature control medium holds a certain one in each annular chamber Temperature upright, so that on the polishing plate radially symmetrical Areas with a characteristic temperature arise that sweep over the semiconductor wafers during polishing. The The number of available areas depends on the number of the provided ring chambers. The radial widths of the areas are of the chosen radial widths of the annular chambers and depending on the temperature of the temperature control medium flows through the annular chambers.
In Figur 2 ist ein Horizontalschnitt durch den Polierteller der Vorrichtung gemäß Fig.1 in Draufsicht dargestellt. Wenn sich die Temperatur des Temperiermediums in jeder Ringkammer Z1 bis Z5 von den Temperaturen des Temperiermediums in den übrigen Ringkammern unterscheidet, erzeugen die Ringkammern auf dem Polierteller eine der Zahl der Ringkammern entsprechende Anzahl ringfömiger Bereiche. Diese Bereiche werden auf einer Temperatur gehalten, die im wesentlichen der Temperatur des Temperiermediums in der zugehörigen Ringkammer entspricht. Die Anzahl der Bereiche ist entsprechend geringer, wenn die Temperatur des Temperiermediums in zwei oder mehreren benachbarten Ringkammern gleich ist. Ist die Temperatur des Temperiermediums in zwei benachbarten Ringkammern gleich, resultiert daraus ein Bereich auf dem Polierteller, dessen radiale Breite näherungsweise der Summe der radialen Breiten dieser Ringkammern entspricht. Vorzugsweise werden 2 bis 5 Ringkammern bereitgestellt. Die radialen Breiten der Ringkammern betragen bevorzugt 25 bis 120 % des Durchmessers der zu polierenden Halbleiterscheiben.In Figure 2 is a horizontal section through the polishing plate the device shown in Figure 1 in plan view. If the temperature of the temperature control medium in each ring chamber Z1 to Z5 of the temperatures of the tempering medium in the rest Differentiates annular chambers, produce the annular chambers the polishing plate corresponds to the number of annular chambers Number of annular areas. These areas are on a Temperature maintained, which is essentially the temperature of the Temperature control medium in the associated ring chamber corresponds. The Number of areas is correspondingly lower when the temperature of the temperature control medium in two or more neighboring ones Annular chambers is the same. Is the temperature of the temperature control medium the same in two adjacent ring chambers, results from this an area on the polishing plate whose radial width is approximately the sum of the radial widths of these annular chambers corresponds. 2 to 5 annular chambers are preferred provided. The radial widths of the annular chambers are preferably 25 to 120% of the diameter of the to be polished Semiconductor wafers.
Die Ringkammern können abweichend von der Darstellung in Fig.2 auch in sich strukturiert sein (beispielsweise mäanderförmig). Die Vorgabe eines bestimmten radialen Temperaturprofils auf dem Polierteller durch die Bereitstellung von Bereichen mit einer bestimmten Temperatur kann auch auf andere Weise, als vorstehend beschrieben, erreicht werden, beispielsweise durch die Integration von Heiz- und Kühlelementen im Polierteller. Diese können induktiv oder durch eine ebenfalls im Polierteller untergebrachte Stromversorgung betrieben werden.The annular chambers can deviate from the illustration in Fig. 2 also be structured in itself (for example meandering). The specification of a certain radial temperature profile the polishing plate by providing areas with a certain temperature can also be considered other than described above can be achieved, for example by the integration of heating and cooling elements in the polishing plate. These can be done inductively or through a likewise in the polishing plate housed power supply are operated.
In den Figuren 3a, 3b und 4a, 4b ist schematisch dargestellt, wie die Geometrie von Halbleiterscheiben durch die Anwendung der Erfindung beeinflußt werden kann. Die Figuren spiegeln das Ergebnis von Ausführungsbeispielen wider.FIGS. 3a, 3b and 4a, 4b show schematically like the geometry of semiconductor wafers through the application the invention can be influenced. The figures reflect that Result of exemplary embodiments.
Nach einer Polierfahrt in einer Vorrichtung gemäß Fig.1 wurden Halbleiterscheiben mit positiver Keiligkeit erhalten. Während der Polierfahrt strömte durch die Ringkammern Temperiermedium, das in den Ringkammern Z1 bis Z5 folgendermaßen temperiert war: Z1=30°C, Z2=30°C, Z3=40°C, Z4=30°C und Z5=30°C (Fig. 3a). Durch eine Änderung der Temperaturen in den Ringkammern (Z1=40°C, Z2=40°C, Z3=30°C, Z4=40°C und Z5=40°C) konnten nach einer folgenden Polierfahrt Halbleiterscheiben mit nahezu planparallelen Seiten erhalten werden (Fig. 3b).After a polishing run in a device according to FIG Preserved semiconductor wafers with positive taper. While during the polishing run, tempering medium flowed through the ring chambers, which is tempered in the annular chambers Z1 to Z5 as follows was: Z1 = 30 ° C, Z2 = 30 ° C, Z3 = 40 ° C, Z4 = 30 ° C and Z5 = 30 ° C (Fig. 3a). By changing the temperatures in the annular chambers (Z1 = 40 ° C, Z2 = 40 ° C, Z3 = 30 ° C, Z4 = 40 ° C and Z5 = 40 ° C) were able to a subsequent polishing run with nearly semiconductor wafers plane-parallel sides can be obtained (Fig. 3b).
Nach einer Polierfahrt in einer Vorrichtung gemäß Fig.1 wurden Halbleiterscheiben mit negativer Keiligkeit erhalten. Während der Polierfahrt strömte durch die Ringkammern Temperiermedium, das in den Ringkammern Z1 bis Z5 folgendermaßen temperiert war: Z1=30°C, Z2=30°C, Z3=40°C, Z4=30°C und Z5=30°C (Fig. 4a). Durch eine Änderung der Temperaturen in den Ringkammern (Z1=20°C, Z2=20°C, Z3=50°C, Z4=20°C und Z5=20°C) konnten nach einer folgenden Polierfahrt widerum Halbleiterscheiben mit nahezu planparallelen Seiten erhalten werden (Fig. 4b).After a polishing run in a device according to FIG Preserved semiconductor wafers with negative wedge. While during the polishing run, tempering medium flowed through the ring chambers, which is tempered in the annular chambers Z1 to Z5 as follows was: Z1 = 30 ° C, Z2 = 30 ° C, Z3 = 40 ° C, Z4 = 30 ° C and Z5 = 30 ° C (Fig. 4a). By changing the temperatures in the annular chambers (Z1 = 20 ° C, Z2 = 20 ° C, Z3 = 50 ° C, Z4 = 20 ° C and Z5 = 20 ° C) were able to a subsequent polishing run around semiconductor wafers with almost plane-parallel sides can be obtained (Fig. 4b).
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19748020A DE19748020A1 (en) | 1997-10-30 | 1997-10-30 | Method and device for polishing semiconductor wafers |
DE19748020 | 1997-10-30 |
Publications (2)
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EP0916450A1 true EP0916450A1 (en) | 1999-05-19 |
EP0916450B1 EP0916450B1 (en) | 2002-01-09 |
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EP98119004A Expired - Lifetime EP0916450B1 (en) | 1997-10-30 | 1998-10-08 | Method and apparatus for polishing semiconductor wafers |
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US (1) | US6095898A (en) |
EP (1) | EP0916450B1 (en) |
JP (1) | JPH11207605A (en) |
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DE (2) | DE19748020A1 (en) |
MY (1) | MY133888A (en) |
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TW (1) | TW407311B (en) |
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-
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- 1997-10-30 DE DE19748020A patent/DE19748020A1/en not_active Withdrawn
-
1998
- 1998-09-15 SG SG1998003674A patent/SG75876A1/en unknown
- 1998-10-08 DE DE59802824T patent/DE59802824D1/en not_active Expired - Lifetime
- 1998-10-08 EP EP98119004A patent/EP0916450B1/en not_active Expired - Lifetime
- 1998-10-09 MY MYPI98004632A patent/MY133888A/en unknown
- 1998-10-22 KR KR1019980044284A patent/KR100315162B1/en not_active IP Right Cessation
- 1998-10-28 US US09/181,428 patent/US6095898A/en not_active Expired - Lifetime
- 1998-10-28 TW TW087117834A patent/TW407311B/en not_active IP Right Cessation
- 1998-10-28 JP JP30728298A patent/JPH11207605A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4471579A (en) * | 1981-07-22 | 1984-09-18 | Peter Wolters | Lapping or polishing machine |
JPS60201868A (en) * | 1984-03-23 | 1985-10-12 | Hitachi Ltd | Polishing of wafer |
EP0562718A1 (en) * | 1992-02-28 | 1993-09-29 | Shin-Etsu Handotai Company Limited | Polishing machine and method of dissipating heat therefrom |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 010, no. 051 (M - 457) 28 February 1986 (1986-02-28) * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10009656B4 (en) * | 2000-02-24 | 2005-12-08 | Siltronic Ag | Method for producing a semiconductor wafer |
DE10012840C2 (en) * | 2000-03-16 | 2001-08-02 | Wacker Siltronic Halbleitermat | Process for the production of a large number of polished semiconductor wafers |
DE102004017452A1 (en) * | 2004-04-08 | 2005-11-03 | Siltronic Ag | Laminar and abrasive machining device for e.g. crystalline silicon wafer, has supporting device with surface bearing and bearing supports supporting rear side of work disk which is pressed against carrier`s front with work piece |
Also Published As
Publication number | Publication date |
---|---|
JPH11207605A (en) | 1999-08-03 |
SG75876A1 (en) | 2000-10-24 |
KR19990037292A (en) | 1999-05-25 |
DE19748020A1 (en) | 1999-05-06 |
DE59802824D1 (en) | 2002-02-28 |
US6095898A (en) | 2000-08-01 |
MY133888A (en) | 2007-11-30 |
KR100315162B1 (en) | 2002-06-20 |
EP0916450B1 (en) | 2002-01-09 |
TW407311B (en) | 2000-10-01 |
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