EP0910906A1

EP0910906A1 - Digital signal processing system for transmission of digital fdm signals

Info

Publication number: EP0910906A1
Application number: EP97932740A
Authority: EP
Inventors: Heinz Goeckler; Karlheinz Grotz
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 1996-07-10
Filing date: 1997-07-04
Publication date: 1999-04-28
Also published as: DE19627786A1; WO1998001969A1

Abstract

The invention concerns a digital signal processing system for transmission of digital FDM signals with at least two FDM circuits (3, 5) to each of which of plurality of channels is directed and each of which produces an FDM signal which comprises a sub-band. It is characterised by a transmission interface circuit (7) which is connected after the FDM circuits (3, 5) and which combines the FDM output signals from the FDM circuits into a single FDM signal for transmission.

Description

DIGITAL SIGNAL PROCESSING DEVICE FOR TRANSMITTING A DIGITAL FDM SIGNAL

State of the art

The invention relates to a digital signal processing device for transmitting a frequency multiplex signal (FDM signal), with two DFM circuits (digital frequency multiplexers), each of which is supplied with a plurality of channels, in particular television and radio channels, and each one Generate subband comprehensive FDM signal.

From the article "DIAMANT, All Digital Frequency Division Multiplexing for 10 Gbit / ε Fiber-Optic CATV Distribution System", GÖCKLER and GROTZ, SIGNAL PROCESSING VII, 1994, a transmission system is known with which up to 64 TV channels via a single Fiber optic line can be transmitted. For this purpose, the individual channels with a usual Bandwidth of 7 MHz combined by means of a DFM circuit (hereinafter referred to as DFM) to form a single FDM signal with a bandwidth of 448 MHz. The signal is then fed into an optical fiber line and converted into corresponding analog signals on the receiver side.

With a bandwidth of 448 MHz, the digital / analog converter must operate according to the sampling theorem with a sampling frequency of 2 x 448 MHz = 896 MHz. According to the current state of the art, this is not yet possible with the required quality.

For this reason, DFMs are currently being used, to which only half the number of channels, namely 32, are fed. This results in a total bandwidth of the combined signal of 224 MHz. The sampling frequency to be observed is consequently 448 MHz, which is already technologically feasible today.

To increase the number of channels to the desired 64 channels, two parallel fiber optic lines must be used with this system, each of which works with a DFM and a digital / analog converter on the receiver side.

Of course, as soon as the fast digital / analog converters are technically feasible, one would like to make better use of the existing optical fibers by then feeding a larger number of channels into the optical fibers. However, sustainable changes are to be made on the transmitter side, in particular the previous changes DFMs intended for 32 channels can be replaced by new DFMs suitable for 64 channels. However, this requires high financial expenses.

Advantages of the invention

The digital signal processing device according to the invention with the features of claim 1 has the advantage that a doubling of the transmission bandwidth is possible immediately after the availability of the fast digital / analog converter, without having to replace the very expensive DFM's on the transmitter side. Because the transmitter-side, digital signal processing device has a transmission interface circuit which combines the individual signals of the existing DFMs and feeds them into a common optical fiber, the higher transmission bandwidth can be used on the one hand, but without having to replace the DFMs on the other hand.

The DFMs are preferably suitable for the transmission of 32 individual channels with a total bandwidth of approximately 224 MHz.

In an advantageous embodiment, a signal of a DFM comprising a subband is first fed as a real-value signal to a complex half-band filter, which in turn feeds its complex-value output signal to a complex adder. As an additional input signal, the adder receives a complex signal indirectly or directly from a second complex half-band filter. If the subbands are already in the desired frequency position, the adder can immediately follow the second half-band filter. If, on the other hand, a frequency conversion of the second subband is required, then the second complex halfband filter is first followed by a complex mixer which shifts the frequency position of the output signal of the halfband filter comprising the second subband.

The second complex half-band filter is fed by another DFM. The output signal of the adder is then fed to a further complex half-band filter for doubling the sampling rate, of whose complex output signal only the real-valued signal component is passed on (real or imaginary part of the complex output signal). By using complex half-band filters with a center frequency f _m = 1/4 f or 3/4 f _{A of} the respective sampling frequency f, more than 50% of the multipliers can be saved compared to the general case with a center frequency not equal to f / 4 or 3 f / 4 .

In a further advantageous embodiment, the frequency conversion of the subband does not take place after the first complex half-band filter, but before it. With the aid of this arrangement, it can be achieved that the two complex half-band filters upstream of the adder can share the state memory, that is to say they can use the same state memories. Significant effort can be saved. A further advantageous embodiment variant provides that subordinate complex half-band filters for doubling the sampling rate are split into two corresponding half-band filters, one half-band filter in each case being assigned to a processing branch, that is to say a sub-band signal. The preprocessing of the two subband signals corresponds to the previously mentioned methods. The two real-value output signals of the two branches are then fed to a real adder and combined there.

A further embodiment variant is particularly advantageous with regard to the computing effort. This embodiment variant provides for combining the two subordinate complex half-band filters described above with sampling rate doubling to form a complex half-band filter filter. This saves a large number of multipliers in particular.

Further advantageous embodiments of the invention result from the remaining subclaims.

drawing

The invention is explained in more detail below on the basis of exemplary embodiments with reference to the drawings. Show it:

Figure 1 is a schematic representation of a digital signal processing device;

Figure 2a shows a first embodiment of a transmission interface circuit; Figure 2b is a spectral representation of the signal processing of the first embodiment;

Figure 3a shows a second embodiment of a transmission interface circuit;

FIG. 3b shows the spectral representation of the transmission interface circuit according to FIG. 3a;

Figure 4a shows a transmission interface circuit according to a third exemplary embodiment;

FIG. 4b the associated spectral representation;

FIG. 5a shows a transmission interface circuit according to a further exemplary embodiment;

FIG. 5b shows a possible implementation of the filter switch according to FIG. 5a;

FIG. 6 shows a transmission interface circuit according to a further exemplary embodiment, and

7 shows a transmission interface circuit according to a further exemplary embodiment.

FIG. 1 shows a digital signal processing device 1 with a dashed border, which has two DFM circuits 3, 5 and an FDM (Frequency Division Multiplex) interface circuit 7 has.

In the present exemplary embodiment, the DFM circuit 3 processes a number of 32 equivalent TV channels, each with a bandwidth of 7 MHz, to form an FDM signal with a bandwidth of 224 MHz, which is fed to the FDM interface circuit 7 via a line 9.

The second DFM circuit 5 also processes 32 individual channels, whereby of course not only television but also radio channels can be processed. The corresponding output signal, likewise with a bandwidth of approximately 224 MHz, is fed to a further input of the FDM interface circuit 7 via a line 11.

The FDM interface circuit 7 now processes the two input signals in such a way that a single FDM signal with 64 frequency slots of 7 MHz arises. This 64-channel FDM-PCM signal is then transmitted via a fiber optic line 13 to a receiver 15.

Before this, however, the digital FDM-PCM signal is converted by a digital / analog converter 17. With a total signal bandwidth of 448 MHz, the sampling rate required by the sampling theorem is 896 MHz. A digital / analog converter with this sampling rate is not yet feasible at the moment, but it can certainly be expected in the next few years. The channels processed by the DFM 3 are usually transmitted in the normal position, while the channels of the second sub-band are transmitted by the DFM 5 in the inverted position.

The processing of the two signals S (2kT) and s ₂ (2kT) coming from the DFM circuits 3, 5 in the FDM interface circuit 7 will now be described with reference to FIG. 2.

The first exemplary embodiment shown in FIG. 2 shows a first complex half-band filter 19 which is connected to the DFM 3 via the line 9. This half-band filter 19 thus processes the sub-band TB1.

Another complex half-band filter 21 is connected to the other DFM 5 via line 11. This half-band filter processes the sub-band TB2.

The complex-valued output signal s_η_ (2kT) of the first half-band filter 19 is fed to an adder 23, while the likewise complex-valued output signal ε_ | _ ₂ - ² ^ ^τ ) of the second half-band filter 21 initially by means of a complex mixer 25 by a frequency f of approximately -36. 42 MHz at a sampling frequency f _A = 452.42 MHz is frequency shifted.

The sum signal s (2 kT) is fed to a downstream complex half-band filter 27 which doubles the sampling rate and outputs a real-value signal s (kT). A corresponding spectral diagram is shown in FIG. 2b for clarification. This clearly shows that the first subband S _{] ^ is} transmitted in control position R with a frequency range from 47 to 216 MHz. To filter out this frequency range, the complex half-band filter 19 has a center frequency f of 1/4 f and blocks from a frequency of 236 MHz.

Correspondingly, the frequency range from 252 MHz to 434 MHz of the second subband S ' ₂ is filtered out by the complex half-band filter 21 and shifted downward by a frequency Δf. The complex half-band filter 21 itself has a center frequency f ₂ = 3/4 f _A and a blocking frequency of 470.42 MHz.

The composite signal spectrum S supplied by the adder 23 is then shown below, the downstream complex half-band filter 27 filtering out the lower spectral range from 47 MHz to 398 MHz.

The lower diagram then shows the real-value signal spectrum S present at the output of the FDM interface circuit, which is a mirror image of f _A / 2.

FIG. 3a shows a second exemplary embodiment, which essentially corresponds to the aforementioned first exemplary embodiment. Therefore, a more detailed description is omitted.

The only difference between the two embodiments is that the signal s ₂ (2kT) of the second subband before the processing in the complex half-band filter 21 is shifted in frequency by the complex mixer 25 by an amount Δf = -36.42 MHz. A corresponding spectral representation is shown in FIG. 3b.

Due to the advanced position of the complex mixer 25, the two complex half-band filters 19, 21 can be arranged such that they share state memories, that is to say use the same state memory. This leads to a further saving of effort.

In addition to the key data of the half-band filter 21 shown in FIG. 3b, its center frequency is f ₂ = 3/4 f _A + Δf = 302.89 MHz.

However, this saving effect due to the shared use of the state memory is lost when the complex half-band filters 19, 21 of the first exemplary embodiment according to FIG. 2a are implemented in direct form. A corresponding possibility is disclosed in patent application DE 37 05 207, to which explicit reference is made. A description is therefore omitted.

FIG. 4a shows a further third exemplary embodiment of an FDM interface circuit 7. The preprocessing of the real-value signals S _j ^ kT) and s ₂ ( ₂ kT) is carried out in accordance with the first exemplary embodiment using two complex half-band filters 19 and 21, the complex-valued signal ε _! _ ₂ (2kT) of the second half-band filter 21 is shifted in frequency in the mixer 25 by the frequency Δf. However, the further processing of the two complex signals Signale _j _ (2kT) and and s (2kT) takes place in each case with a complex half-band filter 31 or 33, which, as it were, carry out a sampling rate doubling. Their real-value output signals (kT) and s ₂ (kT) are fed to an adder 35 and combined there to form a signal s (kT).

The corresponding spectral diagram is shown in FIG. 4b. It can be seen from this that the half-band filter 31 with a sampling frequency of f _A = 904.84 MHz has a center frequency of foi = 1/8 f _A.

In contrast, the other half- ^band filter 33 operates with a center frequency f ₀ 2 = ^3/8 ^r _A - ^{AlΞ output} signal of the adder 35, and the signal composed of S _] _ and S, shown in the lower spectral representation, is obtained.

FIG. 5a shows a fourth exemplary embodiment of an FDM interface circuit 7. Here, too, the signals s ₁ (2kT) and s ₂ (2kT) of the subbands TB1 and TB2 are processed by complex half-band filters 19 and 21, the output signal s_ ₂ - ^2kτ ) being shifted by the mixer 25 by the frequency Δf.

The two complex signals s_ι_ (2kT) and s ₂ (2kT) are then supplied to a filter switch 37 in contrast to the exemplary embodiments shown. Such a combination of two half band filters, as shown in FIG. 4a, shown as 31, 33, is possible if the two half-band filters have the same coefficients, apart from a few signs. Such an implementation enables the interface circuit to be further minimized.

FIG. 5b shows an example of a possibility for designing the filter switch 37. It is a canonical structure with a minimal number of state memories. A more detailed description should not be given here. Rather, for inclusion in the disclosure, the patent DE 36 10 195 C2 and the patent application "digital filter filter" from Robert Bosch GmbH from the same day are expressly referred to.

Another exemplary embodiment is shown in FIG. 6. This corresponds essentially to the exemplary embodiment according to FIG. 4a, but the upper processing branch relating to the subband TB1 operates purely as a real value. A real half-band filter 39 takes on the one hand the filtering of the signal S] _ and on the other hand the sampling rate doubling. The two output signals of the half-band filters 33 and 39 are combined via an adder 35 to form a common real-value signal s (kT).

In contrast to the half-band filter 19 of the third exemplary embodiment according to FIG. 4a, the real half-band filter 39 has twice the number Coefficients, which leads to a doubling of the effort.

The sixth exemplary embodiment shown in FIG. 7 differs from the fourth exemplary embodiment according to FIG. 5a only in that the subband TB1 is not fed in the desired frequency position. For this reason, a complex mixer 51 is assigned to the complex half-band filter 19.

Of course, this additional mixer 51 can also be used in all of the above-mentioned exemplary embodiments, provided that the subband TB1 is not in the desired frequency position.

Another possibility, not shown, of an FDM interface circuit is to provide an arrangement with M branches instead of the arrangement with two processing branches shown in FIG. 7 (M = integer> 2). This means that instead of two DFM signals, M DFM signals with M> 2 are combined to form an FDM signal and, instead of half-band filters for doubling the sampling rate, B-th band filters are provided to increase the sampling rate by a factor of M. Compare: N. Fly: multi-rate signal processing, Teubner 1993

In addition, the structures described can be used not only to summarize, but also to separate a common signal into two individual signals. The measures necessary for this are known to the person skilled in the art, which is why Place is not discussed in more detail, compare claim 14).

Claims

Expectations

1. Digital signal processing device for transmitting a digital FDM signal, with at least two DFM circuits (3, 5), each of which is supplied with a plurality of channels and which each generate an FDM signal, each of which comprises a subband, with one transmission cut - Position circuit (7) is provided, which is arranged downstream of the DFM circuits (3, 5) and which the FDM output signals

DFM circuits combined into a single FDM signal for transmission, characterized in that the transmission interface circuit (7) has the following:

a) two complex half-band filters (19, 21), each of which is connected to one of the two DFM circuits (3, 5),

b) a complex half-band filter for doubling the sampling rate (27), to which a signal composed of the two output signals of the half-band filters (19, 21) is fed.

2. Digital signal processing device according to claim 1, characterized in that at least one output signal is first fed to a complex mixer (25) for shifting the frequency position.

3. Digital signal processing device according to claim l or 2, characterized in that the complex half-band filter are designed so that their center frequency is 1/4 or 3/4 of the sampling frequency.

4. Digital signal processing device according to the preamble of claim 1, characterized in that the transmission interface circuit has the following:

b) furthermore a complex half-band filter for doubling the sampling rate (27), to which a signal composed of the two output signals of the half-band filters (19, 21) is added.

5. Digital signal processing device according to claim 4, characterized in that a complex mixer (25) for frequency shift is arranged between at least one DFM circuit and a half-band filter.

6. Digital signal processing device according to claim 4 or 5, characterized in that the two half-band filters (19, 21) are designed so that they share state memory.

7. Digital signal processing device according to the preamble of claim 1, characterized in that the transmission interface circuit (7) has two complex half-band filters (19, 21), each of which is connected to one of the two DFM circuits (3, 5) and their outputs are connected to a complex half-band filter (31, 33) for doubling the sampling rate.

8. Digital signal processing device according to claim 7, characterized in that at least one output is assigned a complex mixer (25) for shifting the frequency position.

9. Digital signal processing device according to the preamble of claim 1, characterized in that the transmission interface circuit (7) has two complex half-band filters (19, 21), each of which is connected to one of the two DFM circuits (3, 5), and one with the Outputs of the complex half-band filter (19, 21) connected complex filter filter (37), which comprises two complex half-band filter for doubling the sampling rate.

10. Digital signal processing device according to claim 9, characterized in that at least one input signal of the complex filter switch (37) first a complex mixer

(25) is supplied for frequency shift

11. A digital signal processing device according to the preamble of claim 1, characterized in that the transmission interface circuit (7) has a half-band filter connected to a DFM circuit (3) for sampling rate doubling (39) and furthermore has a complex half-band filter (21) , which is connected to the other DFM circuit (5) and which is followed by a complex mixer (25) for shifting the frequency position and a complex half-band filter (33) with sampling rate doubling, and furthermore has a real-valued adder (35), which has the real-valued output signals of summarizes two complex half-band filters for doubling the sampling rate (31, 33).

12. Digital signal processing device according to one of the preceding claims, characterized in that a further complex mixer (51) is provided so that both output signals of the DFM circuits (3, 5) are shifted in frequency before they are combined.

13. Digital signal processing device according to one of the preceding claims, characterized in that the complex half-band filters are designed as general recursive (IIR) or non-recursive (FIR) filters.

14. Digital signal processing device according to one of the preceding claims, characterized in that instead of two DFM signals, M DFM signals with M> 2 are combined to form an FDM signal and, instead of half-band filters for doubling the sampling rate, M-tel band filters for increasing the sampling rate are provided by a factor of M.

15. Digital signal processing device for separating FDM signals into partial FDM signals (subband signals), characterized in that in a signal processing device according to one of the preceding claims, all signal flow and arrow directions are reversed, sample rate increases are replaced by reductions and that all adders are replaced by branches and all branches are replaced by adders.

16. Digital signal processing device according to one of the preceding claims, characterized in that the input and output signals of the transmission interface circuit (7) are each real and at least one of the FDM output signals of the DFM circuits in the transmission interface circuit (7) in a complex signal is converted for further processing and that the real-value output signal of the transmission interface circuit (7) represents the real or the imaginary part of the complex output signal obtained during further processing.

17. Digital signal processing device according to one of the preceding claims, characterized in that it is designed so that the unnecessary portions of the output signal (real or imaginary part) are not calculated at all.

18. Digital signal processing device according to one of the preceding claims, characterized in that the DFM circuits (3, 5) are suitable for the transmission of approximately 32 individual channels with a total bandwidth of approximately 224 MHz.