EP0885503B1 - Procede et systeme de creation d'une interface cryptographique de toute securite entre la machine de decryptage et le decodeur du systeme d'un televiseur numerique - Google Patents

Procede et systeme de creation d'une interface cryptographique de toute securite entre la machine de decryptage et le decodeur du systeme d'un televiseur numerique Download PDF

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Publication number
EP0885503B1
EP0885503B1 EP97946000A EP97946000A EP0885503B1 EP 0885503 B1 EP0885503 B1 EP 0885503B1 EP 97946000 A EP97946000 A EP 97946000A EP 97946000 A EP97946000 A EP 97946000A EP 0885503 B1 EP0885503 B1 EP 0885503B1
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EP
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Prior art keywords
bitstream
decrypted
decryption engine
scrambling
scrambled
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EP97946000A
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German (de)
English (en)
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EP0885503A3 (fr
EP0885503A2 (fr
Inventor
David Cuccia
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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Publication of EP0885503A3 publication Critical patent/EP0885503A3/fr
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/418—External card to be used in combination with the client device, e.g. for conditional access
    • H04N21/4181—External card to be used in combination with the client device, e.g. for conditional access for conditional access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H04N21/4367—Establishing a secure communication between the client and a peripheral device or smart card
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
    • H04N21/4385—Multiplex stream processing, e.g. multiplex stream decrypting
    • H04N21/43853—Multiplex stream processing, e.g. multiplex stream decrypting involving multiplex stream decryption
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/16—Analogue secrecy systems; Analogue subscription systems
    • H04N7/167—Systems rendering the television signal unintelligible and subsequently intelligible
    • H04N7/1675—Providing digital key or authorisation information for generation or regeneration of the scrambling sequence

Definitions

  • the present invention relates generally to security measures for digital receivers, and more particularly, to a method and apparatus for providing a cryptographically secure interface between the decryption engine and the system decoder of a digital television receiver.
  • a variety of systems have been developed to prevent piracy of digital television signals in present and future cable or satellite subscription digital television systems (e.g., digital television systems based on the MPEG-2 digital video compression standard, as described in the ISO/IEC 13818 document, such as the ATSC Digital Television Standard).
  • the digital television signals are encrypted by the service provider prior to transmission, and then decrypted upon reception.
  • a system subscriber is provided with a digital television receiver which includes a decryption engine (contained in either a separate set-top box or integrated within the digital television receiver itself) connected between the cable feed or satellite receiver and the subscriber's television set.
  • decryption engine contained in either a separate set-top box or integrated within the digital television receiver itself
  • There are several well-known encryption algorithms which can be utilized, including the Diffie-Hellman, RSA (Rivest-Shamir-Adleman), and DES (Data Encryption Standard) encryption algorithms.
  • the decryption engine decrypts the encrypted television signal received by the digital television receiver in accordance with the corresponding decryption algorithm, using both a public key which depends upon the particular encryption algorithm employed, and a private key which is unknown and concealed within the decryption engine.
  • the integrity of the security afforded by such systems depends upon preservation of the secrecy of the private key.
  • the most secure method of implementing the decryption engine is to integrate the decryption engine onto the same die as the system decoder to thereby provide an integrated circuit (IC).
  • IC integrated circuit
  • a system decoder de-multiplexes the Packetized Elementary Streams (PES) from the Transport Stream.
  • PES Packetized Elementary Streams
  • MPEG-2 type streams it is possible to (a) take PES packets and form Transport Packet from them. The Transport Packets can then be encrypted. It is also possible to (b) encrypt the PES packets, then from the encrypted PES packet form Transport Packets, which are delivered as is.
  • (c) encrypt data in PES packets, then form Transport Packets from the encrypted PES data, and have each Transport Packet payload encrypted again. If method (a) is used, then the digital receiver should decrypt the Transport Packet payload first, then perform the de-multiplexing required to recover the PES packet (decryption before de-multiplexing). If method (b) is used, the digital receiver should de-multiplex the Transport Packets to form the encrypted PES packet, then decrypt the PES packet (decryption after de-multiplexing). If method (c) is used, then decryption before and after de-multiplexing will be required.
  • the system decoder and decryption engine are connected by wiring internal to the IC, using specialized masks and layouts which make reverse engineering of the decryption engine very difficult.
  • a hard-wired IC does not afford a great deal of flexibility to the system designer, since it can not be modified and thus, can support only a single encryption scheme, to the exclusion of all others.
  • separate ICs which are specifically designed to support different, respective encryption algorithms must be employed for services which utilize different encryption algorithms.
  • a more flexible method of implementing the decryption engine is to use a general purpose digital signal processing device (e.g., a field programmable gate/logic array (FPGA or FPLA) or ASIC core) which can be reconfigured with software to support different encryption algorithms.
  • a general purpose digital signal processing device e.g., a field programmable gate/logic array (FPGA or FPLA) or ASIC core
  • FPGA or FPLA field programmable gate/logic array
  • ASIC core A more flexible method of implementing the decryption engine
  • Another method of implementing the decryption engine is to implement the decryption engine and the system decoder on separate chips, so that the decryption engine is off-chip from the system decoder. In this way, different decryption engines may be utilized by simply substituting chips.
  • this is a particularly flexible method of implementing the decryption engine, the system security is compromised due to the exposure of the interconnect between the system decoder and the decryption engine to the outside world, and the resultant vulnerability of the exposed interconnect to the following type of attack.
  • an attacker can read the cipher text (i.e., the encrypted bitstream) from the interconnect (e.g., from a first parallel or serial data bus), and the corresponding plain text (i.e., the decrypted bitstream) from the interconnect (e.g., from a second parallel or serial data bus).
  • Access to the cipher text and plain text enables an attacker to perform known-plain text, and chosen cipher text attacks on the decryption engine in an attempt to recover all or part of the private key.
  • cryptanalysis an attack to recover the private key or the entitlement key of a decryption scheme is known as cryptanalysis.
  • a special subset of cryptanalysis is called differential cryptanalysis, and is effective on the DES encryption/decryption scheme.
  • an attacker could employ a chosen-cipher text attack so that a differential cryptanalysis could be performed on the decryption engine, thereby recovering the entitlement key.
  • an exposed interface allows an attacker to employ laboratory equipment to supply cipher text and measure corresponding plain text without difficulty. Under such conditions, an attacker needs to know only the encryption scheme employed, and the public key of the service provider and/or of the client (subscriber).
  • the individual subscriber's set-top box is provided with an encryption engine and a transmitter, so that the subscriber can input data (e.g., via a keypad) which is encrypted and "signed" for authentication with the private key prior to transmission.
  • the attacker who uncovers the private key can also use the private key to impersonate the legitimate subscriber.
  • US-A 5,511,125 discloses an interface for a device for the exploitation of electrical signals between a receiver of this device and a device for the exploitation of these signals.
  • the interface is capable of sending, alternatively, signals received by the receiver to an external circuit and signals delivered by the external circuit to the exploitation circuit.
  • the interface enables the direct connection, without digital/analog conversion, of synthesis video generators such as subtitling machines, games terminals and personal computers.
  • the interface further enables the function of unscrambling digital television signals to be transferred to a detachable element.
  • An object of the invention is to provide a secure interface between a decryption engine and a system decoder of a digital receiver, e.g., an MPEG-2 digital television receiver.
  • the invention provides a method for providing a secure interface, a digital receiver, a system decoder and a decryption engine as defined in the independent claims.
  • Advantageous embodiments are defined in the dependent claims.
  • the system decoder receives an encrypted bitstream and produces a cipher text bitstream which is supplied to the decryption engine via a first parallel data bus which includes a plurality N of parallel bit lines corresponding to respective N bits of the cipher text bitstream.
  • the decryption engine decrypts the cipher text bitstream and produces a plain text bitstream which is supplied to the system decoder via a second parallel data bus which includes a plurality N of parallel bit lines corresponding to respective N bits of the plain text bitstream.
  • the method includes the steps of scrambling the bit order of the N bits of the cipher text bitstream on the respective N bit lines of the first data bus, to thereby produce a scrambled cipher text bitstream N-bits wide, descrambling the bit order of the N bits of the scrambled cipher text bitstream, to thereby produce a descrambled cipher text bitstream which is the same as the original cipher text bitstream, employing the decryption engine to decrypt the descrambled cipher text bitstream, to thereby produce the plain text bitstream, scrambling the bit order of the N bits of the plain text bitstream on the respective N bit lines of the second data bus, to thereby produce a scrambled plain text bitstream N-bits wide, and, descrambling the bit order of the N bits of the scrambled plain text bitstream, to thereby produce a descrambled plain text bitstream which is the same as the original plain text bitstream.
  • the step of scrambling the bit order of the N bits of the cipher text bitstream is performed in accordance with a first bit-scrambling algorithm, and the step of scrambling the bit order of the N bits of the plain text bitstream is performed in accordance with a second bit-scrambling algorithm.
  • the first and second bit-scrambling algorithms may either be the same or different.
  • the first bit-scrambling algorithm is a different one of a plurality of possible first bit-scrambling algorithms for each of a plurality of successive power-up cycles of the digital receiver
  • the second bit-scrambling algorithm is a different one of a plurality of different possible second bit-scrambling algorithms for each separate power-up cycle of the digital receiver.
  • the step of descrambling the bit order of the N bits of the scrambled cipher text bitstream is performed in accordance with a first bit-descrambling algorithm which is the inverse of the first bit-scrambling algorithm
  • the step of descrambling the bit order of the N bits of the scrambled plain text bitstream is performed in accordance with a second bit-descrambling algorithm which is the inverse of the second bit-scrambling algorithm.
  • the present invention also encompasses a digital receiver which includes a system decoder for receiving an encrypted bitstream and producing a cipher text bitstream, a decryption engine for decrypting the cipher text bitstream and producing a plain text bitstream, a first parallel data bus which includes a plurality N of parallel bit lines coupled between a parallel output port of the system decoder and a parallel input port of the decryption engine, a second parallel data bus which includes a plurality N of parallel bit lines coupled between a parallel output port of the decryption engine and a parallel input port of the system decoder.
  • the system decoder includes a cipher text scrambler module for scrambling the bit order of N bits of the cipher text bitstream on the N bit lines of the first data bus, to thereby produce a scrambled cipher text bitstream N-bits wide which is supplied to the parallel input port of the decryption engine via the first parallel data bus.
  • the decryption engine includes a cipher text descramble module for descrambling the bit order of the N bits of the scrambled cipher text bitstream, to thereby produce a descrambled cipher text bitstream which is the same as the original cipher text bitstream.
  • the decryption engine further includes a plain text scramble module for scrambling the bit order of N bits of the plain text bitstream on the N bit lines of the second data bus, to thereby produce a scrambled plain text bitstream N-bits wide which is supplied to the parallel input port of the system decoder via the second parallel data bus.
  • the system decoder further includes a plain text descramble module for descrambling the bit order of the N bits of the scrambled plain text bitstream, to thereby produce a descrambled plain text bitstream which is the same as the original plain text bitstream.
  • system decoder and the decryption engine are preferably coupled to a common power source and are power-cycled together, whereby the first and second state machines synchronously cycle through respective sequences of complementary first and second states over a plurality of successive power-up cycles, and the third and fourth state machines synchronously cycle through respective sequences of complementary third and fourth states over a plurality of successive power-up cycles.
  • a digital receiver 10 e.g., an MPEG-2 digital television receiver, includes a decryption engine 12 and a system decoder 14 which communicate with one another via a pair of data busses 16, 18, e.g., 16-bit wide parallel data busses, which together comprise the interconnect between the decryption engine 12 and the system decoder 14.
  • the system decodes 14 includes, in addition to its usual decoder circuitry, a cipher text scramble circuit or module 20 and a plain text descramble circuit or module 22, and the decryption engine 12 includes, in addition to its usual decryption circuitry, a cipher text descramble circuit or module 24 and a plain text scramble circuit or module 26.
  • the cipher text scramble module 20 of the system decoder 14 and the cipher text descramble module 24 of the decryption engine 12 communicate via the 16-bit wide parallel bus 16, and the plain text scramble module 26 of the decryption engine 12 and the plain text descramble module 22 of the system decoder 14 communicate via the 16-bit wide parallel bus 18.
  • the bit order (bit position) of the bits comprising the cipher text bitstream is scrambled by the cipher text scramble module 20 of the system decoder 14, in accordance with any suitable bit-scrambling algorithm.
  • the odd-numbered bits of the cipher text bitstream could be placed on the even-numbered bit lines of the parallel data bus 16
  • the even-numbered bits of the cipher text bitstream could be placed on the odd-numbered bit lines of the parallel data bus 16.
  • the particular bit-scrambling algorithm employed in scrambling the bit order of the cipher text bitstream is not in any way limiting to the present invention.
  • the bit order of the bits comprising the plain text bitstream produced by the decryption engine 12 is scrambled by the plain text scramble module 26 of the decryption engine 12, in accordance with any suitable bit-scrambling scheme.
  • the odd-numbered bits of the plain text bitstream could be placed on the even-numbered bit lines of the parallel data bus 18, and the even-numbered bits of the plain text bitstream could be placed on the odd-numbered bit lines of the parallel data bus 18.
  • the particular bit-scrambling algorithm employed to scramble the bit order of the plain text bitstream is also not in any way limiting to the present invention. In this connection, it will be appreciated that the bit-scrambling algorithm used to scramble the bit order of the cipher and plain text bitstreams may be the same or different.
  • the plain text descramble module 22 of the system decoder 14 then functions to descramble the bit order of the scrambled plain text bitstream received over the parallel data bus 18 by executing a bit-descrambling algorithm which is the inverse of the bit-scrambling algorithm executed by the plain text scramble module 26 of the decryption engine 12 to thereby produce a descrambled plain text bitstream, which is subsequently processed in the normal manner.
  • this is accomplished by implementing the cipher text scramble module 20 and the cipher text descramble module 24 as complementary state machines, and by implementing the plain text scramble module 26 and the plain text descramble module 22 as complementary state machines.
  • Each pair of compelementary state machines will cycle through a plurality of different complementary states corresponding to a plurality of different bit-scrambling/descrambling algorithms, e.g., on successive power-up cycles of the digital television receiver 10.
  • the state machines are configured to have a large number of states, so that they do not "wrap around" and repeat the same pattern of states in a short period of successive power-up cycles.
  • the interconnect between the decryption engine 12 and the system decoder 14 is comprised of a pair of 16-bit wide parallel data busses 16, 18, there are, in theory, 2 16 different possible bit patterns (and thus, 2 16 possible states of the respective state machines) which could be invoked in order to scramble the order (position) of the bits of the 2-byte words carried by the 16-bit wide parallel data busses 16, 18.
  • the state machines are identical. Each state machine has the same initialization vector. When the power is cycled, the next state in the state machine is realized. Since the decryption engine 12 and the system decoder 14 are coupled to a common power supply, they are power-cycled together, so that the state machines in each the decryption engine 12 and the system decoder 14 are intrinsically synchronized. The output of each state machine (for a given input) is dependent upon the current state of that state machine. Thus, the bit-scrambling/descrambling algorithm executed by each state machine is dependent upon its current state (or seed state).
  • the requirement that the cipher text scramble module 20 of the system decoder 14 and the cipher text descramble module 24 of the decryption engine 12 be synchronized in such a manner as to run the complementary bit-scrambling/descrambling algorithms at the same time, at all times, and that the plain text scramble module 26 of the decryption engine 12 and the plain text descramble module 22 of the system decoder 14 be synchronized in such a manner as to run the complementary bit-scrambling/descrambling algorithms at the same time, at all times, can be easily satisfied by configuring the cipher text scramble module 20 state machine and the cipher text descramble module 24 state machine to cycle through the same number of complementary states during successive power-up cycles, and by configuring the plain text scramble module 26 and the plain text descramble module 22 to cycle through the same number of complementary states during successive power-up cycles.
  • the interface therebetween will be "out of sync", thereby preventing any communication therebetween. If this occurs, it is preferable that this "out of sync" status not be correctable by any means (hardware or software) within the system, since this would compromise the cryptographical security of the system.
  • the following four additional anti-piracy measures can be taken in order to increase the difficulty and cost-to-reward ratio of attacking the system:
  • the cipher text descramble module 24, the plain text scramble module 26, and the plain text descramble module 22 could be implemented as signal processing circuits under the control of respective state machines, with the output of the state machines being utilized as control signals.
  • the output of the state machines could be used as addresses to look-up different bit patterns (bit position combinations) stored in a read-only (ROM), or as seed states for linear feedback shift registers (LFSR's) generating bit patterns.
  • the output of the state machines could be transformed by the respective signal processing circuits in order to produce the final bitstreams.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Storage Device Security (AREA)

Claims (18)

  1. Procédé pour procurer une interface (16, 18) entre un moteur de déchiffrement (12) et un décodeur de système (14) d'un récepteur numérique (10), dans lequel le décodeur de système (14) reçoit un train de bits chiffré, lequel est fourni (16) au moteur de déchiffrement (12), et dans lequel le moteur de déchiffrement (12) déchiffre le train de bits chiffré;
       le procédé étant caractérisé en ce qu'il comporte les étapes suivantes :
    brouillage (20) dans ledit décodeur de système (14) du train de bits chiffré, afin de produire ainsi un train de bits chiffré brouillé;
    désembrouillage (24) dans ledit moteur de déchiffrement (12) du train de bits chiffré brouillé, afin de produire ainsi un train de bits chiffré désembrouillé, lequel est identique au train de bits chiffré d'origine;
    utilisation (12) du moteur de déchiffrement (12) pour déchiffrer le train de bits chiffré désembrouillé, afin de produire ainsi un train de bits déchiffré;
    brouillage (26) dans ledit moteur de déchiffrement (12) du train de bits déchiffré, afin de produire ainsi un train de bits déchiffré brouillé, et
    désembrouillage (22) dans ledit décodeur de système (14) du train de bits déchiffré brouillé, afin de produire ainsi un train de bits déchiffré désembrouillé, lequel est identique au train de bits déchiffré d'origine.
  2. Procédé suivant la revendication 1, dans lequel :
    le train de bits chiffré brouillé est fourni, au moteur de déchiffrement (12) par le biais d'un premier bus de données parallèle, lequel comporte une pluralité N de lignes de bits parallèles correspondant à N bits respectifs du train de bits chiffré brouillé;
    le train de bits déchiffré brouillé est fourni au décodeur de système (14) par le biais d'un second bus de données parallèle, lequel comporte une pluralité N de lignes de bits parallèles correspondant à N bits respectifs du train de bits déchiffré brouillé;
    l'étape de brouillage du train de bits chiffré comprend le brouillage de l'ordre des bits des N bits du train de bits chiffré sur les N lignes de bits respectives du premier bus de données, et
    l'étape de brouillage du train de bits déchiffré comprend le brouillage de l'ordre des bits des N bits du train de bits déchiffré sur les N lignes de bits respectives du second bus de données.
  3. Procédé suivant la revendication 1, dans lequel :
    le train de bits chiffré brouillé est fourni au moteur de déchiffrement (12) par le biais d'un premier bus de données parallèle (16), lequel comporte une pluralité N de lignes de bits parallèles correspondant à N bits respectifs du train de bits chiffré brouillé;
    le train de bits déchiffré brouillé est fourni au décodeur de système (14) par le biais d'un second bus de données parallèle (18), lequel comporte une pluralité N de lignes de bits parallèles correspondant à N bits respectifs du train de bits déchiffré brouillé;
    l'étape de brouillage du train de bits chiffré comprend le retardement de chacun des N bits respectifs du train de bits chiffré à raison d'une période de temps variable, et
    l'étape de brouillage du train de bits déchiffré comprend le retardement de chacun des N bits respectifs du train de bits déchiffré à raison d'une période de temps variable.
  4. Procédé suivant la revendication 1, dans lequel :
    l'étape de brouillage du train de bits chiffré est exécutée suivant un premier algorithme de brouillage de bits, et
    l'étape de brouillage du train de bits déchiffré est exécutée suivant un second algorithme de brouillage de bits.
  5. Procédé suivant la revendication 4, dans lequel les premier et second algorithmes de brouillage de bits sont identiques.
  6. Procédé suivant la revendication 4, dans lequel les premier et second algorithmes de brouillage de bits sont différents.
  7. Procédé suivant la revendication 4, dans lequel le premier algorithme de brouillage de bits est un différent de plusieurs premiers algorithmes de brouillage de bits possibles pour chacun de plusieurs cycles de mise sous tension successifs du récepteur numérique.
  8. Procédé suivant la revendication 4, dans lequel le second algorithme de brouillage de bits est un différent de plusieurs seconds algorithmes de brouillage de bits possibles pour chacun de plusieurs cycles de mise sous tension successifs du récepteur numérique.
  9. Récepteur numérique (10) comportant :
    un décodeur de système (14) pour recevoir un train de bits chiffré, et
    un moteur de déchiffrement (12) pour déchiffrer le train de bits chiffré et produire un train de bits déchiffré,
    le récepteur numérique étant caractérisé en ce qu'il comporte :
    un premier module de brouillage (20) intégré dans ledit décodeur de système (14) pour brouiller le train de bits chiffré, afin de produire ainsi un train de bits chiffré brouillé;
    un premier module de désembrouillage (24) intégré dans ledit moteur de déchiffrement (12) pour désembrouiller le train de bits chiffré brouillé, afin de produire ainsi un train de bits chiffré désembrouillé, lequel est identique au train de bits chiffré d'origine;
    un second module de brouillage (26) intégré dans le moteur de déchiffrement (12) pour brouiller le train de bits déchiffré, afin de produire ainsi un train de bits déchiffré brouillé, et
    un second module de désembrouillage (22) intégré dans ledit décodeur de système (14) pour désembrouiller le train de bits déchiffré brouillé, afin de produire ainsi un train de bits déchiffré désembrouillé, lequel est identique au train de bits déchiffré d'origine.
  10. Récepteur numérique (10) suivant la revendication 9, dans lequel le récepteur numérique comporte un téléviseur numérique.
  11. Récepteur numérique (10) suivant la revendication 9, dans lequel ledit décodeur de système (14) et ledit moteur de déchiffrement (12) sont mis en oeuvre sous la forme de première et seconde puces séparées.
  12. Récepteur numérique suivant la revendication 11, comportant en outre des premier et second boítiers BGA pour mettre sous boítier lesdites première et seconde puces.
  13. Décodeur de système (14) pour recevoir un train de bits chiffré, le décodeur de système (14) étant caractérisé en ce qu'il comporte :
    un module de brouillage (20) pour brouiller le train de bits chiffré, afin de produire ainsi un train de bits chiffré brouillé à fournir à un moteur de déchiffrement (12), et
    un module de désembrouillage (22) pour désembrouiller un train de bits déchiffré brouillé produit par le moteur de déchiffrement (12), afin de produire ainsi un train de bits déchiffré désembrouillé.
  14. Moteur de déchiffrement (12) pour déchiffrer un train de bits chiffré et produire un train de bits déchiffré, le moteur de déchiffrement (12) étant caractérisé en ce qu'il comporte :
    un module de désembrouillage (24) pour désembrouiller un train de bits chiffré brouillé afin de produire ainsi un train de bits chiffré, et
    un module de brouillage (26) pour brouiller le train de bits déchiffré, afin de produire ainsi un train de bits déchiffré brouillé.
  15. Procédé pour procurer une interface (16, 18) entre un moteur de déchiffrement (12) et un décodeur de système (14) d'un récepteur numérique (10), dans lequel le moteur de déchiffrement (12) déchiffre un train de bits chiffré afin de produire un train de bits déchiffré;
       le procédé étant caractérisé en ce qu'il comporte les étapes suivantes :
    brouillage (26) dans ledit moteur de déchiffrement (12) du train de bits déchiffré, afin de produire ainsi un train de bits déchiffré brouillé;
    désembrouillage (22) dans ledit décodeur de système (14) du train de bits déchiffré brouillé, afin de produire ainsi un train de bits déchiffré désembrouillé, lequel est identique au train de bits déchiffré d'origine.
  16. Récepteur numérique (10) comportant :
    un moteur de déchiffrement (12) pour déchiffrer un train de bits chiffré et produire un train de bits déchiffré, et
    un décodeur de système (14),
    le récepteur numérique étant caractérisé en ce qu'il comporte :
    un module de brouillage (26) intégré dans ledit moteur de déchiffrement (12) pour brouiller le train de bits déchiffré, afin de produire ainsi un train de bits déchiffré brouillé; et
    un module de désembrouillage (22) intégré dans ledit décodeur de système (14) pour désembrouiller le train de bits déchiffré brouillé, afin de produire ainsi un train de bits déchiffré désembrouillé, lequel est identique au train de bits déchiffré d'origine.
  17. Décodeur de système (14) caractérisé en ce qu'il comporte :
    un module de désembrouillage (22) pour désembrouiller un train de bits déchiffré brouillé produit par un moteur de déchiffrement (12), afin de produire ainsi un train de bits déchiffré désembrouillé.
  18. Moteur de déchiffrement (12) pour déchiffrer un train de bits chiffré et produire un train de bits déchiffré, le moteur de déchiffrement (12) étant caractérisé en ce qu'il comporte :
    un module de brouillage (26) pour brouiller le train de bits déchiffré afin de produire ainsi un train de bits déchiffré brouillé.
EP97946000A 1996-12-18 1997-12-11 Procede et systeme de creation d'une interface cryptographique de toute securite entre la machine de decryptage et le decodeur du systeme d'un televiseur numerique Expired - Lifetime EP0885503B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/768,489 US5818934A (en) 1996-12-18 1996-12-18 Method and apparatus for providing a cryptographically secure interface between the decryption engine and the system decoder of a digital television receiver
US768489 1996-12-18
PCT/IB1997/001558 WO1998027687A2 (fr) 1996-12-18 1997-12-11 Procede et systeme de creation d'une interface cryptographique de toute securite entre la machine de decryptage et le decodeur du systeme d'un televiseur numerique

Publications (3)

Publication Number Publication Date
EP0885503A2 EP0885503A2 (fr) 1998-12-23
EP0885503A3 EP0885503A3 (fr) 1999-12-29
EP0885503B1 true EP0885503B1 (fr) 2003-05-07

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EP97946000A Expired - Lifetime EP0885503B1 (fr) 1996-12-18 1997-12-11 Procede et systeme de creation d'une interface cryptographique de toute securite entre la machine de decryptage et le decodeur du systeme d'un televiseur numerique

Country Status (5)

Country Link
US (1) US5818934A (fr)
EP (1) EP0885503B1 (fr)
JP (1) JP4302189B2 (fr)
DE (1) DE69721743T2 (fr)
WO (1) WO1998027687A2 (fr)

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JP2000507072A (ja) 2000-06-06
DE69721743T2 (de) 2004-03-18
WO1998027687A3 (fr) 1998-08-20
JP4302189B2 (ja) 2009-07-22
WO1998027687A2 (fr) 1998-06-25
EP0885503A3 (fr) 1999-12-29
DE69721743D1 (de) 2003-06-12
EP0885503A2 (fr) 1998-12-23
US5818934A (en) 1998-10-06

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