EP0858178B1 - Method and apparatus for mixing digital audio signals - Google Patents

Description

The invention relates to a method and apparatus for mixing digital audio signals from a first number of inputs to a second number of outputs.

Such methods and devices are already known and are used in so-called digital or digitally working audio mixing consoles. Digital mixing consoles make it possible to transmit incoming sound signals in several different channels individually or collectively to any output. The individual sound signals can be changed and combined with other sound signals. This means that it should be possible to multiply each signal by a factor and to add it with other signals and possibly delay the sound signals.

EP-A-0 462 799 describes an apparatus for mixing digital audio signals.

Known digital mixing consoles therefore have devices in which the inputs are connected in pairs or groups to digital signal processors (DSPs) which are easily capable of performing such operations as addition, multiplication and storage of audio signals. However, one encounters limits when trying to direct as many inputs as possible to a signal processor, because these are not provided with suitable interfaces and can not provide the required computing power for many channels. This is because sound signals in given periods contain relatively large amounts of data.
These problems caused by the large amount of data are usually mitigated by assigning only a small number of inputs to a signal processor, which means that for a given number of inputs and outputs, several signal processors are provided which must be switched to cascades. The biggest problem is the summation of the sound signals from a large number of inputs or just from several such signal processors in a so-called sum bus.
Therefore, solutions with so-called TDM buses or systems with shared memories, so-called "shared memory" systems, have already become known as a sum bus. A TDM bus is a parallel bus which holds a time window for the data from each input channel, so that the signals in the bus occur serially in series. It is also conceivable to use DPRAM memory and to interconnect the processors like a so-called "daisy-chain". However, all these solutions are technically complicated and expensive.

The invention, as characterized in the claims, therefore solves the problem to provide a method for mixing digital audio signals, which are much easier and cheaper.

The solution to this problem is achieved in particular by using simple circuits or programmable components such as programmable logic modules, PLDs or customer-specific integrated circuits ASICS for the summation of the audio signals from the individual inputs or channels, which are used for the bitwise summation of the word and bitwise synchronized data streams Sound signals are formed and used. For this, however, the data words must be transmitted ahead with the least significant bit, which requires a corresponding formatting of the data streams. For possible additional processing of the signals prior to the summation, a bitwise multiplication of the relevant data stream is provided, wherein the data stream is fed several times to a summer, but the multiply supplied data streams are offset or delayed by one bit. Thus, the data words of the incoming audio signals are routed to each other so that the data bits in ascending order ahead with the least significant bit occur in parallel data streams synchronized wordwise and bitwise and are bitwise summed. For this purpose, each output is preceded by a summer, which is connected to at least a part of the inputs via the processing elements.

The advantages achieved by the invention are to be seen in particular in that the device can be realized very inexpensively. One reason for this is that the proposed summation of the data streams requires very little memory. Another reason is that for the formatting and for any further processing of the Data from the individual inputs or channels now relatively simple and inexpensive digital signal processors (DSPs) can be used, a signal processor, if he has multiple inputs can also serve multiple channels, since he only has to fulfill relatively simple tasks. This is just possible because a complex task, namely the summation of the data streams no longer needs to be fulfilled by the signal processors. However, it can also be provided that a signal processor adds data streams as far as possible, so that partial summations are already supplied to the summer. But this should only happen as far as this can be done in a single signal processor.

• Fig. 1 ein Blockschema einer erfindungsgemässen Vorrichtung,
• Fig. 2 eine schematische aber detailliertere Darstellung eines Teils der Vorrichtung gemäss Fig. 1,
• Fig. 3 eine schematische Darstellung eines weiteren Teils der Vorrichtung gemäss Fig. 1 und
• Fig. 4 und 5 je eine schematische Dartellung eines Verfahrensschrittes.

In the following the invention will be explained in more detail with reference to drawings showing only one embodiment. It shows

• 1 is a block diagram of an inventive device,
• 2 shows a schematic but more detailed representation of a part of the device according to FIG. 1,
• Fig. 3 is a schematic representation of another part of the device according to FIGS. 1 and
• 4 and 5 each show a schematic Dartellung a process step.

Fig. 1 shows an apparatus for mixing digital audio signals with multiple inputs 1, 2, 3, 4, 5 and m, which indicates that a number of m inputs is possible, with up to m = 64 channels are common today. The inputs 1 to m lead into a respective processing unit 10, 11, 12, 13, which can be constructed either as a digitally operating signal processor DSP or otherwise as a unit for digital signal processing. A processing unit can also be connected to a plurality of inputs, as is indicated for the processing unit 10 with the inputs 1, 2 and 3. The device has outputs 21, 22, 23 and n, today up to n = 32 outputs are not uncommon. Each output 21 to n is preceded by a summer 17, 18, 19, 20. Each processing unit 10, 11, 12, 13, and therefore each input 1 to m, is connected via several or ideally all outputs 21 to n connected. This is done for the processing unit 10 here via lines 101, 102, 103, 104 which lead from corresponding outputs on the processing units 10 to 13 to inputs to the summers 17 to 20. In Fig. 1, such inputs and outputs and part of the necessary connections are shown. The representation of all compounds was omitted to ensure the clarity of the presentation. Optionally, the outputs, as here output 21, also open into a format converter 24, which in turn may have a plurality of parallel outputs 25. This is especially true if audio signals from several channels are supplied serially via an input. These audio signals can then be output in parallel. Further, in the lines 101, 102, etc., another processing element 26 may be inserted, which can attenuate or amplify the signal. Such another processing element 26 is connected together with the other processing elements 10 to 13 via control lines 28 to an operating unit 27, which has those operating elements that are usually present on the user interface of a mixing console. The format converter 24 may also be a digitally operating signal processor (DSP) or else a signal processing element. Preferably, the summers 17 to 20 form a sum bus in a digitally working audio mixing console.

Fig. 2 shows an embodiment of a summer 17 to 20. Such consists of at least three two-bit adders 30, 31 and 32, each having an input 33, 34 and 35 for a first clock signal, one input 36, 37 and 38 for another Clock signal and two inputs 39 and 40, 41 and 42 and 43 and 44 for digitized audio signals. In this case, the two two-bit adders 30 and 31 are connected in parallel and their outputs are connected to the inputs 43, 44 of the third two-bit adder 32. If audio signals from more than four inputs 39, 40, 41, 42 are to be processed, the structure is supplemented by three further two bit adders 45, 46, 47. However, the outputs 48, 49 of the two-bit adders 32 and 47 lead to an additional two-bit adder 50. Thus, the structure can be cascaded for several inputs. However, the summer can also be constructed in the same sense from two-bit or Mehrbitaddierern. For example, if three-bit adders are used, each three-bit adder has three inputs for audio signals and three three-bit adders are connected in parallel with another three-bit adder.

FIG. 3 shows a specific embodiment of a processing element 26, as is known from FIG. This in turn consists of a summer 51 with an output 52 and, for example, three inputs 53, 54, 55. These are preceded by multipliers 56, 57, 58 with two inputs 59 and 60, 61 and 62, 63 and 64. Here, the input 63 provided directly for the unchanged data stream. The inputs 61 and 59 receive the data stream delayed from delay units 65 or 66.

4 shows, for example, three data words W1, W2, W3 which occur synchronized in bit-wise fashion in parallel. Lines 67 indicate first clock signals that control the operations in the bitmap. The data words are moved in the direction of an arrow 70. In this case, each data word W is formatted in such an order that first the least significant bit 68 and finally the most significant bit 69 occurs.

5 shows a representation of data words corresponding to FIG. 4, wherein a time delay corresponding to the time duration assigned to one or two or more bits is provided between data words W11, W12 and W13, which causes the data words W11, W12 and W13 to be delayed by one or two or more bits are shown spatially or temporally offset.

The operation of the device is therefore as follows:
Digitized audio signals are input through inputs 1 through n and are formatted in processing units 10 through 13 in a manner known per se such that the least significant bit is output first and the most significant bit is output last. This can be achieved by a corresponding read-out of a cache. All audio signals output or possibly also input by the processing units 10 to 13 are synchronized with the first clock signal 67, so that each bit in the device is treated synchronously, as shown in FIGS. 4 and 5. In addition, the reading out of the data words from the processing units 10 to 13 takes place synchronously, as shown in FIG. 4. Via the operating unit 27 and the control lines 28, the individual outputs of the processing units 10 to 13 are driven. This specifies for each output of a processing unit whether an audio signal is output there and in which strength.

Thus, each summer 17 to 20 receives from the lines 101 to 104, etc. audio signals which he must sum and then deliver to its output 21 to n. It can also be the case that several audio signals arrive in series via one input. Such signals are treated the same as a single signal. After the output but they can be passed in parallel, as indicated for the output 21 and the parallel outputs 25.
The summation of the bit-wise synchronized audio signals in the summers 17 to 20 can be explained with reference to FIG. Each two signals a and b are at the inputs 39 and 40, further two signals b and c at the inputs 41 and 42. At the inputs 33, 34 and 35 is a first clock signal for bitwise synchronization and at the inputs 36, 37th and 38 is another clock signal indicating the Anfanng (or the end) of a data word, thus causing the word synchronization. The further clock signal is derived from the first clock signal. The signals a and b in the two-bit adder 30 are summed according to the following formula or instruction: (! A AND! B AND cy) OR (! A AND b AND! Cy) OR (a AND! B AND! Cy) OR (a AND b AND cy)

• (a UND b UND !pr) ODER (a UND cy UND !pr) ODER (b UND cy UND !pr), wobei pr ein angelegtes weiteres Taktsignal für das Wortende und !pr Fehlen eines solchen Signales bedeutet (!steht allg. für Fehlen des entspr. Signales). Die anderen Zweibitaddierer arbeiten nach dem gleichen Prinzip und ergeben immer aus zwei Eingangssignalen ein Ausgangssignal. So kann mit der gezeigten Struktur eine beliebige Anzahl Eingangssignale summiert werden. Diese Verarbeitung entspricht der Addition von mehrstelligen Zahlen wie sie im Kopf des Menschen oder bei grösseren Zahlen mit Hilfe einer Rechenmethode durchgeführt und in der Schule gelehrt wird. Das bedeutet, dass zuerst alle niedrigstwertigen Bit 68 addiert werden, wobei ein Übertrag gespeichert wird, so dass er bei der Addition der nächsthöheren Bit zugerechnet werden kann. Zuletzt werden die höchstwertigen Bit 69 untereinander addiert und, sofern vorhanden, der letzte Übertrag berücksichtigt. Die so summierten Datenströme verlassen den Summierer über den Ausgang 21. Dann können sie im Formatkonverter 24 beispielsweise so formatiert werden, dass nun das höchstwertige Bit im Datenwort vorausgeht. Oder der Datenstrom kann aufgeteilt werden und über mehrere Leitungen 25 parallel ausgegeben werden.
  Die Eingangssignale können dabei in ihrem Wert in den Verarbeitungseinheiten 10 bis 13 vor der Summierung verändert oder gewichtet werden. Dies kann aber auch in einem Verarbeitungselement 26 geschehen.
  Ist das Verarbeitungselement 26 als Vorrichtung gemäss Fig. 3 ausgebildet, so wird ein Tonsignal über den Eingang 63 einerseits dem Multiplizierer 58 und andererseits der Verzögerungseinheit 65 zugeführt. Aus der Verzögerungseinheit 65 wird das Ausgangssignal sowohl dem Multiplizierer 57 als auch der weiteren Verzögerungseinheit 66 zugeführt. So sind die Signale, die an den Multiplizierern 56, 57 und 58 anliegen jeweils um ein Bit zueinander versetzt, was durch die Verzögerungseinheiten 65, 66 bewirkt wird. Parallel dazu liegen an den Multiplizierern 56, 57, 58 über die Eingänge 60, 62 und 64 auch je ein Bit eines Multiplikators oder Faktors an, mit dem das Signal im Eingang 63 multipliziert werden soll. So wird ein über den Eingang 63 eintreffendes Datenwort im Multiplizierer 58 mit dem ersten Bit des Faktors, im Addierer 57 mit dem zweiten Bit und im Addierer 56 mit dem dritten Bit des Faktors bitweise multipliziert. So entstehen drei zueinander um ein Bit versetzte Datenwörter, die im Summierer 40 summiert werden. Mit anderen Worten entsteht eine Situation, wie sie Fig. 5 zeigt, so dass die drei Datenworte W11, W12 und W13 nur noch bitweise summiert werden müssen. So soll ein Audiosignal 63 in mehrere gleiche parallele Signale 63, 61, 59 aufgeteilt und mit aufsteigender Verzögerung um je ein Bit verzögert werden. Dann soll das ursprüngliche Signal und die verzögerten Signale mit je einem Bit eines in einem digitalen Wert ausgedrückten Faktor addiert und anschliessend die resultierenden Signale bitweise zu einem veränderten Signal summmiert werden.

The carry cy is treated according to the following rule:

• (a AND b AND! pr) OR (a AND cy AND! pr) OR (b AND cy AND! pr), where pr denotes an applied further clock signal for the word end and! pr the absence of such a signal (! Absence of the corresponding signal). The other two-bit adders operate on the same principle and always give an output signal from two input signals. Thus, any number of input signals can be summed with the structure shown. This processing corresponds to the addition of multi-digit numbers as in the human head or larger numbers using a calculation method and taught in school. This means that first all least significant bits 68 are added, with a carry stored so that it can be added to the next higher bit in the addition. Finally, the most significant bits 69 are added together and, if present, the last carry taken into account. The summed data streams leave the summer via the output 21. Then they can be formatted in the format converter 24, for example, so that now the most significant bit in the data word precedes. Or the data stream can be split and output in parallel via several lines 25.
  The input signals can be changed or weighted in their value in the processing units 10 to 13 before the summation. However, this can also be done in a processing element 26.
  If the processing element 26 is designed as a device according to FIG. 3, then a sound signal is fed via the input 63 on the one hand to the multiplier 58 and on the other hand to the delay unit 65. From the delay unit 65, the output signal is supplied to both the multiplier 57 and the further delay unit 66. Thus, the signals applied to the multipliers 56, 57 and 58 are each offset by one bit from one another, which is effected by the delay units 65, 66. At the same time, one bit of a multiplier or factor is applied to the multipliers 56, 57, 58 via the inputs 60, 62 and 64, with which the signal in the input 63 is to be multiplied. Thus, a data word arriving via the input 63 is multiplied bit by bit in the multiplier 58 by the first bit of the factor, in the adder 57 by the second bit, and in the adder 56 by the third bit of the factor. This results in three data words offset from one another by a bit, which are summed in the summer 40. In other words, a situation arises, as shown in FIG. 5, so that the three data words W11, W12 and W13 only have to be summed bitwise. Thus, an audio signal 63 is to be divided into several identical parallel signals 63, 61, 59 and delayed by one bit each with increasing delay. Then the original signal and the delayed signals are to be added with one bit each of a factor expressed in a digital value and then the resulting signals are summed bit by bit to form an altered signal.

Claims (2)

1. A method of mixing digital audio signals from a first number of inputs (1 to m) into a second number (21 to n) of outputs, characterised in that the data words of the incoming audio signals are so conducted with respect to one another that the data bits occur synchronised wordwise and bitwise in parallel data streams in an ascending sequence with the lowest value bit first and are summed bitwise.
2. A method as claimed in Claim 1, characterised in that an audio signal (63) is divided into a plurality of equal parallel signals (63, 61, 59) and are delayed with a delay which increases each time by one bit and that the signal (63) and the delayed signals (61, 59) are added to a respective bit of a factor expressed in a digital value and the resulting signals (53; 54, 55) are then summed (52) bitwise to form an altered signal.

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