EP0858076A3 - Mémoire multi-étâts et méthode d'acces pour une telle mémoire - Google Patents

Mémoire multi-étâts et méthode d'acces pour une telle mémoire Download PDF

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Publication number
EP0858076A3
EP0858076A3 EP97307574A EP97307574A EP0858076A3 EP 0858076 A3 EP0858076 A3 EP 0858076A3 EP 97307574 A EP97307574 A EP 97307574A EP 97307574 A EP97307574 A EP 97307574A EP 0858076 A3 EP0858076 A3 EP 0858076A3
Authority
EP
European Patent Office
Prior art keywords
valued memory
valued
memory
data access
access method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97307574A
Other languages
German (de)
English (en)
Other versions
EP0858076A2 (fr
Inventor
Tomohiro c/o Fujitsu Comp. Techn. Ltd. Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0858076A2 publication Critical patent/EP0858076A2/fr
Publication of EP0858076A3 publication Critical patent/EP0858076A3/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
EP97307574A 1997-02-06 1997-09-26 Mémoire multi-étâts et méthode d'acces pour une telle mémoire Withdrawn EP0858076A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP24035/97 1997-02-06
JP2403597A JPH10222992A (ja) 1997-02-06 1997-02-06 多値メモリ及び多値メモリに対するデータアクセス方法

Publications (2)

Publication Number Publication Date
EP0858076A2 EP0858076A2 (fr) 1998-08-12
EP0858076A3 true EP0858076A3 (fr) 1999-05-19

Family

ID=12127265

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97307574A Withdrawn EP0858076A3 (fr) 1997-02-06 1997-09-26 Mémoire multi-étâts et méthode d'acces pour une telle mémoire

Country Status (4)

Country Link
US (1) US5907504A (fr)
EP (1) EP0858076A3 (fr)
JP (1) JPH10222992A (fr)
KR (1) KR100279233B1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4437519B2 (ja) 2001-08-23 2010-03-24 スパンション エルエルシー 多値セルメモリ用のメモリコントローラ
KR101414494B1 (ko) * 2008-03-17 2014-07-04 삼성전자주식회사 메모리 장치 및 메모리 데이터 읽기 방법
US8321764B2 (en) * 2008-12-11 2012-11-27 Micron Technology, Inc. Multilevel encoding with error correction
KR101670922B1 (ko) * 2009-08-07 2016-11-09 삼성전자주식회사 아날로그 신호를 출력하는 불휘발성 메모리 장치 및 그것을 포함하는 메모리 시스템

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07234823A (ja) * 1993-12-28 1995-09-05 Toshiba Corp 記憶システム
US5450363A (en) * 1994-06-02 1995-09-12 Intel Corporation Gray coding for a multilevel cell memory system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04290380A (ja) * 1991-03-19 1992-10-14 Mitsubishi Electric Corp 画像情報伝送方式
US5694356A (en) * 1994-11-02 1997-12-02 Invoice Technology, Inc. High resolution analog storage EPROM and flash EPROM

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07234823A (ja) * 1993-12-28 1995-09-05 Toshiba Corp 記憶システム
US5450363A (en) * 1994-06-02 1995-09-12 Intel Corporation Gray coding for a multilevel cell memory system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HORIGUCHI M ET AL: "AN EXPERIMENTAL LARGE-CAPACITY SEMICONDUCTOR FILE MEMORY USING 16-LEVELS/CELL STORAGE", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 23, no. 1, February 1988 (1988-02-01), pages 27 - 33, XP000649444 *
PATENT ABSTRACTS OF JAPAN vol. 096, no. 001 31 January 1996 (1996-01-31) *

Also Published As

Publication number Publication date
EP0858076A2 (fr) 1998-08-12
US5907504A (en) 1999-05-25
KR100279233B1 (ko) 2001-01-15
JPH10222992A (ja) 1998-08-21
KR19980070013A (ko) 1998-10-26

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