EP0851324B1 - Vorrichtung die als Haupt-/Nebenuhr benutzt werden kann für die Übermittlung der Standardzeit übers Telefonnetz - Google Patents

Vorrichtung die als Haupt-/Nebenuhr benutzt werden kann für die Übermittlung der Standardzeit übers Telefonnetz Download PDF

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Publication number
EP0851324B1
EP0851324B1 EP19960309511 EP96309511A EP0851324B1 EP 0851324 B1 EP0851324 B1 EP 0851324B1 EP 19960309511 EP19960309511 EP 19960309511 EP 96309511 A EP96309511 A EP 96309511A EP 0851324 B1 EP0851324 B1 EP 0851324B1
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EP
European Patent Office
Prior art keywords
time
data
clock
master
interface
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Expired - Lifetime
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EP19960309511
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English (en)
French (fr)
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EP0851324A1 (de
Inventor
Parameswar National Physical Laboratory Banerjee
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Council of Scientific and Industrial Research CSIR
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Council of Scientific and Industrial Research CSIR
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G99/00—Subject matter not provided for in other groups of this subclass
    • G04G99/006—Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G5/00—Setting, i.e. correcting or changing, the time-indication

Definitions

  • This invention relates to a device useful as a master slave clock for transmitting standard time over a telephone network and a telephone network incorporating the device for transmitting and receiving standard time.
  • Time is one of the several basic quantities from which most physical measurement systems are derived. Others are length, mass and temperature. Unlike other physical quantities it cannot be apprehended by any of the physical senses. For example, we can see distance, feel weight or temperature. But we can know time only through consciousness or observing effects.
  • time interval is the duration between two events, or in other words, it is the length of time between two events. Time interval may or may not be associated with a specific date. It is of vital importance for synchronization, the very basic need for efficient communication.
  • the second one specifies the particular time at which an event has occurred or will occur.
  • Time of a day or date is the most often used term. It is usually presented in a brief form of hour, minute and second, whereas a complete statement of time should also include week, day, month and year. It could also extend to units of smaller than the second going down through milliseconds, microseconds, nanoseconds and picoseconds.
  • STFS Time and Frequency Signal
  • US 4,125,993 discloses digital display devices and digital timepieces in which the display is remotely updated.
  • the remote updating signal can be transmitted through telephone means and a single improved digital display device can be utilised as a master in controlling the display of multiple devices.
  • Patent Abstracts of Japan for JP54-041776A discloses a microprocessor system for watches which reduces the power consumption by generating system clocks once every lowest time of the time digits which undergo flow processing in ROM/RAM system.
  • the present invention provides a device useful as a master/slave clock for transmitting standard time over a telephone network, which comprises a pulse generator capable of being synchronized with a standard external clock system, wherein the output of the generator is connected directly to and also through an I/O interface to a CPU having RAM and EPROM, wherein the CPU is connected to a keyboard and to a digital display unit through an interface, and wherein said CPU is connected to an interface capable of making the signals compatible for connecting to a telephone modem, characterized in that the EPROM used contains the main programme for the received mode by enabling the initialising process, if required setting the time, activating the interrupts, and thereafter if required receiving the data checking for locking and the EPROM used contains an interrupt service subroutine (RST 6.5) for transmit mode by running the master/slave clock as a master clock activated by a pulse per second signal, setting time and date if commanded through a key entry, and outputting a data stream advanced by 1 second through a serial output data port following a transmission scheme if operated
  • the main object of the present invention is to provide a device useful as a master/slave clock for transmitting standard time over a telephone network. Another object is to provide a telephone network incorporating the device for transmitting and receiving standard time.
  • synchronization of time is being done through telephone lines.
  • digital data is being generated from a standard clock and is transferred through a telephone line.
  • Uusers may get their clock synchronized to Indian Standard Time (IST) by dialing the number of the dedicated telephone line.
  • Teleclock has its own independent clock based on a good crystal oscillator, which is sufficient to maintain time within one second for a day or two. It has its own automatic dialling system too. It can dial the number and get its clock synchronized to the data transmitted by NPL through a telephone line within few seconds.
  • the clock of the user will then run from its new time automatically as soon as the telephone line is disconnected.
  • the phase of second pulse or one pulse per second (1pps) of the local clock will also be set within few tens of millisecond if we ignore the propagation delay.
  • block 1 is a pulse generator
  • block 2 is a central processing unit (CPU) with Random Access Memory (RAM) and Externally programmable read only memory (EPROM)
  • block 3 is an input/output (I/O) interface
  • block 4 is a key board/display interface
  • block 5 is display unit
  • block 6 is an interface connected to the modem
  • block 7 is a key board.
  • the present invention provides a device useful as a master/slave clock for transmitting standard time over a telephone network which comprises a pulse generator (1) capable of being synchronized with a standard external clock system, the output of the generator (1) being connected directly to and also through an I/O interface (3) to a CPU (2) having RAM and EPROM, the CPU (2) being connected to a key board (7) and to a digital display unit (5) through an interface (4), the said CPU (2) being connected to an interface (6) capable of making the signals compatible for connecting to a telephone modem.
  • the central processing unit used may be a microprocessor such as Intel (8085,8080,8086), Motorola (68000).
  • the block diagram of the telephone network incorporating the device for transmitting and receiving standard time is shown.
  • block S depicts the master clock the details of which is shown in fig. 1 of the drawings
  • block 9 is a modem
  • block 10 is an electronic switch.
  • the present invention provides a telephone network incorporating the device for transmitting and receiving standard time which comprises a master/slave clock (8) connected to a telephone network through a modem (9) and an electronic switch (10) at the transmitting end, a slave clock at the receiving end being connected to the said telephone network through a modem (9).
  • the device of the present invention is a microprocessor based system which functions through a software, intimately related to its hardware arrangements.
  • the system is basically comprised of an independent clock system with a display unit.
  • the output of the clock is connected to a modem through RS232C part.
  • the oscillator is based on standard crystal ( ⁇ IPPM). 1pps (pulse per second) is generated by dividing the oscillator output by the number same as the frequency value of the oscillator.
  • This 1pps actually drives the interrupt subroutine of the microprocessor software to generate the clock (i.e. hour, minute, second) data and to feed them to the display unit.
  • the system functions in either master (i.e. transmit) mode or receive (i.e. slave) mode.
  • the system dials a known telephone number through modem either at a predecided time or on command.
  • the data stream from the transmit/master system starts flowing in.
  • the system accepts the data.
  • the phase of second pulse of the system clock can be set. This can be achieved by generating a software pulse on identifying the special character.
  • the software pulse thus generated is used to reset the clock.
  • the clock data stream available from the modem is used to update the current clock data stored in RAM which in turn is used by clock software. After the clock data is "errorlessly" updated , the telephone line is disconnected by a command through Modem.
  • the system can be in master mode when the system is not linked with telephone line.
  • the clock, system just at the start of the interrupt subroutine, generates the special character virtually coinciding with the phase of the second pulse of the master clock.
  • the master clock can be "constantly" set by external master clock system, if necessary.
  • the system outputs the stream of clock data in a predefined format through RS232C port. This output can be practically linked to the modem when the status of carrier-detect of the modem is ON.
  • the master clock When the clock is in the master mode, the master clock sends out data related to current time through the RS232C port in a definite format so that the receiving slave clock can recognize the pattern.
  • the sequence of characters and data those are sent are as follows:
  • the dividing counter is started by the incoming MASTER clock's 1pps and after pulse shaping, we get a phase shifted 1pps in the SLAVE clock.
  • S", "K” and “G” are signature that precedes the second data (SD), minute data (MD) and hour data (HD) respectively.
  • clock operating in the slave mode it receives the data stream from the RS232C port. Since the data is transmitted serially and the ⁇ p can start intercepting data from any point, the necessity of the signature is felt. That is, when any of this signature is recognized, the following two digits would be assumed to be the corresponding hour, minute or second data.
  • the above data sequence is repeated four times in a second in order to provide enough redundance and confidence in reliability of the data at the receiving end.
  • the carriage return " ⁇ CR> " is not necessary if the receiving end is a slave clock but it is convenient when a computer's internal clock is to be synchronized. However the software is not unduly complicated due to its presence.
  • ⁇ CR> is added after each data. The slave takes two sets of data pertaining to current time out of the transmitted five sets of data in a second. It compares the two sets. If any discrepancy is found it throws the whole data and starts afresh.
  • the 1pps is actually generated from a 5MHz signal.
  • a cascade of frequency divider are used to generate 1pps from 5MHz.
  • a frequency divider we have used IC7490 which is a decade counter.
  • the divider chain has the provision of being reset by a software 1pps and/or hardware 1pps available from the external source.
  • the software pulse helps in aligning the phase of the in built 1pps with that of the received 1pps. This alignment helps in extracting data from the received signal as will be more clarified in the software section.
  • the system has in built 5 MHz crystal oscillator.
  • phase lock loop (PLL - chip IC564) has been used instead of a simple oscillator.
  • the advantage of using the PLL is the following.
  • VCO voltage controlled oscillator
  • Microprocessor related unit is :
  • the system is based on an 8-bit microprocessor.
  • the functional block diagram of the system is shown in fig. 1 of drawings.
  • the main operation of the microprocessor is in its interrupt mode.
  • the interrupt pulse required to run the software is fed from the 1pps signal generator as explained in the later section.
  • the microprocessor based clock system is made compatible to other digital systems like computers by the provision of the RS232C port.
  • This port serially transmits data related to time through serial output data (SOD) port of the microprocessor. Through serial input data (SID), it receives data.
  • SOD serial output data
  • SID serial input data
  • This port is directly connected to RS232C interface.
  • the functional block diagram of a teleclock system shown in fig. 2 comprises of the following main components :
  • the RS232C interfacing is done through two pins of the 8085 ⁇ P. These two pins are the serial I/O pins. Since the RS232C is not compatible with TTL logic so we have used the line driver IC1488 and the line receiver IC1489 for interfacing TTL logic with RS232C.
  • the data out of SOD of ⁇ P 8085 is of TTL logic level.
  • TTL logic In order to make this TTL logic compatible with RS232C it is converted to RS232C by IC 1488.
  • the output voltage level of the line driver is decided by its power supply.
  • the received RS232C signal is converted to TTL logic by the IC 1489 and is fed to the line of the ⁇ P 8085.
  • the RS232C is made compatible with the TTL logic using 1488 and 1489 ICs.
  • 8255 is a general purpose I/O interface. It has been configured for only output port. C-low port of 8255 is used for the generation of 1pps by software means.
  • the 8279 is used for interfacing keyboard/ display. This is done by software means. When day is entered through keyboard, it is stored in the internal FIFO (First In First Out) memory and an interrupt signal is generated with each entry. This interrupt signal is used to interrupt RST 5.5 of the 8085 ⁇ P. The software for running the keyboard interface is written in the ISS of the RST 5.5.
  • FIFO First In First Out
  • the display unit is an eight-unit seven segment LED. These are used to display the current time and the status of the different mode of operation through pre-assigned character.
  • the software of the teleclock system comprises of the main program and two Interrupt Service Subroutine (ISS) RST 6.5 and RST 5.5.
  • ISS Interrupt Service Subroutine
  • the main program (see flow chart in fig.3 )after initialising process enables the interrupts RST 6.5 and RST 5.5 and receives the data from serial port if desired.
  • the initialising process consists of configuring I/O interface 8255, suitably setting the memory areas and setting the current time through the key entry if required. After enabling the interrupts the program lies in a wait loop with a provision of routing to the slave program whenever necessary.
  • the signature of the incoming data is checked. If the incoming signature is "S” then the following data is stored as the second data. Thus after the identification of the signature of "K” and “G” , the minute and hour data are stored respectively. These stored data are used as valid data for time till two consecutive sets of data match exactly.
  • the lock flag is set after the availability of valid data.
  • the basic clock of the system is a software clock run in the interrupt mode through RST 6.5 (see flow chart in fig.4 ).
  • the RST 6.5 is activated by a 1pps signal generated as described in example 2.
  • the ISS RST 6.5 updates the clock. One may set the time according to the key entry.
  • the data stream following the transmission scheme (as described in example 1) is outputted through the SOD port when the system operates in the master mode.
  • the ISS RST 5.5 is executed on entering data through the key board. RST 5.5. ISS actually stores the keyed data in the desired area. The ISS is written in such a way that on pressing the letter "E" the last three data set entered will be displayed on the eight unit 7-segment LED. This has been implemented by the interfacing of ⁇ P 8085 with the 8279.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)

Claims (2)

  1. Vorrichtung zum Einsatz als Master-/Slave-Takt, um eine Standardzeit über ein Telefonnetz zu übertragen, welche einen Pulsgenerator (1) umfasst, welcher mit einem standardisierten externen Taktsystem synchronisierbar ist, wobei der Ausgang des Generators (1) direkt und auch über eine I/O-Schnittstelle (3) mit einer CPU (2) mit einem RAM und einem EPROM verbunden ist, wobei die CPU (2) mit einer Tastatur (7) und mit einer digitalen Anzeigeeinheit (5) über eine Schnittstelle (4) verbunden ist, und wobei die CPU (2) mit einer Schnittstelle (6) verbunden ist, welche in der Lage ist, die Signale kompatibel zur Verbindung mit einem Telefonmodem zu erstellen,
    dadurch gekennzeichnet,
    dass das eingesetzte EPROM die Hauptprogramme für die empfangene Betriebsart enthält, indem der Initialisierungsprozess aktiviert wird, wenn ein Setzen der Zeit erforderlich ist, wobei die Interrupt-Signale aktiviert werden und anschließend, wenn es erforderlich ist, die Eingangsdaten empfangen und überprüft werden und ein Sperrvermerk nach der Verfügbarkeit von gültigen Zeitdaten gesetzt wird, und wobei das eingesetzte EPROM ein Unterbrechungsdienst-Unterprogramm (RST 6.5) für die Übertragungsbetriebsart enthält, indem der Master-/Slave-Takt als ein Master-Takt, welcher durch ein Signal mit einem Puls pro Sekunde aktiviert wird, läuft, wobei Zeit und Datum gesetzt werden, wenn es über eine Tastatureingabe angewiesen wird, und wobei ein Datenstrom, welcher 1 Sekunde vorgesetzt wird, über einen seriellen Ausgangsdatenanschluss ausgegeben wird, wobei einem Übertragungsschema gefolgt wird, wenn in einer Master-Betriebsart gearbeitet wird; wobei das Übertragungsschema ein vordefiniertes Format ist, um Zeichen und Daten in einer Folge von "O", "<CR>", "S", "<CR>", SD, "<CR>", "K", "<CR>", MD, "<CR>", "G", "<CR>", HD, "<CR>" zu senden, wobei Elemente in den Anführungszeichen (" ") selbst Zeichen sind und SD, MD und HD zweistellige Daten der Sekunde, Minute bzw. Stunde sind, wobei "<CR>" das Anweisungszeichen für "Zeilenumschaltung" ist, und wobei das Auftreten von "O" die Phase des Sekundenpulses des Master-Takts anzeigt.
  2. Vorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass die eingesetzte zentrale Verarbeitungseinheit ein Mikroprozessor ist.
EP19960309511 1996-12-27 1996-12-27 Vorrichtung die als Haupt-/Nebenuhr benutzt werden kann für die Übermittlung der Standardzeit übers Telefonnetz Expired - Lifetime EP0851324B1 (de)

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Application Number Priority Date Filing Date Title
EP19960309511 EP0851324B1 (de) 1996-12-27 1996-12-27 Vorrichtung die als Haupt-/Nebenuhr benutzt werden kann für die Übermittlung der Standardzeit übers Telefonnetz

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Application Number Priority Date Filing Date Title
EP19960309511 EP0851324B1 (de) 1996-12-27 1996-12-27 Vorrichtung die als Haupt-/Nebenuhr benutzt werden kann für die Übermittlung der Standardzeit übers Telefonnetz

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EP0851324A1 EP0851324A1 (de) 1998-07-01
EP0851324B1 true EP0851324B1 (de) 2012-06-13

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9225344B2 (en) 2013-01-16 2015-12-29 Altera Corporation Methods and apparatus for aligning clock signals on an integrated circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH1377974A4 (de) * 1974-10-14 1976-10-29
US4125993A (en) * 1976-07-02 1978-11-21 Emile Jr Philip Digital display devices with remote updating
JPS5441776A (en) * 1977-09-08 1979-04-03 Sharp Corp Microprocessor system for watches
CH641923B (fr) * 1980-02-12 Ebauches Sa Montre munie d'un micro-ordinateur.

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