Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector

Definitions

• the present invention relates to a method for monitoring and restoring waveforms, and to an implementation device.
• a sensor such as a photodetector coupled to an optical fiber receives a train of optical pulses, it translates them into electrical pulses.
• the average value of these electrical pulses is not constant. It is linked on the one hand to the occurrence (cadence) and to the levels of the different optical pulses received and, on the other hand, it fluctuates according to the dark current, variable characteristic of the photodetector (according to the temperature especially).
• These electrical pulses restored by the opto-electric conversion element therefore have an offset value (continuous component) which is not stable during the phase of reception of the physical information. The risk being the non-detection of one or more useful optical pulses of low level arriving at the sensor with as a consequence the loss of logical information.
• optical pulses emitted by equipment close to the receiving equipment have a level sufficient to be easily exploited by the receiving equipment while those emitted by remote equipment have a lower level, and when the difference between extreme levels reaches or exceeds 24 dB, the weakest optical pulses arriving immediately after high level pulses may not be taken into account, as specified above. The converse also applies for higher optical pulses arriving immediately after low level pulses.
• the transmitters sending pulses asynchronously, there may occur a more or less significant overlap of the pulses received.
• the receiver can then either not take into account the pulses of lower amplitude partially masked by pulses of higher amplitude and thus not detect the simultaneity of emission of distant transmitters, or misinterpret received signals.
• the present invention relates to a method allowing, in a pulse data transmission system, a single channel, comprising several transmitters and at least at the receiver, to monitor the form and the position of the received signals, in order to detect possible overlaps. of pulses and / or deformations of these pulses, and to restore them in an easily exploitable form.
• the present invention implements a process for monitoring the quality of the trains of pulses received, performing both a time monitoring and a spatial monitoring (waveform ).
• This method is particularly advantageous in the case of multiplex buses for the detection of simultaneous transmission of two or more pieces of equipment.
• the present invention also relates to a device for implementing such a method, a device which is simple, reliable and faithfully reproduces reproducible logical information from the reception scenarios.
• the method according to the invention is characterized in that on reception the signals received are sampled with a sampling period significantly shorter than the duration of the shortest waveforms, that the successive samples of each waveform received with the corresponding samples of stored templates, that a nonconformity signal is produced when a determined number of samples received exceed the limits of the templates, and that in the event of compliance, it is shaped , if necessary, the received waveforms.
• This process therefore comprises two operating phases: the first phase is an offset compensation phase, in particular at power-up and during periods of emission inactivity.
• the second phase is a phase of acquisition by sampling of the physical information received, of analysis and restitution.
• the device according to the invention comprises a circuit for shaping the pulses received connected to a sampling circuit, itself connected to a circuit for detecting synchronization and collision errors.
• FIG. 1 is a block diagram of a device for pulse acquisition and offset correction cooperating with the device according to the invention
• FIG. 2 is a block diagram of the device according to the invention.
• FIG. 3 is a block diagram of an offset control circuit of the device of FIG. 1, in a digital version,
• - Figure 4 is the block diagram of a simplified, analog version of the offset control circuit of the device of Figure 1
• - Figure 5 is an example in time form, sequence of physical information received under form of pulses.
• the present invention is described below with reference to equipment connected to an asynchronous transmission multiplex optical bus such as the ARINC 629 bus, but it is understood that it is not limited to such an application, and that it can be implemented in numerous fields in which one or more transmitters emitting pulses whose shape and / or position can be modified to the point of being badly interpreted or not interpreted at all.
• the device 1 shown in FIG. 1 receives light energy from an optical fiber 2, converted into electrical energy by an opto ⁇ electronic sensor 3 (PIN or photodiode for example).
• This sensor 3 is connected to a circuit 4 of the transimpedance type (current / voltage conversion).
• circuit 4 is connected to the input "+" of an adder 5, the output of which is connected to the analog input of an analog-digital converter 6, which is advantageously of the "Flash" type.
• the output of the converter 6 is connected to a set of circuits 7 for analyzing the received signals and restoring the clock signal, as well as to a set of circuits 8 for controlling the offset of reception.
• the output of the assembly 8 is connected by a digital-analog converter 9 to the input "-" of the adder 5.
• the circuits 6, 7 and 8 receive a clock signal called, in a standard way, "RICKT ".
• Circuit sets 7 and 8 receive the following standardized signals: “RXE”("Receptionenable”),”RXCK” (reception clock signal), and circuit set 7 produces the standardized signals: “RXI” ( Manchester logic receive signal), “RXN” ("Manchester logic reverse reception signal”), as well as the “ERR” signal (Error detection signal see figure 2).
• the assembly 7 comprises, at its input, a circuit 10 for shaping the signals received from the converter 6.
• the signals taken from the bus 2 come from several sources located at different distances from the sensor 3, and have therefore different amplitudes and are deformed differently. The possibility of simultaneous transmission of these distant sources also leads to the presence of different amplitudes and different pulse shapes (Figure 5 for example).
• the circuit 10 transforms them into pulses all having the same amplitude and a standard form, provided that the circuit 11 for signaling the shape of the pulses received and the circuit 12 for monitoring level consistency in the same message (all pulses of the same message, therefore coming from the same source must have substantially the same amplitude, the various intermediate elements being able to bring an attenuation remaining invariable during the duration of a message) recognize as good the pulses received.
• the output of circuit 10 is connected to a sampling circuit 13, itself connected to a circuit 14 for detecting synchronization errors and collision errors (overlapping pulses) causing the triggering of time monitoring.
• the circuit 14 also monitors the temporal coherence of the pulses received, that is to say it checks whether the distances between successive pulses are those predicted in the same message.
• the output of circuit 10 is also connected to a phase detector 15, the sequencing input of which is connected to a clock signal generator 16 (providing signals at a period of 150 ⁇ s in the present example).
• the outputs "phase delay” and “phase advance” of the detector 15 are connected to the control inputs of a clock signal generator 17 (providing signals with a period of 250 nanoseconds in the present example), the output of which is connected to the sequencing input of circuit 13.
• the period of the signals of clock circuit 17 must be much less than that of the pulses arriving at circuit 10, in order to analyze in the most fine possible the pulses received.
• circuit 10 is finally connected to a bus activity detector 18 (in fact detecting the phases of inactivity on the bus), the output of which is connected to the inhibition / activation input of clock 17.
• bus activity detector 18 in fact detecting the phases of inactivity on the bus
• the logic information then restored RXI, RXN being at the low level.
• Circuit 18 also provides direct "Bus Quiet" information used by all of the offset control circuits 8 for the start of each adaptation phase.
• the phase detection carried out by the circuit 15 and the application of an advance or a delay on the clock for sampling and restitution of the logic information are necessary for the compensation of the drift of this clock.
• FIG. 5 shows some examples of waveforms appearing at various points in a system with several transmitters and receivers connected to an optical bus such as the ARINC 629 bus.
• A there are shown some optical pulses such as emitted by a transmitter on the bus and received by the loopback circuit ensuring the monitoring of the emission for example.
• B is represented by the pulses of the same sequence coming from a remote device. These B pulses are not deformed, only their amplitude is reduced (they are homothetic with the corresponding A pulses).
• F there is shown an example of a template used by the invention.
• This template is drawn in solid lines, but in fact, it is stored in sampled form, the sampling period being significantly smaller than the duration of the pulse defined by this template.
• This template is formed by an inner "border” F1 and an outer “border” F2.
• the borders F1 and F2 define between them a zone Z inside which must be all the samples of the same pulse. If at least a determined number of samples (one or more) are outside zone Z, the circuit 14 signals this to the host part of the receiving equipment which takes the necessary measures (alarm, error signal , rejection of the entire message containing the corrupted impulse, request to repeat the message, etc.).
• FIG. 3 shows a digital embodiment of the circuit 8 of FIG. 1.
• the input terminal 19 of this circuit is connected to the output of the converter 6.
• the terminal 19 is connected to three threshold detection circuits, respectively referenced 20, 21 and 22.
• the circuit 20 is adjusted to a threshold below which the pulses received are estimated to be insignificant, during transient periods (in particular when the device is powered up).
• the circuits 21 and 22 are adjusted to thresholds situated respectively slightly above and slightly below a value equal to the output voltage of the circuit established during a period of inactivity on the fiber 2.
• circuit 20 is connected via a circuit 23 for detecting transient phases to a first input of an OR gate 24, the second input of which is connected to a bus inactivity detector, such as circuit 18 in FIG. 2
• the output of the OR 24 is connected to the validation input of a clock pulse generator 25, with a period of 200 ⁇ s in the present example.
• the output of generator 25 is connected to the input of clock signals from an accumulation register 26.
• circuits 21 and 22 are respectively connected to the inputs "-" and "+” of an adder 27, the output of which is connected via an amplifier 28 to a first input of an adder 29, the second input of which is connected to the output of register 26.
• the output of adder 29 is connected to the input of register 26, the output of which is also connected to the output terminal 30 of circuit 8.
• the operation of the device described above is as follows. During the periods of reception of pulse trains circulating on the optical bus 2, the assembly 8 is inhibited (the clock 25 controlling the register 26 is not validated by the output signal from the OR 24. because it is neither the power-up phase or a period of bus inactivity.
• the optical pulses, converted into electrical pulses by the sensor 3, sampled by the CAN converter 6 and controlled by the assembly 7, are sent as signals (RXI, RXN) to the operating circuits, not shown, connected downstream of the set 7.
• a logic validation signal appears at the output of OR gate 24, which releases the clock 25 and validates the register 26.
• a signal appears on one of the outputs of circuits 21 or 22. This signal , amplified at 28, is algebraically added to the previous content of register 26.
• a digital signal is obtained at output 30 of circuit 8 which, after conversion to analog signal by converter 9, makes it possible to slave the DC component of the signal output of circuit 4 at a value (slightly positive in this case) which is such that pulses, even of very small amplitude, occurring after a short period of inactivity of bus 2, can be taken into account .
• the input signal of the converter 6 is, in the absence of the circuit of the invention, superimposed on a DC component which varies slowly with respect to the period of the impulses, which can mask subsequent impulses occurring soon after.
• this continuous component is slaved to a slightly positive value which makes it possible to take into account all the significant pulses (of level comprised between 6mV and 1.5 V in the present case) occurring even little long after the last pulse of a train.
• FIG. 4 shows a simplified embodiment, with analog circuits of the servo circuit.
• the circuit assembly 8 ′ has the same elements 3, 4 and 5 as the assembly 8 in FIG. 3.
• the output of the adder 5 is connected to an amplifier 31 whose output is connected on the one hand to a comparator 32, and secondly, via a switch 33, at the input of an integrating amplifier 34 partially replacing the functionality of circuit 8 and DAC converter 9.
• the output of the amplifier 34 is connected to the input "-" of the adder 5.
• the output of the comparator 32 is connected to a set of circuits T similar to the set 7.
• the detection output bus inactivity of the set T is connected to the control input of switch 33.
• This switch 33 is controlled in such a way that when the bus is active, a zero voltage is applied to the input of the amplifier 34, not involving the application of a modification of the offset compensation, and that when the bus is inactive, the input of the amplifier 34 is connected to the output of the amplifier 31.
• the operation of the assembly 8 'described above is similar to that of the assembly 8.
• the input of the amplifier 34 is at 0 volts, and ensures the maintenance of the value of the offset developed during the previous acquisition phase.
• the input of amplifier 34 is switched to the output of amplifier 31, performing the measurement of the offset present, which forces the output voltage of amplifier 31 to zero. So at the end of the period of inactivity of the bus, the input voltage of the amplifier 34 is practically zero, there is storage by the amplifier as soon as the switch 33 switches, and so on.
• the assembly 8 ' is slower than the circuit assembly 8, in particular because of the reaction times of the amplifiers 31 and 34, but comprises fewer components than the latter, and is therefore less expensive than it.

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• Engineering & Computer Science (AREA)
• Quality & Reliability (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Dc Digital Transmission (AREA)
• Optical Communication System (AREA)

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• 1995
  • 1995-08-11 FR FR9509763A patent/FR2737828B1/fr not_active Expired - Fee Related
• 1996
  • 1996-08-02 CA CA 2226315 patent/CA2226315A1/fr not_active Abandoned
  • 1996-08-02 EP EP96927740A patent/EP0843925A1/de not_active Withdrawn
  • 1996-08-02 WO PCT/FR1996/001241 patent/WO1997007610A1/fr not_active Application Discontinuation

Non-Patent Citations (1)

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